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1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2013-2014 Panasonic Corporation
4  * Copyright (C) 2015-2016 Socionext Inc.
5  */
6 
7 #include <common.h>
8 #include <linux/errno.h>
9 #include <linux/io.h>
10 
11 #include "../init.h"
12 #include "../sc-regs.h"
13 
14 #undef DPLL_SSC_RATE_1PER
15 
uniphier_pro4_dpll_init(const struct uniphier_board_data * bd)16 int uniphier_pro4_dpll_init(const struct uniphier_board_data *bd)
17 {
18 	unsigned int dram_freq = bd->dram_freq;
19 	u32 tmp;
20 
21 	/*
22 	 * Set Frequency
23 	 * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
24 	 * to FOUT ( DPLLCTRL.bit[29:20] )
25 	 */
26 	tmp = readl(SC_DPLLCTRL);
27 	tmp &= ~(0x000f0000);
28 	switch (dram_freq) {
29 	case 1333:
30 		tmp |= 0x000d0000;
31 		break;
32 	case 1600:
33 		tmp |= 0x000c0000;
34 		break;
35 	default:
36 		pr_err("Unsupported frequency");
37 		return -EINVAL;
38 	}
39 
40 	/*
41 	 * Set Moduration rate
42 	 * Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15])
43 	 */
44 #if defined(DPLL_SSC_RATE_1PER)
45 	tmp &= ~0x00008000;
46 #else
47 	tmp |= 0x00008000;
48 #endif
49 	writel(tmp, SC_DPLLCTRL);
50 
51 	tmp = readl(SC_DPLLCTRL2);
52 	tmp |= SC_DPLLCTRL2_NRSTDS;
53 	writel(tmp, SC_DPLLCTRL2);
54 
55 	/* Wait until dpll gets stable */
56 	udelay(500);
57 
58 	return 0;
59 }
60