1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * From coreboot src/soc/intel/broadwell/romstage/power_state.c
4 *
5 * Copyright (C) 2016 Google, Inc.
6 */
7
8 #include <common.h>
9 #include <pci.h>
10 #include <asm/io.h>
11 #include <asm/intel_regs.h>
12 #include <asm/arch/iomap.h>
13 #include <asm/arch/lpc.h>
14 #include <asm/arch/pch.h>
15 #include <asm/arch/pm.h>
16
17 /* Return 0, 3, or 5 to indicate the previous sleep state. */
prev_sleep_state(struct chipset_power_state * ps)18 static int prev_sleep_state(struct chipset_power_state *ps)
19 {
20 /* Default to S0. */
21 int prev_sleep_state = SLEEP_STATE_S0;
22
23 if (ps->pm1_sts & WAK_STS) {
24 switch ((ps->pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) {
25 #if CONFIG_HAVE_ACPI_RESUME
26 case SLP_TYP_S3:
27 prev_sleep_state = SLEEP_STATE_S3;
28 break;
29 #endif
30 case SLP_TYP_S5:
31 prev_sleep_state = SLEEP_STATE_S5;
32 break;
33 }
34 /* Clear SLP_TYP. */
35 outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
36 }
37
38 if (ps->gen_pmcon3 & (PWR_FLR | SUS_PWR_FLR))
39 prev_sleep_state = SLEEP_STATE_S5;
40
41 return prev_sleep_state;
42 }
43
dump_power_state(struct chipset_power_state * ps)44 static void dump_power_state(struct chipset_power_state *ps)
45 {
46 debug("PM1_STS: %04x\n", ps->pm1_sts);
47 debug("PM1_EN: %04x\n", ps->pm1_en);
48 debug("PM1_CNT: %08x\n", ps->pm1_cnt);
49 debug("TCO_STS: %04x %04x\n", ps->tco1_sts, ps->tco2_sts);
50
51 debug("GPE0_STS: %08x %08x %08x %08x\n",
52 ps->gpe0_sts[0], ps->gpe0_sts[1],
53 ps->gpe0_sts[2], ps->gpe0_sts[3]);
54 debug("GPE0_EN: %08x %08x %08x %08x\n",
55 ps->gpe0_en[0], ps->gpe0_en[1],
56 ps->gpe0_en[2], ps->gpe0_en[3]);
57
58 debug("GEN_PMCON: %04x %04x %04x\n",
59 ps->gen_pmcon1, ps->gen_pmcon2, ps->gen_pmcon3);
60
61 debug("Previous Sleep State: S%d\n",
62 ps->prev_sleep_state);
63 }
64
65 /* Fill power state structure from ACPI PM registers */
power_state_get(struct udevice * pch_dev,struct chipset_power_state * ps)66 void power_state_get(struct udevice *pch_dev, struct chipset_power_state *ps)
67 {
68 ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
69 ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN);
70 ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
71 ps->tco1_sts = inw(ACPI_BASE_ADDRESS + TCO1_STS);
72 ps->tco2_sts = inw(ACPI_BASE_ADDRESS + TCO2_STS);
73 ps->gpe0_sts[0] = inl(ACPI_BASE_ADDRESS + GPE0_STS(0));
74 ps->gpe0_sts[1] = inl(ACPI_BASE_ADDRESS + GPE0_STS(1));
75 ps->gpe0_sts[2] = inl(ACPI_BASE_ADDRESS + GPE0_STS(2));
76 ps->gpe0_sts[3] = inl(ACPI_BASE_ADDRESS + GPE0_STS(3));
77 ps->gpe0_en[0] = inl(ACPI_BASE_ADDRESS + GPE0_EN(0));
78 ps->gpe0_en[1] = inl(ACPI_BASE_ADDRESS + GPE0_EN(1));
79 ps->gpe0_en[2] = inl(ACPI_BASE_ADDRESS + GPE0_EN(2));
80 ps->gpe0_en[3] = inl(ACPI_BASE_ADDRESS + GPE0_EN(3));
81
82 dm_pci_read_config16(pch_dev, GEN_PMCON_1, &ps->gen_pmcon1);
83 dm_pci_read_config16(pch_dev, GEN_PMCON_2, &ps->gen_pmcon2);
84 dm_pci_read_config16(pch_dev, GEN_PMCON_3, &ps->gen_pmcon3);
85
86 ps->prev_sleep_state = prev_sleep_state(ps);
87
88 dump_power_state(ps);
89 }
90