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1 /*
2  * Copyright (C) 2016 Freescale Semiconductor, Inc.
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  *
8  */
9 
10 #ifndef __DT_BINDINGS_CLOCK_IMX7ULP_H
11 #define __DT_BINDINGS_CLOCK_IMX7ULP_H
12 
13 #define IMX7ULP_CLK_DUMMY		0
14 #define IMX7ULP_CLK_CKIL		1
15 #define IMX7ULP_CLK_OSC			2
16 #define IMX7ULP_CLK_FIRC		3
17 
18 /* SCG1 */
19 #define IMX7ULP_CLK_SPLL_PRE_SEL	4
20 #define IMX7ULP_CLK_SPLL_PRE_DIV	5
21 #define IMX7ULP_CLK_SPLL		6
22 #define IMX7ULP_CLK_SPLL_POST_DIV1	7
23 #define IMX7ULP_CLK_SPLL_POST_DIV2	8
24 #define IMX7ULP_CLK_SPLL_PFD0		9
25 #define IMX7ULP_CLK_SPLL_PFD1		10
26 #define IMX7ULP_CLK_SPLL_PFD2		11
27 #define IMX7ULP_CLK_SPLL_PFD3		12
28 #define IMX7ULP_CLK_SPLL_PFD_SEL	13
29 #define IMX7ULP_CLK_SPLL_SEL		14
30 #define IMX7ULP_CLK_APLL_PRE_SEL	15
31 #define IMX7ULP_CLK_APLL_PRE_DIV	16
32 #define IMX7ULP_CLK_APLL		17
33 #define IMX7ULP_CLK_APLL_POST_DIV1	18
34 #define IMX7ULP_CLK_APLL_POST_DIV2	19
35 #define IMX7ULP_CLK_APLL_PFD0		20
36 #define IMX7ULP_CLK_APLL_PFD1		21
37 #define IMX7ULP_CLK_APLL_PFD2		22
38 #define IMX7ULP_CLK_APLL_PFD3		23
39 #define IMX7ULP_CLK_APLL_PFD_SEL	24
40 #define IMX7ULP_CLK_APLL_SEL		25
41 #define IMX7ULP_CLK_UPLL		26
42 #define IMX7ULP_CLK_SYS_SEL		27
43 #define IMX7ULP_CLK_CORE_DIV		28
44 #define IMX7ULP_CLK_BUS_DIV		29
45 #define IMX7ULP_CLK_PLAT_DIV		30
46 #define IMX7ULP_CLK_DDR_SEL		31
47 #define IMX7ULP_CLK_DDR_DIV		32
48 #define IMX7ULP_CLK_NIC_SEL		33
49 #define IMX7ULP_CLK_NIC0_DIV		34
50 #define IMX7ULP_CLK_GPU_DIV		35
51 #define IMX7ULP_CLK_NIC1_DIV		36
52 #define IMX7ULP_CLK_NIC1_BUS_DIV	37
53 #define IMX7ULP_CLK_NIC1_EXT_DIV	38
54 
55 /* PCG2 */
56 #define IMX7ULP_CLK_DMA1		39
57 #define IMX7ULP_CLK_RGPIO2P1		40
58 #define IMX7ULP_CLK_FLEXBUS		41
59 #define IMX7ULP_CLK_SEMA42_1		42
60 #define IMX7ULP_CLK_DMA_MUX1		43
61 #define IMX7ULP_CLK_SNVS		44
62 #define IMX7ULP_CLK_CAAM		45
63 #define IMX7ULP_CLK_LPTPM4		46
64 #define IMX7ULP_CLK_LPTPM5		47
65 #define IMX7ULP_CLK_LPIT1		48
66 #define IMX7ULP_CLK_LPSPI2		49
67 #define IMX7ULP_CLK_LPSPI3		50
68 #define IMX7ULP_CLK_LPI2C4		51
69 #define IMX7ULP_CLK_LPI2C5		52
70 #define IMX7ULP_CLK_LPUART4		53
71 #define IMX7ULP_CLK_LPUART5		54
72 #define IMX7ULP_CLK_FLEXIO1		55
73 #define IMX7ULP_CLK_USB0		56
74 #define IMX7ULP_CLK_USB1		57
75 #define IMX7ULP_CLK_USB_PHY		58
76 #define IMX7ULP_CLK_USB_PL301		59
77 #define IMX7ULP_CLK_USDHC0		60
78 #define IMX7ULP_CLK_USDHC1		61
79 #define IMX7ULP_CLK_WDG1		62
80 #define IMX7ULP_CLK_WDG2		63
81 
82 /* PCG3 */
83 #define IMX7ULP_CLK_LPTPM6		64
84 #define IMX7ULP_CLK_LPTPM7		65
85 #define IMX7ULP_CLK_LPI2C6		66
86 #define IMX7ULP_CLK_LPI2C7		67
87 #define IMX7ULP_CLK_LPUART6		68
88 #define IMX7ULP_CLK_LPUART7		69
89 #define IMX7ULP_CLK_VIU			70
90 #define IMX7ULP_CLK_DSI			71
91 #define IMX7ULP_CLK_LCDIF		72
92 #define IMX7ULP_CLK_MMDC		73
93 #define IMX7ULP_CLK_PCTLC		74
94 #define IMX7ULP_CLK_PCTLD		75
95 #define IMX7ULP_CLK_PCTLE		76
96 #define IMX7ULP_CLK_PCTLF		77
97 #define IMX7ULP_CLK_GPU3D		78
98 #define IMX7ULP_CLK_GPU2D		79
99 
100 #define IMX7ULP_CLK_MIPI_PLL		80
101 #define IMX7ULP_CLK_SIRC		81
102 
103 #define IMX7ULP_CLK_SCG1_CLKOUT		82
104 
105 #define IMX7ULP_CLK_END			83
106 
107 /*cm4 clocks*/
108 #define IMX7ULP_CM4_CLK_DUMMY		0
109 #define IMX7ULP_CM4_CLK_CKIL		1
110 #define IMX7ULP_CM4_CLK_OSC		2
111 #define IMX7ULP_CM4_CLK_FIRC		3
112 #define IMX7ULP_CM4_CLK_SIRC		4
113 
114 /* SCG0 */
115 #define IMX7ULP_CM4_CLK_SPLL_VCO_PRE_SEL	5
116 #define IMX7ULP_CM4_CLK_SPLL_VCO_PRE_DIV	6
117 #define IMX7ULP_CM4_CLK_SPLL		7
118 #define IMX7ULP_CM4_CLK_SPLL_VCO	8
119 #define IMX7ULP_CM4_CLK_SPLL_VCO_POST_DIV1	9
120 #define IMX7ULP_CM4_CLK_SPLL_VCO_POST_DIV2	10
121 #define IMX7ULP_CM4_CLK_SPLL_PFD0	11
122 #define IMX7ULP_CM4_CLK_SPLL_PFD1	12
123 #define IMX7ULP_CM4_CLK_SPLL_PFD2	13
124 #define IMX7ULP_CM4_CLK_SPLL_PFD3	14
125 #define IMX7ULP_CM4_CLK_SPLL_PFD_SEL	15
126 #define IMX7ULP_CM4_CLK_SPLL_PFD	16
127 #define IMX7ULP_CM4_CLK_SPLL_SEL	17
128 #define IMX7ULP_CM4_CLK_APLL_VCO_PRE_SEL	18
129 #define IMX7ULP_CM4_CLK_APLL_VCO_PRE_DIV	19
130 #define IMX7ULP_CM4_CLK_APLL		20
131 #define IMX7ULP_CM4_CLK_APLL_VCO	21
132 #define IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV1	22
133 #define IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV2	23
134 #define IMX7ULP_CM4_CLK_APLL_PFD0	24
135 #define IMX7ULP_CM4_CLK_APLL_PFD1	25
136 #define IMX7ULP_CM4_CLK_APLL_PFD2	26
137 #define IMX7ULP_CM4_CLK_APLL_PFD3	27
138 #define IMX7ULP_CM4_CLK_APLL_PFD_SEL	28
139 #define IMX7ULP_CM4_CLK_APLL_PFD	29
140 #define IMX7ULP_CM4_CLK_APLL_SEL	30
141 #define IMX7ULP_CM4_CLK_APLL_PFD0_PRE_DIV	31
142 #define IMX7ULP_CM4_CLK_SYS_SEL		32
143 #define IMX7ULP_CM4_CLK_CORE_DIV	33
144 #define IMX7ULP_CM4_CLK_BUS_DIV		34
145 #define IMX7ULP_CM4_CLK_PLAT_DIV	35
146 #define IMX7ULP_CM4_CLK_SLOW_DIV	36
147 
148 #define IMX7ULP_CM4_CLK_SAI0_SEL	37
149 #define IMX7ULP_CM4_CLK_SAI0_DIV	38
150 #define IMX7ULP_CM4_CLK_SAI0_ROOT	39
151 #define IMX7ULP_CM4_CLK_SAI0_IPG	40
152 #define IMX7ULP_CM4_CLK_SAI1_SEL	41
153 #define IMX7ULP_CM4_CLK_SAI1_DIV	42
154 #define IMX7ULP_CM4_CLK_SAI1_ROOT	43
155 #define IMX7ULP_CM4_CLK_SAI1_IPG	44
156 
157 #define IMX7ULP_CLK_SCG0_CLKOUT		45
158 
159 #define IMX7ULP_CM4_CLK_END		46
160 
161 #endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */
162