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1 /*
2  * Copyright 2016 Freescale Semiconductor, Inc.
3  * Copyright 2017 NXP
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License version 2 as
7  * published by the Free Software Foundation.
8  */
9 
10 #ifndef __DT_BINDINGS_CLOCK_IMX8MQ_H
11 #define __DT_BINDINGS_CLOCK_IMX8MQ_H
12 
13 #define IMX8MQ_CLK_DUMMY		0
14 #define IMX8MQ_CLK_32K			1
15 #define IMX8MQ_CLK_25M			2
16 #define IMX8MQ_CLK_27M			3
17 #define IMX8MQ_CLK_EXT1			4
18 #define IMX8MQ_CLK_EXT2			5
19 #define IMX8MQ_CLK_EXT3			6
20 #define IMX8MQ_CLK_EXT4			7
21 
22 /* ANAMIX PLL clocks */
23 /* FRAC PLLs */
24 /* ARM PLL */
25 #define IMX8MQ_ARM_PLL_REF_SEL		8
26 #define IMX8MQ_ARM_PLL_REF_DIV		9
27 #define IMX8MQ_ARM_PLL			10
28 #define IMX8MQ_ARM_PLL_BYPASS		11
29 #define IMX8MQ_ARM_PLL_OUT		12
30 
31 /* GPU PLL */
32 #define IMX8MQ_GPU_PLL_REF_SEL		13
33 #define IMX8MQ_GPU_PLL_REF_DIV		14
34 #define IMX8MQ_GPU_PLL			15
35 #define IMX8MQ_GPU_PLL_BYPASS		16
36 #define IMX8MQ_GPU_PLL_OUT		17
37 
38 /* VPU PLL */
39 #define IMX8MQ_VPU_PLL_REF_SEL		18
40 #define IMX8MQ_VPU_PLL_REF_DIV		19
41 #define IMX8MQ_VPU_PLL			20
42 #define IMX8MQ_VPU_PLL_BYPASS		21
43 #define IMX8MQ_VPU_PLL_OUT		22
44 
45 /* AUDIO PLL1 */
46 #define IMX8MQ_AUDIO_PLL1_REF_SEL	23
47 #define IMX8MQ_AUDIO_PLL1_REF_DIV	24
48 #define IMX8MQ_AUDIO_PLL1		25
49 #define IMX8MQ_AUDIO_PLL1_BYPASS	26
50 #define IMX8MQ_AUDIO_PLL1_OUT		27
51 
52 /* AUDIO PLL2 */
53 #define IMX8MQ_AUDIO_PLL2_REF_SEL	28
54 #define IMX8MQ_AUDIO_PLL2_REF_DIV	29
55 #define IMX8MQ_AUDIO_PLL2		30
56 #define IMX8MQ_AUDIO_PLL2_BYPASS	31
57 #define IMX8MQ_AUDIO_PLL2_OUT		32
58 
59 /* VIDEO PLL1 */
60 #define IMX8MQ_VIDEO_PLL1_REF_SEL	33
61 #define IMX8MQ_VIDEO_PLL1_REF_DIV	34
62 #define IMX8MQ_VIDEO_PLL1		35
63 #define IMX8MQ_VIDEO_PLL1_BYPASS	36
64 #define IMX8MQ_VIDEO_PLL1_OUT		37
65 
66 /* SYS1 PLL */
67 #define IMX8MQ_SYS1_PLL1_REF_SEL	38
68 #define IMX8MQ_SYS1_PLL1_REF_DIV	39
69 #define IMX8MQ_SYS1_PLL1		40
70 #define IMX8MQ_SYS1_PLL1_OUT		41
71 #define IMX8MQ_SYS1_PLL1_OUT_DIV	42
72 #define IMX8MQ_SYS1_PLL2		43
73 #define IMX8MQ_SYS1_PLL2_DIV		44
74 #define IMX8MQ_SYS1_PLL2_OUT		45
75 
76 /* SYS2 PLL */
77 #define IMX8MQ_SYS2_PLL1_REF_SEL	46
78 #define IMX8MQ_SYS2_PLL1_REF_DIV	47
79 #define IMX8MQ_SYS2_PLL1		48
80 #define IMX8MQ_SYS2_PLL1_OUT		49
81 #define IMX8MQ_SYS2_PLL1_OUT_DIV	50
82 #define IMX8MQ_SYS2_PLL2		51
83 #define IMX8MQ_SYS2_PLL2_DIV		52
84 #define IMX8MQ_SYS2_PLL2_OUT		53
85 
86 /* SYS3 PLL */
87 #define IMX8MQ_SYS3_PLL1_REF_SEL	54
88 #define IMX8MQ_SYS3_PLL1_REF_DIV	55
89 #define IMX8MQ_SYS3_PLL1		56
90 #define IMX8MQ_SYS3_PLL1_OUT		57
91 #define IMX8MQ_SYS3_PLL1_OUT_DIV	58
92 #define IMX8MQ_SYS3_PLL2		59
93 #define IMX8MQ_SYS3_PLL2_DIV		60
94 #define IMX8MQ_SYS3_PLL2_OUT		61
95 
96 /* DRAM PLL */
97 #define IMX8MQ_DRAM_PLL1_REF_SEL	62
98 #define IMX8MQ_DRAM_PLL1_REF_DIV	63
99 #define IMX8MQ_DRAM_PLL1		64
100 #define IMX8MQ_DRAM_PLL1_OUT		65
101 #define IMX8MQ_DRAM_PLL1_OUT_DIV	66
102 #define IMX8MQ_DRAM_PLL2		67
103 #define IMX8MQ_DRAM_PLL2_DIV		68
104 #define IMX8MQ_DRAM_PLL2_OUT		69
105 
106 /* SYS PLL DIV */
107 #define IMX8MQ_SYS1_PLL_40M		70
108 #define IMX8MQ_SYS1_PLL_80M		71
109 #define IMX8MQ_SYS1_PLL_100M		72
110 #define IMX8MQ_SYS1_PLL_133M		73
111 #define IMX8MQ_SYS1_PLL_160M		74
112 #define IMX8MQ_SYS1_PLL_200M		75
113 #define IMX8MQ_SYS1_PLL_266M		76
114 #define IMX8MQ_SYS1_PLL_400M		77
115 #define IMX8MQ_SYS1_PLL_800M		78
116 
117 #define IMX8MQ_SYS2_PLL_50M		79
118 #define IMX8MQ_SYS2_PLL_100M		80
119 #define IMX8MQ_SYS2_PLL_125M		81
120 #define IMX8MQ_SYS2_PLL_166M		82
121 #define IMX8MQ_SYS2_PLL_200M		83
122 #define IMX8MQ_SYS2_PLL_250M		84
123 #define IMX8MQ_SYS2_PLL_333M		85
124 #define IMX8MQ_SYS2_PLL_500M		86
125 #define IMX8MQ_SYS2_PLL_1000M		87
126 
127 /* CCM ROOT clocks */
128 /* A53 */
129 #define IMX8MQ_CLK_A53_SRC		88
130 #define IMX8MQ_CLK_A53_CG		89
131 #define IMX8MQ_CLK_A53_DIV		90
132 /* M4 */
133 #define IMX8MQ_CLK_M4_SRC		91
134 #define IMX8MQ_CLK_M4_CG		92
135 #define IMX8MQ_CLK_M4_DIV		93
136 /* VPU */
137 #define IMX8MQ_CLK_VPU_SRC		94
138 #define IMX8MQ_CLK_VPU_CG		95
139 #define IMX8MQ_CLK_VPU_DIV		96
140 /* GPU CORE */
141 #define IMX8MQ_CLK_GPU_CORE_SRC		97
142 #define IMX8MQ_CLK_GPU_CORE_CG		98
143 #define IMX8MQ_CLK_GPU_CORE_DIV		99
144 /* GPU SHADER */
145 #define IMX8MQ_CLK_GPU_SHADER_SRC	100
146 #define IMX8MQ_CLK_GPU_SHADER_CG	101
147 #define IMX8MQ_CLK_GPU_SHADER_DIV	102
148 
149 /* BUS TYPE */
150 /* MAIN AXI */
151 #define IMX8MQ_CLK_MAIN_AXI_SRC		103
152 #define IMX8MQ_CLK_MAIN_AXI_CG		104
153 #define IMX8MQ_CLK_MAIN_AXI_PRE_DIV	105
154 #define IMX8MQ_CLK_MAIN_AXI_DIV		106
155 /* ENET AXI */
156 #define IMX8MQ_CLK_ENET_AXI_SRC		107
157 #define IMX8MQ_CLK_ENET_AXI_CG		108
158 #define IMX8MQ_CLK_ENET_AXI_PRE_DIV	109
159 #define IMX8MQ_CLK_ENET_AXI_DIV		110
160 /* NAND_USDHC_BUS */
161 #define IMX8MQ_CLK_NAND_USDHC_BUS_SRC		111
162 #define IMX8MQ_CLK_NAND_USDHC_BUS_CG		112
163 #define IMX8MQ_CLK_NAND_USDHC_BUS_PRE_DIV	113
164 #define IMX8MQ_CLK_NAND_USDHC_BUS_DIV		114
165 /* VPU BUS */
166 #define IMX8MQ_CLK_VPU_BUS_SRC			115
167 #define IMX8MQ_CLK_VPU_BUS_CG			116
168 #define IMX8MQ_CLK_VPU_BUS_PRE_DIV		117
169 #define IMX8MQ_CLK_VPU_BUS_DIV			118
170 /* DISP_AXI */
171 #define IMX8MQ_CLK_DISP_AXI_SRC			119
172 #define IMX8MQ_CLK_DISP_AXI_CG			120
173 #define IMX8MQ_CLK_DISP_AXI_PRE_DIV		121
174 #define IMX8MQ_CLK_DISP_AXI_DIV			122
175 /* DISP APB */
176 #define IMX8MQ_CLK_DISP_APB_SRC			123
177 #define IMX8MQ_CLK_DISP_APB_CG			124
178 #define IMX8MQ_CLK_DISP_APB_PRE_DIV		125
179 #define IMX8MQ_CLK_DISP_APB_DIV			126
180 /* DISP RTRM */
181 #define IMX8MQ_CLK_DISP_RTRM_SRC		127
182 #define IMX8MQ_CLK_DISP_RTRM_CG			128
183 #define IMX8MQ_CLK_DISP_RTRM_PRE_DIV		129
184 #define IMX8MQ_CLK_DISP_RTRM_DIV		130
185 /* USB_BUS */
186 #define IMX8MQ_CLK_USB_BUS_SRC			131
187 #define IMX8MQ_CLK_USB_BUS_CG			132
188 #define IMX8MQ_CLK_USB_BUS_PRE_DIV		133
189 #define IMX8MQ_CLK_USB_BUS_DIV			134
190 /* GPU_AXI */
191 #define IMX8MQ_CLK_GPU_AXI_SRC			135
192 #define IMX8MQ_CLK_GPU_AXI_CG			136
193 #define IMX8MQ_CLK_GPU_AXI_PRE_DIV		137
194 #define IMX8MQ_CLK_GPU_AXI_DIV			138
195 /* GPU_AHB */
196 #define IMX8MQ_CLK_GPU_AHB_SRC			139
197 #define IMX8MQ_CLK_GPU_AHB_CG			140
198 #define IMX8MQ_CLK_GPU_AHB_PRE_DIV		141
199 #define IMX8MQ_CLK_GPU_AHB_DIV			142
200 /* NOC */
201 #define IMX8MQ_CLK_NOC_SRC			143
202 #define IMX8MQ_CLK_NOC_CG			144
203 #define IMX8MQ_CLK_NOC_PRE_DIV			145
204 #define IMX8MQ_CLK_NOC_DIV			146
205 /* NOC_APB */
206 #define IMX8MQ_CLK_NOC_APB_SRC			147
207 #define IMX8MQ_CLK_NOC_APB_CG			148
208 #define IMX8MQ_CLK_NOC_APB_PRE_DIV		149
209 #define IMX8MQ_CLK_NOC_APB_DIV			150
210 
211 /* AHB */
212 #define IMX8MQ_CLK_AHB_SRC			151
213 #define IMX8MQ_CLK_AHB_CG			152
214 #define IMX8MQ_CLK_AHB_PRE_DIV			153
215 #define IMX8MQ_CLK_AHB_DIV			154
216 /* AUDIO AHB */
217 #define IMX8MQ_CLK_AUDIO_AHB_SRC		155
218 #define IMX8MQ_CLK_AUDIO_AHB_CG			156
219 #define IMX8MQ_CLK_AUDIO_AHB_PRE_DIV		157
220 #define IMX8MQ_CLK_AUDIO_AHB_DIV		158
221 
222 /* DRAM_ALT */
223 #define IMX8MQ_CLK_DRAM_ALT_SRC			159
224 #define IMX8MQ_CLK_DRAM_ALT_CG			160
225 #define IMX8MQ_CLK_DRAM_ALT_PRE_DIV		161
226 #define IMX8MQ_CLK_DRAM_ALT_DIV			162
227 /* DRAM APB */
228 #define IMX8MQ_CLK_DRAM_APB_SRC			163
229 #define IMX8MQ_CLK_DRAM_APB_CG			164
230 #define IMX8MQ_CLK_DRAM_APB_PRE_DIV		165
231 #define IMX8MQ_CLK_DRAM_APB_DIV			166
232 /* VPU_G1 */
233 #define IMX8MQ_CLK_VPU_G1_SRC			167
234 #define IMX8MQ_CLK_VPU_G1_CG			168
235 #define IMX8MQ_CLK_VPU_G1_PRE_DIV		169
236 #define IMX8MQ_CLK_VPU_G1_DIV			170
237 /* VPU_G2 */
238 #define IMX8MQ_CLK_VPU_G2_SRC			171
239 #define IMX8MQ_CLK_VPU_G2_CG			172
240 #define IMX8MQ_CLK_VPU_G2_PRE_DIV		173
241 #define IMX8MQ_CLK_VPU_G2_DIV			174
242 /* DISP_DTRC */
243 #define IMX8MQ_CLK_DISP_DTRC_SRC		175
244 #define IMX8MQ_CLK_DISP_DTRC_CG			176
245 #define IMX8MQ_CLK_DISP_DTRC_PRE_DIV		177
246 #define IMX8MQ_CLK_DISP_DTRC_DIV		178
247 /* DISP_DC8000 */
248 #define IMX8MQ_CLK_DISP_DC8000_SRC		179
249 #define IMX8MQ_CLK_DISP_DC8000_CG		180
250 #define IMX8MQ_CLK_DISP_DC8000_PRE_DIV		181
251 #define IMX8MQ_CLK_DISP_DC8000_DIV		182
252 /* PCIE_CTRL */
253 #define IMX8MQ_CLK_PCIE1_CTRL_SRC		183
254 #define IMX8MQ_CLK_PCIE1_CTRL_CG		184
255 #define IMX8MQ_CLK_PCIE1_CTRL_PRE_DIV		185
256 #define IMX8MQ_CLK_PCIE1_CTRL_DIV		186
257 /* PCIE_PHY */
258 #define IMX8MQ_CLK_PCIE1_PHY_SRC		187
259 #define IMX8MQ_CLK_PCIE1_PHY_CG			188
260 #define IMX8MQ_CLK_PCIE1_PHY_PRE_DIV		189
261 #define IMX8MQ_CLK_PCIE1_PHY_DIV		190
262 /* PCIE_AUX */
263 #define IMX8MQ_CLK_PCIE1_AUX_SRC		191
264 #define IMX8MQ_CLK_PCIE1_AUX_CG			192
265 #define IMX8MQ_CLK_PCIE1_AUX_PRE_DIV		193
266 #define IMX8MQ_CLK_PCIE1_AUX_DIV		194
267 /* DC_PIXEL */
268 #define IMX8MQ_CLK_DC_PIXEL_SRC			195
269 #define IMX8MQ_CLK_DC_PIXEL_CG			196
270 #define IMX8MQ_CLK_DC_PIXEL_PRE_DIV		197
271 #define IMX8MQ_CLK_DC_PIXEL_DIV			198
272 /* LCDIF_PIXEL */
273 #define IMX8MQ_CLK_LCDIF_PIXEL_SRC		199
274 #define IMX8MQ_CLK_LCDIF_PIXEL_CG		200
275 #define IMX8MQ_CLK_LCDIF_PIXEL_PRE_DIV		201
276 #define IMX8MQ_CLK_LCDIF_PIXEL_DIV		202
277 /* SAI1~6 */
278 #define IMX8MQ_CLK_SAI1_SRC			203
279 #define IMX8MQ_CLK_SAI1_CG			204
280 #define IMX8MQ_CLK_SAI1_PRE_DIV			205
281 #define IMX8MQ_CLK_SAI1_DIV			206
282 
283 #define IMX8MQ_CLK_SAI2_SRC			207
284 #define IMX8MQ_CLK_SAI2_CG			208
285 #define IMX8MQ_CLK_SAI2_PRE_DIV			209
286 #define IMX8MQ_CLK_SAI2_DIV			210
287 
288 #define IMX8MQ_CLK_SAI3_SRC			211
289 #define IMX8MQ_CLK_SAI3_CG			212
290 #define IMX8MQ_CLK_SAI3_PRE_DIV			213
291 #define IMX8MQ_CLK_SAI3_DIV			214
292 
293 #define IMX8MQ_CLK_SAI4_SRC			215
294 #define IMX8MQ_CLK_SAI4_CG			216
295 #define IMX8MQ_CLK_SAI4_PRE_DIV			217
296 #define IMX8MQ_CLK_SAI4_DIV			218
297 
298 #define IMX8MQ_CLK_SAI5_SRC			219
299 #define IMX8MQ_CLK_SAI5_CG			220
300 #define IMX8MQ_CLK_SAI5_PRE_DIV			221
301 #define IMX8MQ_CLK_SAI5_DIV			222
302 
303 #define IMX8MQ_CLK_SAI6_SRC			223
304 #define IMX8MQ_CLK_SAI6_CG			224
305 #define IMX8MQ_CLK_SAI6_PRE_DIV			225
306 #define IMX8MQ_CLK_SAI6_DIV			226
307 /* SPDIF1 */
308 #define IMX8MQ_CLK_SPDIF1_SRC			227
309 #define IMX8MQ_CLK_SPDIF1_CG			228
310 #define IMX8MQ_CLK_SPDIF1_PRE_DIV		229
311 #define IMX8MQ_CLK_SPDIF1_DIV			230
312 /* SPDIF2 */
313 #define IMX8MQ_CLK_SPDIF2_SRC			231
314 #define IMX8MQ_CLK_SPDIF2_CG			232
315 #define IMX8MQ_CLK_SPDIF2_PRE_DIV		233
316 #define IMX8MQ_CLK_SPDIF2_DIV			234
317 /* ENET_REF */
318 #define IMX8MQ_CLK_ENET_REF_SRC			235
319 #define IMX8MQ_CLK_ENET_REF_CG			236
320 #define IMX8MQ_CLK_ENET_REF_PRE_DIV		237
321 #define IMX8MQ_CLK_ENET_REF_DIV			238
322 /* ENET_TIMER */
323 #define IMX8MQ_CLK_ENET_TIMER_SRC		239
324 #define IMX8MQ_CLK_ENET_TIMER_CG		240
325 #define IMX8MQ_CLK_ENET_TIMER_PRE_DIV		241
326 #define IMX8MQ_CLK_ENET_TIMER_DIV		242
327 /* ENET_PHY */
328 #define IMX8MQ_CLK_ENET_PHY_REF_SRC		243
329 #define IMX8MQ_CLK_ENET_PHY_REF_CG		244
330 #define IMX8MQ_CLK_ENET_PHY_REF_PRE_DIV		245
331 #define IMX8MQ_CLK_ENET_PHY_REF_DIV		246
332 /* NAND */
333 #define IMX8MQ_CLK_NAND_SRC			247
334 #define IMX8MQ_CLK_NAND_CG			248
335 #define IMX8MQ_CLK_NAND_PRE_DIV			249
336 #define IMX8MQ_CLK_NAND_DIV			250
337 /* QSPI */
338 #define IMX8MQ_CLK_QSPI_SRC			251
339 #define IMX8MQ_CLK_QSPI_CG			252
340 #define IMX8MQ_CLK_QSPI_PRE_DIV			253
341 #define IMX8MQ_CLK_QSPI_DIV			254
342 /* USDHC1 */
343 #define IMX8MQ_CLK_USDHC1_SRC			255
344 #define IMX8MQ_CLK_USDHC1_CG			256
345 #define IMX8MQ_CLK_USDHC1_PRE_DIV		257
346 #define IMX8MQ_CLK_USDHC1_DIV			258
347 /* USDHC2 */
348 #define IMX8MQ_CLK_USDHC2_SRC			259
349 #define IMX8MQ_CLK_USDHC2_CG			260
350 #define IMX8MQ_CLK_USDHC2_PRE_DIV		261
351 #define IMX8MQ_CLK_USDHC2_DIV			262
352 /* I2C1 */
353 #define IMX8MQ_CLK_I2C1_SRC			263
354 #define IMX8MQ_CLK_I2C1_CG			264
355 #define IMX8MQ_CLK_I2C1_PRE_DIV			265
356 #define IMX8MQ_CLK_I2C1_DIV			266
357 /* I2C2 */
358 #define IMX8MQ_CLK_I2C2_SRC			267
359 #define IMX8MQ_CLK_I2C2_CG			268
360 #define IMX8MQ_CLK_I2C2_PRE_DIV			269
361 #define IMX8MQ_CLK_I2C2_DIV			270
362 /* I2C3 */
363 #define IMX8MQ_CLK_I2C3_SRC			271
364 #define IMX8MQ_CLK_I2C3_CG			272
365 #define IMX8MQ_CLK_I2C3_PRE_DIV			273
366 #define IMX8MQ_CLK_I2C3_DIV			274
367 /* I2C4 */
368 #define IMX8MQ_CLK_I2C4_SRC			275
369 #define IMX8MQ_CLK_I2C4_CG			276
370 #define IMX8MQ_CLK_I2C4_PRE_DIV			277
371 #define IMX8MQ_CLK_I2C4_DIV			278
372 /* UART1 */
373 #define IMX8MQ_CLK_UART1_SRC			279
374 #define IMX8MQ_CLK_UART1_CG			280
375 #define IMX8MQ_CLK_UART1_PRE_DIV		281
376 #define IMX8MQ_CLK_UART1_DIV			282
377 /* UART2 */
378 #define IMX8MQ_CLK_UART2_SRC			283
379 #define IMX8MQ_CLK_UART2_CG			284
380 #define IMX8MQ_CLK_UART2_PRE_DIV		285
381 #define IMX8MQ_CLK_UART2_DIV			286
382 /* UART3 */
383 #define IMX8MQ_CLK_UART3_SRC			287
384 #define IMX8MQ_CLK_UART3_CG			288
385 #define IMX8MQ_CLK_UART3_PRE_DIV		289
386 #define IMX8MQ_CLK_UART3_DIV			290
387 /* UART4 */
388 #define IMX8MQ_CLK_UART4_SRC			291
389 #define IMX8MQ_CLK_UART4_CG			292
390 #define IMX8MQ_CLK_UART4_PRE_DIV		293
391 #define IMX8MQ_CLK_UART4_DIV			294
392 /* USB_CORE_REF */
393 #define IMX8MQ_CLK_USB_CORE_REF_SRC		295
394 #define IMX8MQ_CLK_USB_CORE_REF_CG		296
395 #define IMX8MQ_CLK_USB_CORE_REF_PRE_DIV		297
396 #define IMX8MQ_CLK_USB_CORE_REF_DIV		298
397 /* USB_PHY_REF */
398 #define IMX8MQ_CLK_USB_PHY_REF_SRC		299
399 #define IMX8MQ_CLK_USB_PHY_REF_CG		300
400 #define IMX8MQ_CLK_USB_PHY_REF_PRE_DIV		301
401 #define IMX8MQ_CLK_USB_PHY_REF_DIV		302
402 /* ECSPI1 */
403 #define IMX8MQ_CLK_ECSPI1_SRC			303
404 #define IMX8MQ_CLK_ECSPI1_CG			304
405 #define IMX8MQ_CLK_ECSPI1_PRE_DIV		305
406 #define IMX8MQ_CLK_ECSPI1_DIV			306
407 /* ECSPI2 */
408 #define IMX8MQ_CLK_ECSPI2_SRC			307
409 #define IMX8MQ_CLK_ECSPI2_CG			308
410 #define IMX8MQ_CLK_ECSPI2_PRE_DIV		309
411 #define IMX8MQ_CLK_ECSPI2_DIV			310
412 /* PWM1 */
413 #define IMX8MQ_CLK_PWM1_SRC			311
414 #define IMX8MQ_CLK_PWM1_CG			312
415 #define IMX8MQ_CLK_PWM1_PRE_DIV			313
416 #define IMX8MQ_CLK_PWM1_DIV			314
417 /* PWM2 */
418 #define IMX8MQ_CLK_PWM2_SRC			315
419 #define IMX8MQ_CLK_PWM2_CG			316
420 #define IMX8MQ_CLK_PWM2_PRE_DIV			317
421 #define IMX8MQ_CLK_PWM2_DIV			318
422 /* PWM3 */
423 #define IMX8MQ_CLK_PWM3_SRC			319
424 #define IMX8MQ_CLK_PWM3_CG			320
425 #define IMX8MQ_CLK_PWM3_PRE_DIV			321
426 #define IMX8MQ_CLK_PWM3_DIV			322
427 /* PWM4 */
428 #define IMX8MQ_CLK_PWM4_SRC			323
429 #define IMX8MQ_CLK_PWM4_CG			324
430 #define IMX8MQ_CLK_PWM4_PRE_DIV			325
431 #define IMX8MQ_CLK_PWM4_DIV			326
432 /* GPT1 */
433 #define IMX8MQ_CLK_GPT1_SRC			327
434 #define IMX8MQ_CLK_GPT1_CG			328
435 #define IMX8MQ_CLK_GPT1_PRE_DIV			329
436 #define IMX8MQ_CLK_GPT1_DIV			330
437 /* WDOG */
438 #define IMX8MQ_CLK_WDOG_SRC			331
439 #define IMX8MQ_CLK_WDOG_CG			332
440 #define IMX8MQ_CLK_WDOG_PRE_DIV			333
441 #define IMX8MQ_CLK_WDOG_DIV			334
442 /* WRCLK */
443 #define IMX8MQ_CLK_WRCLK_SRC			335
444 #define IMX8MQ_CLK_WRCLK_CG			336
445 #define IMX8MQ_CLK_WRCLK_PRE_DIV		337
446 #define IMX8MQ_CLK_WRCLK_DIV			338
447 /* DSI_CORE */
448 #define IMX8MQ_CLK_DSI_CORE_SRC			339
449 #define IMX8MQ_CLK_DSI_CORE_CG			340
450 #define IMX8MQ_CLK_DSI_CORE_PRE_DIV		341
451 #define IMX8MQ_CLK_DSI_CORE_DIV			342
452 /* DSI_PHY */
453 #define IMX8MQ_CLK_DSI_PHY_REF_SRC		343
454 #define IMX8MQ_CLK_DSI_PHY_REF_CG		344
455 #define IMX8MQ_CLK_DSI_PHY_REF_PRE_DIV		345
456 #define IMX8MQ_CLK_DSI_PHY_REF_DIV		346
457 /* DSI_DBI */
458 #define IMX8MQ_CLK_DSI_DBI_SRC			347
459 #define IMX8MQ_CLK_DSI_DBI_CG			348
460 #define IMX8MQ_CLK_DSI_DBI_PRE_DIV		349
461 #define IMX8MQ_CLK_DSI_DBI_DIV			350
462 /*DSI_ESC */
463 #define IMX8MQ_CLK_DSI_ESC_SRC			351
464 #define IMX8MQ_CLK_DSI_ESC_CG			352
465 #define IMX8MQ_CLK_DSI_ESC_PRE_DIV		353
466 #define IMX8MQ_CLK_DSI_ESC_DIV			354
467 /* CSI1_CORE */
468 #define IMX8MQ_CLK_CSI1_CORE_SRC		355
469 #define IMX8MQ_CLK_CSI1_CORE_CG			356
470 #define  IMX8MQ_CLK_CSI1_CORE_PRE_DIV		357
471 #define IMX8MQ_CLK_CSI1_CORE_DIV		358
472 /* CSI1_PHY */
473 #define IMX8MQ_CLK_CSI1_PHY_REF_SRC		359
474 #define IMX8MQ_CLK_CSI1_PHY_REF_CG		360
475 #define IMX8MQ_CLK_CSI1_PHY_REF_PRE_DIV		361
476 #define IMX8MQ_CLK_CSI1_PHY_REF_DIV		362
477 /* CSI_ESC */
478 #define IMX8MQ_CLK_CSI1_ESC_SRC			363
479 #define IMX8MQ_CLK_CSI1_ESC_CG			364
480 #define IMX8MQ_CLK_CSI1_ESC_PRE_DIV		365
481 #define IMX8MQ_CLK_CSI1_ESC_DIV			366
482 /* CSI2_CORE */
483 #define IMX8MQ_CLK_CSI2_CORE_SRC		367
484 #define IMX8MQ_CLK_CSI2_CORE_CG			368
485 #define IMX8MQ_CLK_CSI2_CORE_PRE_DIV		369
486 #define IMX8MQ_CLK_CSI2_CORE_DIV		370
487 /* CSI2_PHY */
488 #define IMX8MQ_CLK_CSI2_PHY_REF_SRC		371
489 #define IMX8MQ_CLK_CSI2_PHY_REF_CG		372
490 #define IMX8MQ_CLK_CSI2_PHY_REF_PRE_DIV		373
491 #define IMX8MQ_CLK_CSI2_PHY_REF_DIV		374
492 /* CSI2_ESC */
493 #define IMX8MQ_CLK_CSI2_ESC_SRC			375
494 #define IMX8MQ_CLK_CSI2_ESC_CG			376
495 #define IMX8MQ_CLK_CSI2_ESC_PRE_DIV		377
496 #define IMX8MQ_CLK_CSI2_ESC_DIV			378
497 /* PCIE2_CTRL */
498 #define IMX8MQ_CLK_PCIE2_CTRL_SRC		379
499 #define IMX8MQ_CLK_PCIE2_CTRL_CG		380
500 #define IMX8MQ_CLK_PCIE2_CTRL_PRE_DIV		381
501 #define IMX8MQ_CLK_PCIE2_CTRL_DIV		382
502 /* PCIE2_PHY */
503 #define IMX8MQ_CLK_PCIE2_PHY_SRC		383
504 #define IMX8MQ_CLK_PCIE2_PHY_CG			384
505 #define IMX8MQ_CLK_PCIE2_PHY_PRE_DIV		385
506 #define IMX8MQ_CLK_PCIE2_PHY_DIV		386
507 /* PCIE2_AUX */
508 #define IMX8MQ_CLK_PCIE2_AUX_SRC		387
509 #define IMX8MQ_CLK_PCIE2_AUX_CG			388
510 #define IMX8MQ_CLK_PCIE2_AUX_PRE_DIV		389
511 #define IMX8MQ_CLK_PCIE2_AUX_DIV		390
512 /* ECSPI3 */
513 #define IMX8MQ_CLK_ECSPI3_SRC			391
514 #define IMX8MQ_CLK_ECSPI3_CG			392
515 #define IMX8MQ_CLK_ECSPI3_PRE_DIV		393
516 #define IMX8MQ_CLK_ECSPI3_DIV			394
517 
518 /* CCGR clocks */
519 #define IMX8MQ_CLK_A53_ROOT			395
520 #define IMX8MQ_CLK_DRAM_ROOT			396
521 #define IMX8MQ_CLK_ECSPI1_ROOT			397
522 #define IMX8MQ_CLK_ECSPI2_ROOT			398
523 #define IMX8MQ_CLK_ECSPI3_ROOT			399
524 #define IMX8MQ_CLK_ENET1_ROOT			400
525 #define IMX8MQ_CLK_GPT1_ROOT			401
526 #define IMX8MQ_CLK_I2C1_ROOT			402
527 #define IMX8MQ_CLK_I2C2_ROOT			403
528 #define IMX8MQ_CLK_I2C3_ROOT			404
529 #define IMX8MQ_CLK_I2C4_ROOT			405
530 #define IMX8MQ_CLK_M4_ROOT			406
531 #define IMX8MQ_CLK_PCIE1_ROOT			407
532 #define IMX8MQ_CLK_PCIE2_ROOT			408
533 #define IMX8MQ_CLK_PWM1_ROOT			409
534 #define IMX8MQ_CLK_PWM2_ROOT			410
535 #define IMX8MQ_CLK_PWM3_ROOT			411
536 #define IMX8MQ_CLK_PWM4_ROOT			412
537 #define IMX8MQ_CLK_QSPI_ROOT			413
538 #define IMX8MQ_CLK_SAI1_ROOT			414
539 #define IMX8MQ_CLK_SAI2_ROOT			415
540 #define IMX8MQ_CLK_SAI3_ROOT			416
541 #define IMX8MQ_CLK_SAI4_ROOT			417
542 #define IMX8MQ_CLK_SAI5_ROOT			418
543 #define IMX8MQ_CLK_SAI6_ROOT			419
544 #define IMX8MQ_CLK_UART1_ROOT			420
545 #define IMX8MQ_CLK_UART2_ROOT			421
546 #define IMX8MQ_CLK_UART3_ROOT			422
547 #define IMX8MQ_CLK_UART4_ROOT			423
548 #define IMX8MQ_CLK_USB1_CTRL_ROOT		424
549 #define IMX8MQ_CLK_USB2_CTRL_ROOT		425
550 #define IMX8MQ_CLK_USB1_PHY_ROOT		426
551 #define IMX8MQ_CLK_USB2_PHY_ROOT		427
552 #define IMX8MQ_CLK_USDHC1_ROOT			428
553 #define IMX8MQ_CLK_USDHC2_ROOT			429
554 #define IMX8MQ_CLK_WDOG1_ROOT			430
555 #define IMX8MQ_CLK_WDOG2_ROOT			431
556 #define IMX8MQ_CLK_WDOG3_ROOT			432
557 #define IMX8MQ_CLK_GPU_ROOT			433
558 #define IMX8MQ_CLK_HEVC_ROOT			434
559 #define IMX8MQ_CLK_AVC_ROOT			435
560 #define IMX8MQ_CLK_VP9_ROOT			436
561 #define IMX8MQ_CLK_HEVC_INTER_ROOT		437
562 #define IMX8MQ_CLK_DISP_ROOT			438
563 #define IMX8MQ_CLK_HDMI_ROOT			439
564 #define IMX8MQ_CLK_HDMI_PHY_ROOT		440
565 #define IMX8MQ_CLK_VPU_DEC_ROOT			441
566 #define IMX8MQ_CLK_CSI1_ROOT			442
567 #define IMX8MQ_CLK_CSI2_ROOT			443
568 #define IMX8MQ_CLK_RAWNAND_ROOT			444
569 #define IMX8MQ_CLK_SDMA1_ROOT			445
570 #define IMX8MQ_CLK_SDMA2_ROOT			446
571 #define IMX8MQ_CLK_VPU_G1_ROOT			447
572 #define IMX8MQ_CLK_VPU_G2_ROOT			448
573 
574 /* SCCG PLL GATE */
575 #define IMX8MQ_SYS1_PLL_OUT			449
576 #define IMX8MQ_SYS2_PLL_OUT			450
577 #define IMX8MQ_SYS3_PLL_OUT			451
578 #define IMX8MQ_DRAM_PLL_OUT			452
579 
580 #define IMX8MQ_GPT_3M_CLK			453
581 
582 #define IMX8MQ_CLK_IPG_ROOT			454
583 #define IMX8MQ_CLK_IPG_AUDIO_ROOT		455
584 #define IMX8MQ_CLK_SAI1_IPG			456
585 #define IMX8MQ_CLK_SAI2_IPG			457
586 #define IMX8MQ_CLK_SAI3_IPG			458
587 #define IMX8MQ_CLK_SAI4_IPG			459
588 #define IMX8MQ_CLK_SAI5_IPG			460
589 #define IMX8MQ_CLK_SAI6_IPG			461
590 
591 /* DSI AHB/IPG clocks */
592 /* rxesc clock */
593 #define IMX8MQ_CLK_DSI_AHB_SRC                  462
594 #define IMX8MQ_CLK_DSI_AHB_CG                   463
595 #define IMX8MQ_CLK_DSI_AHB_PRE_DIV              464
596 #define IMX8MQ_CLK_DSI_AHB_DIV                  465
597 /* txesc clock */
598 #define IMX8MQ_CLK_DSI_IPG_DIV                  466
599 
600 /* VIDEO2 PLL */
601 #define IMX8MQ_VIDEO2_PLL1_REF_SEL		467
602 #define IMX8MQ_VIDEO2_PLL1_REF_DIV		468
603 #define IMX8MQ_VIDEO2_PLL1			469
604 #define IMX8MQ_VIDEO2_PLL1_OUT			470
605 #define IMX8MQ_VIDEO2_PLL1_OUT_DIV		471
606 #define IMX8MQ_VIDEO2_PLL2			472
607 #define IMX8MQ_VIDEO2_PLL2_DIV			473
608 #define IMX8MQ_VIDEO2_PLL2_OUT			474
609 #define IMX8MQ_CLK_TMU_ROOT			475
610 
611 #define IMX8MQ_CLK_END				476
612 #endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
613