• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
4  */
5 
6 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H
7 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H
8 
9 /* core clocks */
10 #define PLL_APLL		1
11 #define PLL_DPLL		2
12 #define PLL_CPLL		3
13 #define PLL_GPLL		4
14 #define PLL_NPLL		5
15 #define ARMCLK			6
16 
17 /* sclk gates (special clocks) */
18 #define SCLK_RTC32K		30
19 #define SCLK_SDMMC_EXT		31
20 #define SCLK_SPI		32
21 #define SCLK_SDMMC		33
22 #define SCLK_SDIO		34
23 #define SCLK_EMMC		35
24 #define SCLK_TSADC		36
25 #define SCLK_SARADC		37
26 #define SCLK_UART0		38
27 #define SCLK_UART1		39
28 #define SCLK_UART2		40
29 #define SCLK_I2S0		41
30 #define SCLK_I2S1		42
31 #define SCLK_I2S2		43
32 #define SCLK_I2S1_OUT		44
33 #define SCLK_I2S2_OUT		45
34 #define SCLK_SPDIF		46
35 #define SCLK_TIMER0		47
36 #define SCLK_TIMER1		48
37 #define SCLK_TIMER2		49
38 #define SCLK_TIMER3		50
39 #define SCLK_TIMER4		51
40 #define SCLK_TIMER5		52
41 #define SCLK_WIFI		53
42 #define SCLK_CIF_OUT		54
43 #define SCLK_I2C0		55
44 #define SCLK_I2C1		56
45 #define SCLK_I2C2		57
46 #define SCLK_I2C3		58
47 #define SCLK_CRYPTO		59
48 #define SCLK_PWM		60
49 #define SCLK_PDM		61
50 #define SCLK_EFUSE		62
51 #define SCLK_OTP		63
52 #define SCLK_DDRCLK		64
53 #define SCLK_VDEC_CABAC		65
54 #define SCLK_VDEC_CORE		66
55 #define SCLK_VENC_DSP		67
56 #define SCLK_VENC_CORE		68
57 #define SCLK_RGA		69
58 #define SCLK_HDMI_SFC		70
59 #define SCLK_HDMI_CEC		71
60 #define SCLK_USB3_REF		72
61 #define SCLK_USB3_SUSPEND	73
62 #define SCLK_SDMMC_DRV		74
63 #define SCLK_SDIO_DRV		75
64 #define SCLK_EMMC_DRV		76
65 #define SCLK_SDMMC_EXT_DRV	77
66 #define SCLK_SDMMC_SAMPLE	78
67 #define SCLK_SDIO_SAMPLE	79
68 #define SCLK_EMMC_SAMPLE	80
69 #define SCLK_SDMMC_EXT_SAMPLE	81
70 #define SCLK_VOP		82
71 #define SCLK_MAC2PHY_RXTX	83
72 #define SCLK_MAC2PHY_SRC	84
73 #define SCLK_MAC2PHY_REF	85
74 #define SCLK_MAC2PHY_OUT	86
75 #define SCLK_MAC2IO_RX		87
76 #define SCLK_MAC2IO_TX		88
77 #define SCLK_MAC2IO_REFOUT	89
78 #define SCLK_MAC2IO_REF		90
79 #define SCLK_MAC2IO_OUT		91
80 #define SCLK_TSP		92
81 #define SCLK_HSADC_TSP		93
82 #define SCLK_USB3PHY_REF	94
83 #define SCLK_REF_USB3OTG	95
84 #define SCLK_USB3OTG_REF	96
85 #define SCLK_USB3OTG_SUSPEND	97
86 #define SCLK_REF_USB3OTG_SRC	98
87 #define SCLK_MAC2IO_SRC		99
88 #define SCLK_MAC2IO		100
89 #define SCLK_MAC2PHY		101
90 #define SCLK_MAC2IO_EXT		102
91 
92 /* dclk gates */
93 #define DCLK_LCDC		180
94 #define DCLK_HDMIPHY		181
95 #define HDMIPHY			182
96 #define USB480M			183
97 #define DCLK_LCDC_SRC		184
98 
99 /* aclk gates */
100 #define ACLK_AXISRAM		190
101 #define ACLK_VOP_PRE		191
102 #define ACLK_USB3OTG		192
103 #define ACLK_RGA_PRE		193
104 #define ACLK_DMAC		194
105 #define ACLK_GPU		195
106 #define ACLK_BUS_PRE		196
107 #define ACLK_PERI_PRE		197
108 #define ACLK_RKVDEC_PRE		198
109 #define ACLK_RKVDEC		199
110 #define ACLK_RKVENC		200
111 #define ACLK_VPU_PRE		201
112 #define ACLK_VIO_PRE		202
113 #define ACLK_VPU		203
114 #define ACLK_VIO		204
115 #define ACLK_VOP		205
116 #define ACLK_GMAC		206
117 #define ACLK_H265		207
118 #define ACLK_H264		208
119 #define ACLK_MAC2PHY		209
120 #define ACLK_MAC2IO		210
121 #define ACLK_DCF		211
122 #define ACLK_TSP		212
123 #define ACLK_PERI		213
124 #define ACLK_RGA		214
125 #define ACLK_IEP		215
126 #define ACLK_CIF		216
127 #define ACLK_HDCP		217
128 
129 /* pclk gates */
130 #define PCLK_GPIO0		300
131 #define PCLK_GPIO1		301
132 #define PCLK_GPIO2		302
133 #define PCLK_GPIO3		303
134 #define PCLK_GRF		304
135 #define PCLK_I2C0		305
136 #define PCLK_I2C1		306
137 #define PCLK_I2C2		307
138 #define PCLK_I2C3		308
139 #define PCLK_SPI		309
140 #define PCLK_UART0		310
141 #define PCLK_UART1		311
142 #define PCLK_UART2		312
143 #define PCLK_TSADC		313
144 #define PCLK_PWM		314
145 #define PCLK_TIMER		315
146 #define PCLK_BUS_PRE		316
147 #define PCLK_PERI_PRE		317
148 #define PCLK_HDMI_CTRL		318
149 #define PCLK_HDMI_PHY		319
150 #define PCLK_GMAC		320
151 #define PCLK_H265		321
152 #define PCLK_MAC2PHY		322
153 #define PCLK_MAC2IO		323
154 #define PCLK_USB3PHY_OTG	324
155 #define PCLK_USB3PHY_PIPE	325
156 #define PCLK_USB3_GRF		326
157 #define PCLK_USB2_GRF		327
158 #define PCLK_HDMIPHY		328
159 #define PCLK_DDR		329
160 #define PCLK_PERI		330
161 #define PCLK_HDMI		331
162 #define PCLK_HDCP		332
163 #define PCLK_DCF		333
164 #define PCLK_SARADC		334
165 
166 /* hclk gates */
167 #define HCLK_PERI		408
168 #define HCLK_TSP		409
169 #define HCLK_GMAC		410
170 #define HCLK_I2S0_8CH		411
171 #define HCLK_I2S1_8CH		413
172 #define HCLK_I2S2_2CH		413
173 #define HCLK_SPDIF_8CH		414
174 #define HCLK_VOP		415
175 #define HCLK_NANDC		416
176 #define HCLK_SDMMC		417
177 #define HCLK_SDIO		418
178 #define HCLK_EMMC		419
179 #define HCLK_SDMMC_EXT		420
180 #define HCLK_RKVDEC_PRE		421
181 #define HCLK_RKVDEC		422
182 #define HCLK_RKVENC		423
183 #define HCLK_VPU_PRE		424
184 #define HCLK_VIO_PRE		425
185 #define HCLK_VPU		426
186 #define HCLK_VIO		427
187 #define HCLK_BUS_PRE		428
188 #define HCLK_PERI_PRE		429
189 #define HCLK_H264		430
190 #define HCLK_CIF		431
191 #define HCLK_OTG_PMU		432
192 #define HCLK_OTG		433
193 #define HCLK_HOST0		434
194 #define HCLK_HOST0_ARB		435
195 #define HCLK_CRYPTO_MST		436
196 #define HCLK_CRYPTO_SLV		437
197 #define HCLK_PDM		438
198 #define HCLK_IEP		439
199 #define HCLK_RGA		440
200 #define HCLK_HDCP		441
201 
202 #define CLK_NR_CLKS		(HCLK_HDCP + 1)
203 
204 #define CLKGRF_NR_CLKS		(SCLK_MAC2PHY + 1)
205 
206 /* soft-reset indices */
207 #define SRST_CORE0_PO		0
208 #define SRST_CORE1_PO		1
209 #define SRST_CORE2_PO		2
210 #define SRST_CORE3_PO		3
211 #define SRST_CORE0		4
212 #define SRST_CORE1		5
213 #define SRST_CORE2		6
214 #define SRST_CORE3		7
215 #define SRST_CORE0_DBG		8
216 #define SRST_CORE1_DBG		9
217 #define SRST_CORE2_DBG		10
218 #define SRST_CORE3_DBG		11
219 #define SRST_TOPDBG		12
220 #define SRST_CORE_NIU		13
221 #define SRST_STRC_A		14
222 #define SRST_L2C		15
223 
224 #define SRST_A53_GIC		18
225 #define SRST_DAP		19
226 #define SRST_PMU_P		21
227 #define SRST_EFUSE		22
228 #define SRST_BUSSYS_H		23
229 #define SRST_BUSSYS_P		24
230 #define SRST_SPDIF		25
231 #define SRST_INTMEM		26
232 #define SRST_ROM		27
233 #define SRST_GPIO0		28
234 #define SRST_GPIO1		29
235 #define SRST_GPIO2		30
236 #define SRST_GPIO3		31
237 
238 #define SRST_I2S0		32
239 #define SRST_I2S1		33
240 #define SRST_I2S2		34
241 #define SRST_I2S0_H		35
242 #define SRST_I2S1_H		36
243 #define SRST_I2S2_H		37
244 #define SRST_UART0		38
245 #define SRST_UART1		39
246 #define SRST_UART2		40
247 #define SRST_UART0_P		41
248 #define SRST_UART1_P		42
249 #define SRST_UART2_P		43
250 #define SRST_I2C0		44
251 #define SRST_I2C1		45
252 #define SRST_I2C2		46
253 #define SRST_I2C3		47
254 
255 #define SRST_I2C0_P		48
256 #define SRST_I2C1_P		49
257 #define SRST_I2C2_P		50
258 #define SRST_I2C3_P		51
259 #define SRST_EFUSE_SE_P		52
260 #define SRST_EFUSE_NS_P		53
261 #define SRST_PWM0		54
262 #define SRST_PWM0_P		55
263 #define SRST_DMA		56
264 #define SRST_TSP_A		57
265 #define SRST_TSP_H		58
266 #define SRST_TSP		59
267 #define SRST_TSP_HSADC		60
268 #define SRST_DCF_A		61
269 #define SRST_DCF_P		62
270 
271 #define SRST_SCR		64
272 #define SRST_SPI		65
273 #define SRST_TSADC		66
274 #define SRST_TSADC_P		67
275 #define SRST_CRYPTO		68
276 #define SRST_SGRF		69
277 #define SRST_GRF		70
278 #define SRST_USB_GRF		71
279 #define SRST_TIMER_6CH_P	72
280 #define SRST_TIMER0		73
281 #define SRST_TIMER1		74
282 #define SRST_TIMER2		75
283 #define SRST_TIMER3		76
284 #define SRST_TIMER4		77
285 #define SRST_TIMER5		78
286 #define SRST_USB3GRF		79
287 
288 #define SRST_PHYNIU		80
289 #define SRST_HDMIPHY		81
290 #define SRST_VDAC		82
291 #define SRST_ACODEC_p		83
292 #define SRST_SARADC		85
293 #define SRST_SARADC_P		86
294 #define SRST_GRF_DDR		87
295 #define SRST_DFIMON		88
296 #define SRST_MSCH		89
297 #define SRST_DDRMSCH		91
298 #define SRST_DDRCTRL		92
299 #define SRST_DDRCTRL_P		93
300 #define SRST_DDRPHY		94
301 #define SRST_DDRPHY_P		95
302 
303 #define SRST_GMAC_NIU_A		96
304 #define SRST_GMAC_NIU_P		97
305 #define SRST_GMAC2PHY_A		98
306 #define SRST_GMAC2IO_A		99
307 #define SRST_MACPHY		100
308 #define SRST_OTP_PHY		101
309 #define SRST_GPU_A		102
310 #define SRST_GPU_NIU_A		103
311 #define SRST_SDMMCEXT		104
312 #define SRST_PERIPH_NIU_A	105
313 #define SRST_PERIHP_NIU_H	106
314 #define SRST_PERIHP_P		107
315 #define SRST_PERIPHSYS_H	108
316 #define SRST_MMC0		109
317 #define SRST_SDIO		110
318 #define SRST_EMMC		111
319 
320 #define SRST_USB2OTG_H		112
321 #define SRST_USB2OTG		113
322 #define SRST_USB2OTG_ADP	114
323 #define SRST_USB2HOST_H		115
324 #define SRST_USB2HOST_ARB	116
325 #define SRST_USB2HOST_AUX	117
326 #define SRST_USB2HOST_EHCIPHY	118
327 #define SRST_USB2HOST_UTMI	119
328 #define SRST_USB3OTG		120
329 #define SRST_USBPOR		121
330 #define SRST_USB2OTG_UTMI	122
331 #define SRST_USB2HOST_PHY_UTMI	123
332 #define SRST_USB3OTG_UTMI	124
333 #define SRST_USB3PHY_U2		125
334 #define SRST_USB3PHY_U3		126
335 #define SRST_USB3PHY_PIPE	127
336 
337 #define SRST_VIO_A		128
338 #define SRST_VIO_BUS_H		129
339 #define SRST_VIO_H2P_H		130
340 #define SRST_VIO_ARBI_H		131
341 #define SRST_VOP_NIU_A		132
342 #define SRST_VOP_A		133
343 #define SRST_VOP_H		134
344 #define SRST_VOP_D		135
345 #define SRST_RGA		136
346 #define SRST_RGA_NIU_A		137
347 #define SRST_RGA_A		138
348 #define SRST_RGA_H		139
349 #define SRST_IEP_A		140
350 #define SRST_IEP_H		141
351 #define SRST_HDMI		142
352 #define SRST_HDMI_P		143
353 
354 #define SRST_HDCP_A		144
355 #define SRST_HDCP		145
356 #define SRST_HDCP_H		146
357 #define SRST_CIF_A		147
358 #define SRST_CIF_H		148
359 #define SRST_CIF_P		149
360 #define SRST_OTP_P		150
361 #define SRST_OTP_SBPI		151
362 #define SRST_OTP_USER		152
363 #define SRST_DDRCTRL_A		153
364 #define SRST_DDRSTDY_P		154
365 #define SRST_DDRSTDY		155
366 #define SRST_PDM_H		156
367 #define SRST_PDM		157
368 #define SRST_USB3PHY_OTG_P	158
369 #define SRST_USB3PHY_PIPE_P	159
370 
371 #define SRST_VCODEC_A		160
372 #define SRST_VCODEC_NIU_A	161
373 #define SRST_VCODEC_H		162
374 #define SRST_VCODEC_NIU_H	163
375 #define SRST_VDEC_A		164
376 #define SRST_VDEC_NIU_A		165
377 #define SRST_VDEC_H		166
378 #define SRST_VDEC_NIU_H		167
379 #define SRST_VDEC_CORE		168
380 #define SRST_VDEC_CABAC		169
381 #define SRST_DDRPHYDIV		175
382 
383 #define SRST_RKVENC_NIU_A	176
384 #define SRST_RKVENC_NIU_H	177
385 #define SRST_RKVENC_H265_A	178
386 #define SRST_RKVENC_H265_P	179
387 #define SRST_RKVENC_H265_CORE	180
388 #define SRST_RKVENC_H265_DSP	181
389 #define SRST_RKVENC_H264_A	182
390 #define SRST_RKVENC_H264_H	183
391 #define SRST_RKVENC_INTMEM	184
392 
393 #endif
394