1 /* 2 * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de> 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H 15 #define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H 16 17 /* MPUMODRST */ 18 #define CPU0_RESET 0 19 #define CPU1_RESET 1 20 #define WDS_RESET 2 21 #define SCUPER_RESET 3 22 23 /* PER0MODRST */ 24 #define EMAC0_RESET 32 25 #define EMAC1_RESET 33 26 #define EMAC2_RESET 34 27 #define USB0_RESET 35 28 #define USB1_RESET 36 29 #define NAND_RESET 37 30 #define QSPI_RESET 38 31 #define SDMMC_RESET 39 32 #define EMAC0_OCP_RESET 40 33 #define EMAC1_OCP_RESET 41 34 #define EMAC2_OCP_RESET 42 35 #define USB0_OCP_RESET 43 36 #define USB1_OCP_RESET 44 37 #define NAND_OCP_RESET 45 38 #define QSPI_OCP_RESET 46 39 #define SDMMC_OCP_RESET 47 40 #define DMA_RESET 48 41 #define SPIM0_RESET 49 42 #define SPIM1_RESET 50 43 #define SPIS0_RESET 51 44 #define SPIS1_RESET 52 45 #define DMA_OCP_RESET 53 46 #define EMAC_PTP_RESET 54 47 /* 55 is empty*/ 48 #define DMAIF0_RESET 56 49 #define DMAIF1_RESET 57 50 #define DMAIF2_RESET 58 51 #define DMAIF3_RESET 59 52 #define DMAIF4_RESET 60 53 #define DMAIF5_RESET 61 54 #define DMAIF6_RESET 62 55 #define DMAIF7_RESET 63 56 57 /* PER1MODRST */ 58 #define L4WD0_RESET 64 59 #define L4WD1_RESET 65 60 #define L4SYSTIMER0_RESET 66 61 #define L4SYSTIMER1_RESET 67 62 #define SPTIMER0_RESET 68 63 #define SPTIMER1_RESET 69 64 /* 70-71 is reserved */ 65 #define I2C0_RESET 72 66 #define I2C1_RESET 73 67 #define I2C2_RESET 74 68 #define I2C3_RESET 75 69 #define I2C4_RESET 76 70 /* 77-79 is reserved */ 71 #define UART0_RESET 80 72 #define UART1_RESET 81 73 /* 82-87 is reserved */ 74 #define GPIO0_RESET 88 75 #define GPIO1_RESET 89 76 #define GPIO2_RESET 90 77 78 /* BRGMODRST */ 79 #define HPS2FPGA_RESET 96 80 #define LWHPS2FPGA_RESET 97 81 #define FPGA2HPS_RESET 98 82 #define F2SSDRAM0_RESET 99 83 #define F2SSDRAM1_RESET 100 84 #define F2SSDRAM2_RESET 101 85 #define DDRSCH_RESET 102 86 87 /* SYSMODRST*/ 88 #define ROM_RESET 128 89 #define OCRAM_RESET 129 90 /* 130 is reserved */ 91 #define FPGAMGR_RESET 131 92 #define S2F_RESET 132 93 #define SYSDBG_RESET 133 94 #define OCRAM_OCP_RESET 134 95 96 /* COLDMODRST */ 97 #define CLKMGRCOLD_RESET 160 98 /* 161-162 is reserved */ 99 #define S2FCOLD_RESET 163 100 #define TIMESTAMPCOLD_RESET 164 101 #define TAPCOLD_RESET 165 102 #define HMCCOLD_RESET 166 103 #define IOMGRCOLD_RESET 167 104 105 /* NRSTMODRST */ 106 #define NRSTPINOE_RESET 192 107 108 /* DBGMODRST */ 109 #define DBG_RESET 224 110 #endif 111