1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * This header file contains assembly-language definitions (assembly 4 * macros, etc.) for this specific Xtensa processor's TIE extensions 5 * and options. It is customized to this Xtensa processor configuration. 6 * This file is autogenerated, please do not edit. 7 * 8 * Copyright (C) 1999-2015 Cadence Design Systems Inc. 9 */ 10 11 #ifndef _XTENSA_CORE_TIE_ASM_H 12 #define _XTENSA_CORE_TIE_ASM_H 13 14 /* Selection parameter values for save-area save/restore macros: */ 15 /* Option vs. TIE: */ 16 #define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ 17 #define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ 18 #define XTHAL_SAS_ANYOT 0x0003 /* both of the above */ 19 /* Whether used automatically by compiler: */ 20 #define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ 21 #define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ 22 #define XTHAL_SAS_ANYCC 0x000C /* both of the above */ 23 /* ABI handling across function calls: */ 24 #define XTHAL_SAS_CALR 0x0010 /* caller-saved */ 25 #define XTHAL_SAS_CALE 0x0020 /* callee-saved */ 26 #define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ 27 #define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */ 28 /* Misc */ 29 #define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ 30 #define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \ 31 | ((ccuse) & XTHAL_SAS_ANYCC) \ 32 | ((abi) & XTHAL_SAS_ANYABI) ) 33 34 35 /* 36 * Macro to store all non-coprocessor (extra) custom TIE and optional state 37 * (not including zero-overhead loop registers). 38 * Required parameters: 39 * ptr Save area pointer address register (clobbered) 40 * (register must contain a 4 byte aligned address). 41 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS 42 * registers are clobbered, the remaining are unused). 43 * Optional parameters: 44 * continue If macro invoked as part of a larger store sequence, set to 1 45 * if this is not the first in the sequence. Defaults to 0. 46 * ofs Offset from start of larger sequence (from value of first ptr 47 * in sequence) at which to store. Defaults to next available space 48 * (or 0 if <continue> is 0). 49 * select Select what category(ies) of registers to store, as a bitmask 50 * (see XTHAL_SAS_xxx constants). Defaults to all registers. 51 * alloc Select what category(ies) of registers to allocate; if any 52 * category is selected here that is not in <select>, space for 53 * the corresponding registers is skipped without doing any store. 54 */ 55 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 56 xchal_sa_start \continue, \ofs 57 // Optional caller-saved registers used by default by the compiler: 58 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select) 59 xchal_sa_align \ptr, 0, 1016, 4, 4 60 rsr.ACCLO \at1 // MAC16 option 61 s32i \at1, \ptr, .Lxchal_ofs_+0 62 rsr.ACCHI \at1 // MAC16 option 63 s32i \at1, \ptr, .Lxchal_ofs_+4 64 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 65 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 66 xchal_sa_align \ptr, 0, 1016, 4, 4 67 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 68 .endif 69 // Optional caller-saved registers not used by default by the compiler: 70 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 71 xchal_sa_align \ptr, 0, 1004, 4, 4 72 rsr.SCOMPARE1 \at1 // conditional store option 73 s32i \at1, \ptr, .Lxchal_ofs_+0 74 rsr.M0 \at1 // MAC16 option 75 s32i \at1, \ptr, .Lxchal_ofs_+4 76 rsr.M1 \at1 // MAC16 option 77 s32i \at1, \ptr, .Lxchal_ofs_+8 78 rsr.M2 \at1 // MAC16 option 79 s32i \at1, \ptr, .Lxchal_ofs_+12 80 rsr.M3 \at1 // MAC16 option 81 s32i \at1, \ptr, .Lxchal_ofs_+16 82 .set .Lxchal_ofs_, .Lxchal_ofs_ + 20 83 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 84 xchal_sa_align \ptr, 0, 1004, 4, 4 85 .set .Lxchal_ofs_, .Lxchal_ofs_ + 20 86 .endif 87 .endm // xchal_ncp_store 88 89 /* 90 * Macro to load all non-coprocessor (extra) custom TIE and optional state 91 * (not including zero-overhead loop registers). 92 * Required parameters: 93 * ptr Save area pointer address register (clobbered) 94 * (register must contain a 4 byte aligned address). 95 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS 96 * registers are clobbered, the remaining are unused). 97 * Optional parameters: 98 * continue If macro invoked as part of a larger load sequence, set to 1 99 * if this is not the first in the sequence. Defaults to 0. 100 * ofs Offset from start of larger sequence (from value of first ptr 101 * in sequence) at which to load. Defaults to next available space 102 * (or 0 if <continue> is 0). 103 * select Select what category(ies) of registers to load, as a bitmask 104 * (see XTHAL_SAS_xxx constants). Defaults to all registers. 105 * alloc Select what category(ies) of registers to allocate; if any 106 * category is selected here that is not in <select>, space for 107 * the corresponding registers is skipped without doing any load. 108 */ 109 .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 110 xchal_sa_start \continue, \ofs 111 // Optional caller-saved registers used by default by the compiler: 112 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select) 113 xchal_sa_align \ptr, 0, 1016, 4, 4 114 l32i \at1, \ptr, .Lxchal_ofs_+0 115 wsr.ACCLO \at1 // MAC16 option 116 l32i \at1, \ptr, .Lxchal_ofs_+4 117 wsr.ACCHI \at1 // MAC16 option 118 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 119 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 120 xchal_sa_align \ptr, 0, 1016, 4, 4 121 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 122 .endif 123 // Optional caller-saved registers not used by default by the compiler: 124 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 125 xchal_sa_align \ptr, 0, 1004, 4, 4 126 l32i \at1, \ptr, .Lxchal_ofs_+0 127 wsr.SCOMPARE1 \at1 // conditional store option 128 l32i \at1, \ptr, .Lxchal_ofs_+4 129 wsr.M0 \at1 // MAC16 option 130 l32i \at1, \ptr, .Lxchal_ofs_+8 131 wsr.M1 \at1 // MAC16 option 132 l32i \at1, \ptr, .Lxchal_ofs_+12 133 wsr.M2 \at1 // MAC16 option 134 l32i \at1, \ptr, .Lxchal_ofs_+16 135 wsr.M3 \at1 // MAC16 option 136 .set .Lxchal_ofs_, .Lxchal_ofs_ + 20 137 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 138 xchal_sa_align \ptr, 0, 1004, 4, 4 139 .set .Lxchal_ofs_, .Lxchal_ofs_ + 20 140 .endif 141 .endm // xchal_ncp_load 142 143 144 #define XCHAL_NCP_NUM_ATMPS 1 145 146 #define XCHAL_SA_NUM_ATMPS 1 147 148 #endif /*_XTENSA_CORE_TIE_ASM_H*/ 149 150