1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
4 */
5
6 #include <common.h>
7 #include <miiphy.h>
8 #include <netdev.h>
9 #include <asm/io.h>
10 #include <asm/arch/cpu.h>
11 #include <asm/arch/soc.h>
12
13 DECLARE_GLOBAL_DATA_PTR;
14
15 #define ETH_PHY_CTRL_REG 0
16 #define ETH_PHY_CTRL_POWER_DOWN_BIT 11
17 #define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
18
19 /*
20 * Those values and defines are taken from the Marvell U-Boot version
21 * "u-boot-2011.12-2014_T1.0" for the board rd78460gp aka
22 * "RD-AXP-GP rev 1.0".
23 *
24 * GPPs
25 * MPP# NAME IN/OUT
26 * ----------------------------------------------
27 * 21 SW_Reset_ OUT
28 * 25 Phy_Int# IN
29 * 28 SDI_WP IN
30 * 29 SDI_Status IN
31 * 54-61 On GPP Connector ?
32 * 62 Switch Interrupt IN
33 * 63-65 Reserved from SW Board ?
34 * 66 SW_BRD connected IN
35 */
36 #define RD_78460_GP_GPP_OUT_ENA_LOW (~(BIT(21) | BIT(20)))
37 #define RD_78460_GP_GPP_OUT_ENA_MID (~(BIT(26) | BIT(27)))
38 #define RD_78460_GP_GPP_OUT_ENA_HIGH (~(0x0))
39
40 #define RD_78460_GP_GPP_OUT_VAL_LOW (BIT(21) | BIT(20))
41 #define RD_78460_GP_GPP_OUT_VAL_MID (BIT(26) | BIT(27))
42 #define RD_78460_GP_GPP_OUT_VAL_HIGH 0x0
43
board_early_init_f(void)44 int board_early_init_f(void)
45 {
46 /* Configure MPP */
47 writel(0x00000000, MVEBU_MPP_BASE + 0x00);
48 writel(0x00000000, MVEBU_MPP_BASE + 0x04);
49 writel(0x33000000, MVEBU_MPP_BASE + 0x08);
50 writel(0x11000000, MVEBU_MPP_BASE + 0x0c);
51 writel(0x11111111, MVEBU_MPP_BASE + 0x10);
52 writel(0x00221100, MVEBU_MPP_BASE + 0x14);
53 writel(0x00000003, MVEBU_MPP_BASE + 0x18);
54 writel(0x00000000, MVEBU_MPP_BASE + 0x1c);
55 writel(0x00000000, MVEBU_MPP_BASE + 0x20);
56
57 /* Configure GPIO */
58 writel(RD_78460_GP_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
59 writel(RD_78460_GP_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
60 writel(RD_78460_GP_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
61 writel(RD_78460_GP_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
62 writel(RD_78460_GP_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
63 writel(RD_78460_GP_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
64
65 return 0;
66 }
67
board_init(void)68 int board_init(void)
69 {
70 /* adress of boot parameters */
71 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
72
73 return 0;
74 }
75
checkboard(void)76 int checkboard(void)
77 {
78 puts("Board: Marvell DB-MV784MP-GP\n");
79
80 return 0;
81 }
82
board_eth_init(bd_t * bis)83 int board_eth_init(bd_t *bis)
84 {
85 cpu_eth_init(bis); /* Built in controller(s) come first */
86 return pci_eth_init(bis);
87 }
88
board_phy_config(struct phy_device * phydev)89 int board_phy_config(struct phy_device *phydev)
90 {
91 u16 reg;
92
93 /* Enable QSGMII AN */
94 /* Set page to 4 */
95 phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 4);
96 /* Enable AN */
97 phy_write(phydev, MDIO_DEVAD_NONE, 0x0, 0x1140);
98 /* Set page to 0 */
99 phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0);
100
101 /* Phy C_ANEG */
102 reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x4);
103 reg |= 0x1E0;
104 phy_write(phydev, MDIO_DEVAD_NONE, 0x4, reg);
105
106 /* Soft-Reset */
107 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000);
108 phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140);
109
110 /* Power up the phy */
111 reg = phy_read(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG);
112 reg &= ~(ETH_PHY_CTRL_POWER_DOWN_MASK);
113 phy_write(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG, reg);
114
115 printf("88E1545 Initialized\n");
116 return 0;
117 }
118