1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2012 Atmel Corporation
4 */
5
6 #include <common.h>
7 #include <asm/io.h>
8 #include <asm/arch/at91sam9x5_matrix.h>
9 #include <asm/arch/at91sam9_smc.h>
10 #include <asm/arch/at91_common.h>
11 #include <asm/arch/at91_rstc.h>
12 #include <asm/arch/clk.h>
13 #include <asm/arch/gpio.h>
14 #include <debug_uart.h>
15 #include <asm/mach-types.h>
16
17 DECLARE_GLOBAL_DATA_PTR;
18
19 /* ------------------------------------------------------------------------- */
20 /*
21 * Miscelaneous platform dependent initialisations
22 */
23 #ifdef CONFIG_CMD_NAND
at91sam9x5ek_nand_hw_init(void)24 static void at91sam9x5ek_nand_hw_init(void)
25 {
26 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
27 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
28 unsigned long csa;
29
30 /* Enable CS3 */
31 csa = readl(&matrix->ebicsa);
32 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
33 /* NAND flash on D16 */
34 csa |= AT91_MATRIX_NFD0_ON_D16;
35
36 /* Configure IO drive */
37 csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
38
39 writel(csa, &matrix->ebicsa);
40
41 /* Configure SMC CS3 for NAND/SmartMedia */
42 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
43 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
44 &smc->cs[3].setup);
45 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
46 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
47 &smc->cs[3].pulse);
48 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6),
49 &smc->cs[3].cycle);
50 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
51 AT91_SMC_MODE_EXNW_DISABLE |
52 #ifdef CONFIG_SYS_NAND_DBW_16
53 AT91_SMC_MODE_DBW_16 |
54 #else /* CONFIG_SYS_NAND_DBW_8 */
55 AT91_SMC_MODE_DBW_8 |
56 #endif
57 AT91_SMC_MODE_TDF_CYCLE(1),
58 &smc->cs[3].mode);
59
60 at91_periph_clk_enable(ATMEL_ID_PIOCD);
61
62 /* Configure RDY/BSY */
63 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
64 /* Enable NandFlash */
65 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
66
67 at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
68 at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
69 at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */
70 at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */
71 at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1);
72 at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1);
73 at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1);
74 at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1);
75 at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1);
76 at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1);
77 at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1);
78 at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1);
79 }
80 #endif
81
82 #ifdef CONFIG_BOARD_LATE_INIT
board_late_init(void)83 int board_late_init(void)
84 {
85 #ifdef CONFIG_DM_VIDEO
86 at91_video_show_board_info();
87 #endif
88 return 0;
89 }
90 #endif
91
92 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
board_debug_uart_init(void)93 void board_debug_uart_init(void)
94 {
95 at91_seriald_hw_init();
96 }
97 #endif
98
99 #ifdef CONFIG_BOARD_EARLY_INIT_F
board_early_init_f(void)100 int board_early_init_f(void)
101 {
102 #ifdef CONFIG_DEBUG_UART
103 debug_uart_init();
104 #endif
105 return 0;
106 }
107 #endif
108
board_init(void)109 int board_init(void)
110 {
111 /* arch number of AT91SAM9X5EK-Board */
112 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9X5EK;
113
114 /* adress of boot parameters */
115 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
116
117 #ifdef CONFIG_CMD_NAND
118 at91sam9x5ek_nand_hw_init();
119 #endif
120
121 #if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI_HCD)
122 at91_uhp_hw_init();
123 #endif
124 return 0;
125 }
126
dram_init(void)127 int dram_init(void)
128 {
129 gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
130 CONFIG_SYS_SDRAM_SIZE);
131 return 0;
132 }
133
134 #if defined(CONFIG_SPL_BUILD)
135 #include <spl.h>
136 #include <nand.h>
137
at91_spl_board_init(void)138 void at91_spl_board_init(void)
139 {
140 #ifdef CONFIG_SD_BOOT
141 at91_mci_hw_init();
142 #elif CONFIG_NAND_BOOT
143 at91sam9x5ek_nand_hw_init();
144 #endif
145 }
146
147 #include <asm/arch/atmel_mpddrc.h>
ddr2_conf(struct atmel_mpddrc_config * ddr2)148 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
149 {
150 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
151
152 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
153 ATMEL_MPDDRC_CR_NR_ROW_13 |
154 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
155 ATMEL_MPDDRC_CR_NB_8BANKS |
156 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);
157
158 ddr2->rtr = 0x411;
159
160 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
161 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
162 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
163 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
164 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
165 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
166 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
167 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
168
169 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
170 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
171 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
172 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
173
174 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
175 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
176 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
177 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
178 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
179 }
180
mem_init(void)181 void mem_init(void)
182 {
183 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
184 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
185 struct atmel_mpddrc_config ddr2;
186 unsigned long csa;
187
188 ddr2_conf(&ddr2);
189
190 /* enable DDR2 clock */
191 writel(AT91_PMC_DDR, &pmc->scer);
192
193 /* Chip select 1 is for DDR2/SDRAM */
194 csa = readl(&matrix->ebicsa);
195 csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
196 csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
197 csa |= AT91_MATRIX_EBI_DBPD_OFF;
198 csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
199 writel(csa, &matrix->ebicsa);
200
201 /* DDRAM2 Controller initialize */
202 ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);
203 }
204 #endif
205