1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2014, Barco (www.barco.com)
4 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
5 */
6
7 #include <common.h>
8 #include <asm/arch/iomux.h>
9 #include <asm/arch/mx6-pins.h>
10 #include <asm/gpio.h>
11 #include <asm/mach-imx/iomux-v3.h>
12 #include <asm/mach-imx/mxc_i2c.h>
13 #include <miiphy.h>
14 #include <micrel.h>
15
16 #include "platinum.h"
17
18 iomux_v3_cfg_t const ecspi1_pads[] = {
19 MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(ECSPI1_PAD_CLK),
20 MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO),
21 MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI),
22 MX6_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS),
23 /* non mounted spi nor flash for booting */
24 MX6_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL),
25 MX6_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(ECSPI_PAD_SS),
26 MX6_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(ECSPI_PAD_SS),
27 };
28
29 iomux_v3_cfg_t const ecspi2_pads[] = {
30 MX6_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(ECSPI2_PAD_CLK),
31 MX6_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO),
32 MX6_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI),
33 MX6_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS),
34 };
35
36 iomux_v3_cfg_t const enet_pads1[] = {
37 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
38 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
39 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
40 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
41 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
42 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
43 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
44 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
45 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
46 /* pin 35 - 1 (PHY_AD2) on reset */
47 MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
48 /* pin 32 - 1 - (MODE0) all */
49 MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
50 /* pin 31 - 1 - (MODE1) all */
51 MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
52 /* pin 28 - 1 - (MODE2) all */
53 MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
54 /* pin 27 - 1 - (MODE3) all */
55 MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
56 /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
57 MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
58 /* pin 42 PHY nRST */
59 MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
60 };
61
62 iomux_v3_cfg_t const enet_pads2[] = {
63 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
64 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
65 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
66 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
67 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
68 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
69 };
70
71 iomux_v3_cfg_t const uart1_pads[] = {
72 MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
73 MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
74 };
75
76 iomux_v3_cfg_t const uart2_pads[] = {
77 MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
78 MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
79 MX6_PAD_EIM_D28__UART2_DTE_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
80 MX6_PAD_EIM_D29__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
81 };
82
83 iomux_v3_cfg_t const uart4_pads[] = {
84 MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
85 MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
86 MX6_PAD_CSI0_DAT16__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
87 MX6_PAD_CSI0_DAT17__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
88 };
89
90 struct i2c_pads_info i2c_pad_info0 = {
91 .scl = {
92 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC_SCL,
93 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC_SCL,
94 .gp = IMX_GPIO_NR(5, 27)
95 },
96 .sda = {
97 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
98 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
99 .gp = IMX_GPIO_NR(5, 26)
100 }
101 };
102
103 struct i2c_pads_info i2c_pad_info2 = {
104 .scl = {
105 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC_SCL,
106 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC_SCL,
107 .gp = IMX_GPIO_NR(1, 3)
108 },
109 .sda = {
110 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
111 .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC,
112 .gp = IMX_GPIO_NR(7, 11)
113 }
114 };
115
116 /*
117 * This enet related pin-muxing and GPIO handling is done
118 * in SPL U-Boot. For early initialization. And to give the
119 * PHY some time to come out of reset before the U-Boot
120 * ethernet driver tries to access its registers via MDIO.
121 */
platinum_setup_enet(void)122 int platinum_setup_enet(void)
123 {
124 gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
125 gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
126 gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
127 gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
128 gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
129 gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
130 imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
131 gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
132
133 /* Need delay 10ms according to KSZ9021 spec */
134 mdelay(10);
135 gpio_set_value(IMX_GPIO_NR(3, 23), 1);
136 udelay(100);
137
138 imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
139
140 return 0;
141 }
142
platinum_setup_i2c(void)143 int platinum_setup_i2c(void)
144 {
145 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
146 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
147
148 return 0;
149 }
150
platinum_setup_spi(void)151 int platinum_setup_spi(void)
152 {
153 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
154 imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads));
155
156 return 0;
157 }
158
platinum_setup_uart(void)159 int platinum_setup_uart(void)
160 {
161 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
162 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
163 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
164
165 return 0;
166 }
167
platinum_phy_config(struct phy_device * phydev)168 int platinum_phy_config(struct phy_device *phydev)
169 {
170 /* min rx data delay */
171 ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
172 0x0);
173 /* min tx data delay */
174 ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
175 0x0);
176 /* max rx/tx clock delay, min rx/tx control */
177 ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
178 0xf0f0);
179 if (phydev->drv->config)
180 phydev->drv->config(phydev);
181
182 return 0;
183 }
184
platinum_init_gpio(void)185 int platinum_init_gpio(void)
186 {
187 /* Default GPIO's */
188 /* Toggle CONFIG_n to reset fpga on every boot */
189 gpio_direction_output(IMX_GPIO_NR(5, 18), 0);
190 /* Need delay >=2uS */
191 udelay(3);
192 gpio_set_value(IMX_GPIO_NR(5, 18), 1);
193
194 /* Default pin 1,15 high - DLP_FLASH_WPZ */
195 gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
196
197 return 0;
198 }
199
platinum_init_usb(void)200 int platinum_init_usb(void)
201 {
202 return 0;
203 }
204
platinum_init_finished(void)205 int platinum_init_finished(void)
206 {
207 return 0;
208 }
209