1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2015-2016 Freescale Semiconductor, Inc.
4 * Copyright 2017 NXP
5 */
6
7 #include <common.h>
8 #include <dm.h>
9 #include <asm/io.h>
10 #include <netdev.h>
11 #include <fm_eth.h>
12 #include <fsl_mdio.h>
13 #include <malloc.h>
14 #include <asm/types.h>
15 #include <fsl_dtsec.h>
16 #include <asm/arch/soc.h>
17 #include <asm/arch-fsl-layerscape/config.h>
18 #include <asm/arch-fsl-layerscape/immap_lsch2.h>
19 #include <asm/arch/fsl_serdes.h>
20 #include <net/pfe_eth/pfe_eth.h>
21 #include <dm/platform_data/pfe_dm_eth.h>
22 #include <i2c.h>
23
24 #define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
25
ls1012ardb_reset_phy(void)26 static inline void ls1012ardb_reset_phy(void)
27 {
28 #ifdef CONFIG_TARGET_LS1012ARDB
29 /* Through reset IO expander reset both RGMII and SGMII PHYs */
30 i2c_reg_write(I2C_MUX_IO2_ADDR, 6, __PHY_MASK);
31 i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH2_MASK);
32 mdelay(10);
33 i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH1_MASK);
34 mdelay(10);
35 i2c_reg_write(I2C_MUX_IO2_ADDR, 2, 0xFF);
36 mdelay(50);
37 #endif
38 }
39
pfe_eth_board_init(struct udevice * dev)40 int pfe_eth_board_init(struct udevice *dev)
41 {
42 static int init_done;
43 struct mii_dev *bus;
44 struct pfe_mdio_info mac_mdio_info;
45 struct pfe_eth_dev *priv = dev_get_priv(dev);
46 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
47
48 int srds_s1 = in_be32(&gur->rcwsr[4]) &
49 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
50 srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
51
52 if (!init_done) {
53 ls1012ardb_reset_phy();
54 mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR;
55 mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
56
57 bus = pfe_mdio_init(&mac_mdio_info);
58 if (!bus) {
59 printf("Failed to register mdio\n");
60 return -1;
61 }
62 init_done = 1;
63 }
64
65 pfe_set_mdio(priv->gemac_port,
66 miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
67
68 switch (srds_s1) {
69 case 0x3508:
70 if (!priv->gemac_port) {
71 /* MAC1 */
72 pfe_set_phy_address_mode(priv->gemac_port,
73 CONFIG_PFE_EMAC1_PHY_ADDR,
74 PHY_INTERFACE_MODE_SGMII);
75 } else {
76 /* MAC2 */
77 pfe_set_phy_address_mode(priv->gemac_port,
78 CONFIG_PFE_EMAC2_PHY_ADDR,
79 PHY_INTERFACE_MODE_RGMII_TXID);
80 }
81 break;
82 case 0x2208:
83 if (!priv->gemac_port) {
84 /* MAC1 */
85 pfe_set_phy_address_mode(priv->gemac_port,
86 CONFIG_PFE_EMAC1_PHY_ADDR,
87 PHY_INTERFACE_MODE_SGMII_2500);
88 } else {
89 /* MAC2 */
90 pfe_set_phy_address_mode(priv->gemac_port,
91 CONFIG_PFE_EMAC2_PHY_ADDR,
92 PHY_INTERFACE_MODE_SGMII_2500);
93 }
94 break;
95 default:
96 printf("unsupported SerDes PRCTL= %d\n", srds_s1);
97 break;
98 }
99 return 0;
100 }
101
102 static struct pfe_eth_pdata pfe_pdata0 = {
103 .pfe_eth_pdata_mac = {
104 .iobase = (phys_addr_t)EMAC1_BASE_ADDR,
105 .phy_interface = 0,
106 },
107
108 .pfe_ddr_addr = {
109 .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
110 .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
111 },
112 };
113
114 static struct pfe_eth_pdata pfe_pdata1 = {
115 .pfe_eth_pdata_mac = {
116 .iobase = (phys_addr_t)EMAC2_BASE_ADDR,
117 .phy_interface = 1,
118 },
119
120 .pfe_ddr_addr = {
121 .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
122 .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
123 },
124 };
125
126 U_BOOT_DEVICE(ls1012a_pfe0) = {
127 .name = "pfe_eth",
128 .platdata = &pfe_pdata0,
129 };
130
131 U_BOOT_DEVICE(ls1012a_pfe1) = {
132 .name = "pfe_eth",
133 .platdata = &pfe_pdata1,
134 };
135