1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2015 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <i2c.h>
8 #include <fdt_support.h>
9 #include <fsl_ddr_sdram.h>
10 #include <asm/io.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/fsl_serdes.h>
13 #include <asm/arch/ppa.h>
14 #include <asm/arch/fdt.h>
15 #include <asm/arch/mmu.h>
16 #include <asm/arch/soc.h>
17 #include <ahci.h>
18 #include <hwconfig.h>
19 #include <mmc.h>
20 #include <scsi.h>
21 #include <fm_eth.h>
22 #include <fsl_esdhc.h>
23 #include <fsl_ifc.h>
24 #include <spl.h>
25
26 #include "../common/qixis.h"
27 #include "ls1043aqds_qixis.h"
28
29 DECLARE_GLOBAL_DATA_PTR;
30
31 enum {
32 MUX_TYPE_GPIO,
33 };
34
35 /* LS1043AQDS serdes mux */
36 #define CFG_SD_MUX1_SLOT2 0x0 /* SLOT2 TX/RX0 */
37 #define CFG_SD_MUX1_SLOT1 0x1 /* SLOT1 TX/RX1 */
38 #define CFG_SD_MUX2_SLOT3 0x0 /* SLOT3 TX/RX0 */
39 #define CFG_SD_MUX2_SLOT1 0x1 /* SLOT1 TX/RX2 */
40 #define CFG_SD_MUX3_SLOT4 0x0 /* SLOT4 TX/RX0 */
41 #define CFG_SD_MUX3_MUX4 0x1 /* MUX4 */
42 #define CFG_SD_MUX4_SLOT3 0x0 /* SLOT3 TX/RX1 */
43 #define CFG_SD_MUX4_SLOT1 0x1 /* SLOT1 TX/RX3 */
44 #define CFG_UART_MUX_MASK 0x6
45 #define CFG_UART_MUX_SHIFT 1
46 #define CFG_LPUART_EN 0x1
47
checkboard(void)48 int checkboard(void)
49 {
50 char buf[64];
51 #ifndef CONFIG_SD_BOOT
52 u8 sw;
53 #endif
54
55 puts("Board: LS1043AQDS, boot from ");
56
57 #ifdef CONFIG_SD_BOOT
58 puts("SD\n");
59 #else
60 sw = QIXIS_READ(brdcfg[0]);
61 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
62
63 if (sw < 0x8)
64 printf("vBank: %d\n", sw);
65 else if (sw == 0x8)
66 puts("PromJet\n");
67 else if (sw == 0x9)
68 puts("NAND\n");
69 else if (sw == 0xF)
70 printf("QSPI\n");
71 else
72 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
73 #endif
74
75 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
76 QIXIS_READ(id), QIXIS_READ(arch));
77
78 printf("FPGA: v%d (%s), build %d\n",
79 (int)QIXIS_READ(scver), qixis_read_tag(buf),
80 (int)qixis_read_minor());
81
82 return 0;
83 }
84
if_board_diff_clk(void)85 bool if_board_diff_clk(void)
86 {
87 u8 diff_conf = QIXIS_READ(brdcfg[11]);
88
89 return diff_conf & 0x40;
90 }
91
get_board_sys_clk(void)92 unsigned long get_board_sys_clk(void)
93 {
94 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
95
96 switch (sysclk_conf & 0x0f) {
97 case QIXIS_SYSCLK_64:
98 return 64000000;
99 case QIXIS_SYSCLK_83:
100 return 83333333;
101 case QIXIS_SYSCLK_100:
102 return 100000000;
103 case QIXIS_SYSCLK_125:
104 return 125000000;
105 case QIXIS_SYSCLK_133:
106 return 133333333;
107 case QIXIS_SYSCLK_150:
108 return 150000000;
109 case QIXIS_SYSCLK_160:
110 return 160000000;
111 case QIXIS_SYSCLK_166:
112 return 166666666;
113 }
114
115 return 66666666;
116 }
117
get_board_ddr_clk(void)118 unsigned long get_board_ddr_clk(void)
119 {
120 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
121
122 if (if_board_diff_clk())
123 return get_board_sys_clk();
124 switch ((ddrclk_conf & 0x30) >> 4) {
125 case QIXIS_DDRCLK_100:
126 return 100000000;
127 case QIXIS_DDRCLK_125:
128 return 125000000;
129 case QIXIS_DDRCLK_133:
130 return 133333333;
131 }
132
133 return 66666666;
134 }
135
select_i2c_ch_pca9547(u8 ch)136 int select_i2c_ch_pca9547(u8 ch)
137 {
138 int ret;
139
140 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
141 if (ret) {
142 puts("PCA: failed to select proper channel\n");
143 return ret;
144 }
145
146 return 0;
147 }
148
dram_init(void)149 int dram_init(void)
150 {
151 /*
152 * When resuming from deep sleep, the I2C channel may not be
153 * in the default channel. So, switch to the default channel
154 * before accessing DDR SPD.
155 */
156 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
157 fsl_initdram();
158 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
159 /* This will break-before-make MMU for DDR */
160 update_early_mmu_table();
161 #endif
162
163 return 0;
164 }
165
i2c_multiplexer_select_vid_channel(u8 channel)166 int i2c_multiplexer_select_vid_channel(u8 channel)
167 {
168 return select_i2c_ch_pca9547(channel);
169 }
170
board_retimer_init(void)171 void board_retimer_init(void)
172 {
173 u8 reg;
174
175 /* Retimer is connected to I2C1_CH7_CH5 */
176 select_i2c_ch_pca9547(I2C_MUX_CH7);
177 reg = I2C_MUX_CH5;
178 i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, ®, 1);
179
180 /* Access to Control/Shared register */
181 reg = 0x0;
182 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
183
184 /* Read device revision and ID */
185 i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);
186 debug("Retimer version id = 0x%x\n", reg);
187
188 /* Enable Broadcast. All writes target all channel register sets */
189 reg = 0x0c;
190 i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
191
192 /* Reset Channel Registers */
193 i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);
194 reg |= 0x4;
195 i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);
196
197 /* Enable override divider select and Enable Override Output Mux */
198 i2c_read(I2C_RETIMER_ADDR, 9, 1, ®, 1);
199 reg |= 0x24;
200 i2c_write(I2C_RETIMER_ADDR, 9, 1, ®, 1);
201
202 /* Select VCO Divider to full rate (000) */
203 i2c_read(I2C_RETIMER_ADDR, 0x18, 1, ®, 1);
204 reg &= 0x8f;
205 i2c_write(I2C_RETIMER_ADDR, 0x18, 1, ®, 1);
206
207 /* Selects active PFD MUX Input as Re-timed Data (001) */
208 i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1);
209 reg &= 0x3f;
210 reg |= 0x20;
211 i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1);
212
213 /* Set data rate as 10.3125 Gbps */
214 reg = 0x0;
215 i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);
216 reg = 0xb2;
217 i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);
218 reg = 0x90;
219 i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);
220 reg = 0xb3;
221 i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
222 reg = 0xcd;
223 i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
224
225 /* Return the default channel */
226 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
227 }
228
board_early_init_f(void)229 int board_early_init_f(void)
230 {
231 #ifdef CONFIG_HAS_FSL_XHCI_USB
232 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
233 u32 usb_pwrfault;
234 #endif
235 #ifdef CONFIG_LPUART
236 u8 uart;
237 #endif
238
239 #ifdef CONFIG_SYS_I2C_EARLY_INIT
240 i2c_early_init_f();
241 #endif
242 fsl_lsch2_early_init_f();
243
244 #ifdef CONFIG_HAS_FSL_XHCI_USB
245 out_be32(&scfg->rcwpmuxcr0, 0x3333);
246 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
247 usb_pwrfault =
248 (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
249 (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
250 (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
251 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
252 #endif
253
254 #ifdef CONFIG_LPUART
255 /* We use lpuart0 as system console */
256 uart = QIXIS_READ(brdcfg[14]);
257 uart &= ~CFG_UART_MUX_MASK;
258 uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
259 QIXIS_WRITE(brdcfg[14], uart);
260 #endif
261
262 return 0;
263 }
264
265 #ifdef CONFIG_FSL_DEEP_SLEEP
266 /* determine if it is a warm boot */
is_warm_boot(void)267 bool is_warm_boot(void)
268 {
269 #define DCFG_CCSR_CRSTSR_WDRFR (1 << 3)
270 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
271
272 if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
273 return 1;
274
275 return 0;
276 }
277 #endif
278
config_board_mux(int ctrl_type)279 int config_board_mux(int ctrl_type)
280 {
281 u8 reg14;
282
283 reg14 = QIXIS_READ(brdcfg[14]);
284
285 switch (ctrl_type) {
286 case MUX_TYPE_GPIO:
287 reg14 = (reg14 & (~0x30)) | 0x20;
288 break;
289 default:
290 puts("Unsupported mux interface type\n");
291 return -1;
292 }
293
294 QIXIS_WRITE(brdcfg[14], reg14);
295
296 return 0;
297 }
298
config_serdes_mux(void)299 int config_serdes_mux(void)
300 {
301 return 0;
302 }
303
304
305 #ifdef CONFIG_MISC_INIT_R
misc_init_r(void)306 int misc_init_r(void)
307 {
308 if (hwconfig("gpio"))
309 config_board_mux(MUX_TYPE_GPIO);
310
311 return 0;
312 }
313 #endif
314
board_init(void)315 int board_init(void)
316 {
317 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
318 erratum_a010315();
319 #endif
320
321 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
322 board_retimer_init();
323
324 #ifdef CONFIG_SYS_FSL_SERDES
325 config_serdes_mux();
326 #endif
327
328 #ifdef CONFIG_FSL_LS_PPA
329 ppa_init();
330 #endif
331
332 return 0;
333 }
334
335 #ifdef CONFIG_OF_BOARD_SETUP
ft_board_setup(void * blob,bd_t * bd)336 int ft_board_setup(void *blob, bd_t *bd)
337 {
338 u64 base[CONFIG_NR_DRAM_BANKS];
339 u64 size[CONFIG_NR_DRAM_BANKS];
340 u8 reg;
341
342 /* fixup DT for the two DDR banks */
343 base[0] = gd->bd->bi_dram[0].start;
344 size[0] = gd->bd->bi_dram[0].size;
345 base[1] = gd->bd->bi_dram[1].start;
346 size[1] = gd->bd->bi_dram[1].size;
347
348 fdt_fixup_memory_banks(blob, base, size, 2);
349 ft_cpu_setup(blob, bd);
350
351 #ifdef CONFIG_SYS_DPAA_FMAN
352 fdt_fixup_fman_ethernet(blob);
353 fdt_fixup_board_enet(blob);
354 #endif
355
356 reg = QIXIS_READ(brdcfg[0]);
357 reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
358
359 /* Disable IFC if QSPI is enabled */
360 if (reg == 0xF)
361 do_fixup_by_compat(blob, "fsl,ifc",
362 "status", "disabled", 8 + 1, 1);
363
364 return 0;
365 }
366 #endif
367
flash_read8(void * addr)368 u8 flash_read8(void *addr)
369 {
370 return __raw_readb(addr + 1);
371 }
372
flash_write16(u16 val,void * addr)373 void flash_write16(u16 val, void *addr)
374 {
375 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
376
377 __raw_writew(shftval, addr);
378 }
379
flash_read16(void * addr)380 u16 flash_read16(void *addr)
381 {
382 u16 val = __raw_readw(addr);
383
384 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
385 }
386