1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2015 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <fsl_ddr_sdram.h>
8 #include <fsl_ddr_dimm_params.h>
9 #include "ddr.h"
10 #ifdef CONFIG_FSL_DEEP_SLEEP
11 #include <fsl_sleep.h>
12 #endif
13 #include <asm/arch/clock.h>
14
15 DECLARE_GLOBAL_DATA_PTR;
16
fsl_ddr_board_options(memctl_options_t * popts,dimm_params_t * pdimm,unsigned int ctrl_num)17 void fsl_ddr_board_options(memctl_options_t *popts,
18 dimm_params_t *pdimm,
19 unsigned int ctrl_num)
20 {
21 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
22 ulong ddr_freq;
23
24 if (ctrl_num > 1) {
25 printf("Not supported controller number %d\n", ctrl_num);
26 return;
27 }
28 if (!pdimm->n_ranks)
29 return;
30
31 pbsp = udimms[0];
32
33 /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
34 * freqency and n_banks specified in board_specific_parameters table.
35 */
36 ddr_freq = get_ddr_freq(0) / 1000000;
37 while (pbsp->datarate_mhz_high) {
38 if (pbsp->n_ranks == pdimm->n_ranks) {
39 if (ddr_freq <= pbsp->datarate_mhz_high) {
40 popts->clk_adjust = pbsp->clk_adjust;
41 popts->wrlvl_start = pbsp->wrlvl_start;
42 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
43 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
44 popts->cpo_override = pbsp->cpo_override;
45 popts->write_data_delay =
46 pbsp->write_data_delay;
47 goto found;
48 }
49 pbsp_highest = pbsp;
50 }
51 pbsp++;
52 }
53
54 if (pbsp_highest) {
55 printf("Error: board specific timing not found for %lu MT/s\n",
56 ddr_freq);
57 printf("Trying to use the highest speed (%u) parameters\n",
58 pbsp_highest->datarate_mhz_high);
59 popts->clk_adjust = pbsp_highest->clk_adjust;
60 popts->wrlvl_start = pbsp_highest->wrlvl_start;
61 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
62 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
63 } else {
64 panic("DIMM is not supported by this board");
65 }
66 found:
67 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
68 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
69
70 /* force DDR bus width to 32 bits */
71 popts->data_bus_width = 1;
72 popts->otf_burst_chop_en = 0;
73 popts->burst_length = DDR_BL8;
74
75 /*
76 * Factors to consider for half-strength driver enable:
77 * - number of DIMMs installed
78 */
79 popts->half_strength_driver_enable = 1;
80 /*
81 * Write leveling override
82 */
83 popts->wrlvl_override = 1;
84 popts->wrlvl_sample = 0xf;
85
86 /*
87 * Rtt and Rtt_WR override
88 */
89 popts->rtt_override = 0;
90
91 /* Enable ZQ calibration */
92 popts->zq_en = 1;
93
94 /* optimize cpo for erratum A-009942 */
95 popts->cpo_sample = 0x46;
96
97 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
98 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
99 DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
100 }
101
102 /* DDR model number: MT40A512M8HX-093E */
103 #ifdef CONFIG_SYS_DDR_RAW_TIMING
104 dimm_params_t ddr_raw_timing = {
105 .n_ranks = 1,
106 .rank_density = 2147483648u,
107 .capacity = 2147483648u,
108 .primary_sdram_width = 32,
109 .ec_sdram_width = 0,
110 .registered_dimm = 0,
111 .mirrored_dimm = 0,
112 .n_row_addr = 15,
113 .n_col_addr = 10,
114 .bank_addr_bits = 0,
115 .bank_group_bits = 2,
116 .edc_config = 0,
117 .burst_lengths_bitmask = 0x0c,
118
119 .tckmin_x_ps = 938,
120 .tckmax_ps = 1500,
121 .caslat_x = 0x000DFA00,
122 .taa_ps = 13500,
123 .trcd_ps = 13500,
124 .trp_ps = 13500,
125 .tras_ps = 33000,
126 .trc_ps = 46500,
127 .trfc1_ps = 260000,
128 .trfc2_ps = 160000,
129 .trfc4_ps = 110000,
130 .tfaw_ps = 21000,
131 .trrds_ps = 3700,
132 .trrdl_ps = 5300,
133 .tccdl_ps = 5355,
134 .refresh_rate_ps = 7800000,
135 .dq_mapping[0] = 0x0,
136 .dq_mapping[1] = 0x0,
137 .dq_mapping[2] = 0x0,
138 .dq_mapping[3] = 0x0,
139 .dq_mapping[4] = 0x0,
140 .dq_mapping[5] = 0x0,
141 .dq_mapping[6] = 0x0,
142 .dq_mapping[7] = 0x0,
143 .dq_mapping[8] = 0x0,
144 .dq_mapping[9] = 0x0,
145 .dq_mapping[10] = 0x0,
146 .dq_mapping[11] = 0x0,
147 .dq_mapping[12] = 0x0,
148 .dq_mapping[13] = 0x0,
149 .dq_mapping[14] = 0x0,
150 .dq_mapping[15] = 0x0,
151 .dq_mapping[16] = 0x0,
152 .dq_mapping[17] = 0x0,
153 .dq_mapping_ors = 0,
154 };
155
fsl_ddr_get_dimm_params(dimm_params_t * pdimm,unsigned int controller_number,unsigned int dimm_number)156 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
157 unsigned int controller_number,
158 unsigned int dimm_number)
159 {
160 static const char dimm_model[] = "Fixed DDR on board";
161
162 if (((controller_number == 0) && (dimm_number == 0)) ||
163 ((controller_number == 1) && (dimm_number == 0))) {
164 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
165 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
166 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
167 }
168
169 return 0;
170 }
171 #else
172
fixed_sdram(void)173 phys_size_t fixed_sdram(void)
174 {
175 int i;
176 char buf[32];
177 fsl_ddr_cfg_regs_t ddr_cfg_regs;
178 phys_size_t ddr_size;
179 ulong ddr_freq, ddr_freq_mhz;
180
181 ddr_freq = get_ddr_freq(0);
182 ddr_freq_mhz = ddr_freq / 1000000;
183
184 printf("Configuring DDR for %s MT/s data rate\n",
185 strmhz(buf, ddr_freq));
186
187 for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
188 if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
189 (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
190 memcpy(&ddr_cfg_regs,
191 fixed_ddr_parm_0[i].ddr_settings,
192 sizeof(ddr_cfg_regs));
193 break;
194 }
195 }
196
197 if (fixed_ddr_parm_0[i].max_freq == 0)
198 panic("Unsupported DDR data rate %s MT/s data rate\n",
199 strmhz(buf, ddr_freq));
200
201 ddr_size = (phys_size_t)2048 * 1024 * 1024;
202 fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
203
204 return ddr_size;
205 }
206 #endif
207
fsl_initdram(void)208 int fsl_initdram(void)
209 {
210 phys_size_t dram_size;
211
212 #ifdef CONFIG_SYS_DDR_RAW_TIMING
213 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
214 puts("Initializing DDR....\n");
215 dram_size = fsl_ddr_sdram();
216 #else
217 dram_size = fsl_ddr_sdram_size();
218 #endif
219 #else
220 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
221 puts("Initialzing DDR using fixed setting\n");
222 dram_size = fixed_sdram();
223 #else
224 gd->ram_size = 0x80000000;
225
226 return 0;
227 #endif
228 #endif
229 erratum_a008850_post();
230
231 #ifdef CONFIG_FSL_DEEP_SLEEP
232 fsl_dp_ddr_restore();
233 #endif
234
235 gd->ram_size = dram_size;
236
237 return 0;
238 }
239