1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
4 *
5 * Author: Scott Wood <scottwood@freescale.com>
6 */
7
8 #include <common.h>
9 #if defined(CONFIG_OF_LIBFDT)
10 #include <linux/libfdt.h>
11 #endif
12 #include <pci.h>
13 #include <mpc83xx.h>
14 #include <vsc7385.h>
15 #include <ns16550.h>
16 #include <nand.h>
17 #if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
18 #include <asm/gpio.h>
19 #endif
20
21 DECLARE_GLOBAL_DATA_PTR;
22
board_early_init_f(void)23 int board_early_init_f(void)
24 {
25 #ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
26 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
27
28 if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
29 gd->flags |= GD_FLG_SILENT;
30 #endif
31 #if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
32 mpc83xx_gpio_init_f();
33 #endif
34
35 return 0;
36 }
37
board_early_init_r(void)38 int board_early_init_r(void)
39 {
40 #if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
41 mpc83xx_gpio_init_r();
42 #endif
43
44 return 0;
45 }
46
checkboard(void)47 int checkboard(void)
48 {
49 puts("Board: Freescale MPC8313ERDB\n");
50 return 0;
51 }
52
53 #ifndef CONFIG_SPL_BUILD
54 static struct pci_region pci_regions[] = {
55 {
56 .bus_start = CONFIG_SYS_PCI1_MEM_BASE,
57 .phys_start = CONFIG_SYS_PCI1_MEM_PHYS,
58 .size = CONFIG_SYS_PCI1_MEM_SIZE,
59 .flags = PCI_REGION_MEM | PCI_REGION_PREFETCH
60 },
61 {
62 .bus_start = CONFIG_SYS_PCI1_MMIO_BASE,
63 .phys_start = CONFIG_SYS_PCI1_MMIO_PHYS,
64 .size = CONFIG_SYS_PCI1_MMIO_SIZE,
65 .flags = PCI_REGION_MEM
66 },
67 {
68 .bus_start = CONFIG_SYS_PCI1_IO_BASE,
69 .phys_start = CONFIG_SYS_PCI1_IO_PHYS,
70 .size = CONFIG_SYS_PCI1_IO_SIZE,
71 .flags = PCI_REGION_IO
72 }
73 };
74
pci_init_board(void)75 void pci_init_board(void)
76 {
77 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
78 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
79 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
80 struct pci_region *reg[] = { pci_regions };
81
82 /* Enable all 3 PCI_CLK_OUTPUTs. */
83 clk->occr |= 0xe0000000;
84
85 /*
86 * Configure PCI Local Access Windows
87 */
88 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
89 pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
90
91 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
92 pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
93
94 mpc83xx_pci_init(1, reg);
95 }
96
97 /*
98 * Miscellaneous late-boot configurations
99 *
100 * If a VSC7385 microcode image is present, then upload it.
101 */
misc_init_r(void)102 int misc_init_r(void)
103 {
104 int rc = 0;
105
106 #ifdef CONFIG_VSC7385_IMAGE
107 if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
108 CONFIG_VSC7385_IMAGE_SIZE)) {
109 puts("Failure uploading VSC7385 microcode.\n");
110 rc = 1;
111 }
112 #endif
113
114 return rc;
115 }
116
117 #if defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,bd_t * bd)118 int ft_board_setup(void *blob, bd_t *bd)
119 {
120 ft_cpu_setup(blob, bd);
121 #ifdef CONFIG_PCI
122 ft_pci_setup(blob, bd);
123 #endif
124
125 return 0;
126 }
127 #endif
128 #else /* CONFIG_SPL_BUILD */
board_init_f(ulong bootflag)129 void board_init_f(ulong bootflag)
130 {
131 board_early_init_f();
132 NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
133 CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
134 puts("NAND boot... ");
135 timer_init();
136 dram_init();
137 relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd,
138 CONFIG_SYS_NAND_U_BOOT_RELOC);
139 }
140
board_init_r(gd_t * gd,ulong dest_addr)141 void board_init_r(gd_t *gd, ulong dest_addr)
142 {
143 nand_boot();
144 }
145
putc(char c)146 void putc(char c)
147 {
148 if (gd->flags & GD_FLG_SILENT)
149 return;
150
151 if (c == '\n')
152 NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
153
154 NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
155 }
156 #endif
157