1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2010-2011 Freescale Semiconductor, Inc. 4 */ 5 6 #include <common.h> 7 #include <asm/mmu.h> 8 9 struct fsl_e_tlb_entry tlb_table[] = { 10 /* TLB 0 - for temp stack in cache */ 11 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, 12 CONFIG_SYS_INIT_RAM_ADDR_PHYS, 13 MAS3_SX|MAS3_SW|MAS3_SR, 0, 14 0, 0, BOOKE_PAGESZ_4K, 0), 15 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , 16 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, 17 MAS3_SX|MAS3_SW|MAS3_SR, 0, 18 0, 0, BOOKE_PAGESZ_4K, 0), 19 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , 20 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, 21 MAS3_SX|MAS3_SW|MAS3_SR, 0, 22 0, 0, BOOKE_PAGESZ_4K, 0), 23 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , 24 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, 25 MAS3_SX|MAS3_SW|MAS3_SR, 0, 26 0, 0, BOOKE_PAGESZ_4K, 0), 27 28 /* TLB 1 */ 29 /* *I*** - Covers boot page */ 30 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 31 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, 32 0, 0, BOOKE_PAGESZ_4K, 1), 33 34 /* *I*G* - CCSRBAR */ 35 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 36 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 37 0, 1, BOOKE_PAGESZ_1M, 1), 38 39 #ifndef CONFIG_SPL_BUILD 40 /* W**G* - Flash/promjet, localbus */ 41 /* This will be changed to *I*G* after relocation to RAM. */ 42 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 43 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 44 0, 2, BOOKE_PAGESZ_64M, 1), 45 46 #ifdef CONFIG_PCI 47 /* *I*G* - PCI memory 1.5G */ 48 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 49 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 50 0, 3, BOOKE_PAGESZ_1G, 1), 51 52 /* *I*G* - PCI I/O effective: 192K */ 53 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 54 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 55 0, 4, BOOKE_PAGESZ_256K, 1), 56 #endif 57 58 #ifdef CONFIG_VSC7385_ENET 59 /* *I*G - VSC7385 Switch */ 60 SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS, 61 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 62 0, 5, BOOKE_PAGESZ_1M, 1), 63 #endif 64 65 SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, 66 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 67 0, 6, BOOKE_PAGESZ_1M, 1), 68 SET_TLB_ENTRY(1, CONFIG_SYS_PMC_BASE, CONFIG_SYS_PMC_BASE_PHYS, 69 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 70 0, 10, BOOKE_PAGESZ_64K, 1), 71 #endif /* not SPL */ 72 73 #ifdef CONFIG_SYS_NAND_BASE 74 /* *I*G - NAND */ 75 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 76 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 77 0, 7, BOOKE_PAGESZ_1M, 1), 78 #endif 79 80 #if defined(CONFIG_SYS_RAMBOOT) || \ 81 (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR)) 82 /* *I*G - eSDHC/eSPI/NAND boot */ 83 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, 84 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 85 0, 8, BOOKE_PAGESZ_1G, 1), 86 87 #if defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD) 88 /* 2G DDR on P1020MBG, map the second 1G */ 89 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, 90 CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, 91 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 92 0, 9, BOOKE_PAGESZ_1G, 1), 93 #endif /* TARGET_P1020MBG */ 94 #endif /* RAMBOOT/SPL */ 95 96 #ifdef CONFIG_SYS_INIT_L2_ADDR 97 /* *I*G - L2SRAM */ 98 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, 99 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 100 0, 11, BOOKE_PAGESZ_256K, 1), 101 #if CONFIG_SYS_L2_SIZE >= (256 << 10) 102 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, 103 CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, 104 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 105 0, 12, BOOKE_PAGESZ_256K, 1) 106 #endif 107 #endif 108 }; 109 110 int num_tlb_entries = ARRAY_SIZE(tlb_table); 111