1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2013 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <command.h>
8 #include <hwconfig.h>
9 #include <pci.h>
10 #include <i2c.h>
11 #include <asm/processor.h>
12 #include <asm/mmu.h>
13 #include <asm/cache.h>
14 #include <asm/immap_85xx.h>
15 #include <asm/fsl_pci.h>
16 #include <fsl_ddr_sdram.h>
17 #include <asm/io.h>
18 #include <asm/fsl_law.h>
19 #include <asm/fsl_lbc.h>
20 #include <asm/mp.h>
21 #include <miiphy.h>
22 #include <linux/libfdt.h>
23 #include <fdt_support.h>
24 #include <fsl_mdio.h>
25 #include <tsec.h>
26 #include <ioports.h>
27 #include <asm/fsl_serdes.h>
28 #include <netdev.h>
29
30 #define SYSCLK_64 64000000
31 #define SYSCLK_66 66666666
32
get_board_sys_clk(ulong dummy)33 unsigned long get_board_sys_clk(ulong dummy)
34 {
35 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
36 par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
37 unsigned int cpdat_val = 0;
38
39 /* Set-up up pin muxing based on board switch settings */
40 cpdat_val = par_io[1].cpdat;
41
42 /* Check switch setting for SYSCLK select (PB3) */
43 if (cpdat_val & 0x10000000)
44 return SYSCLK_64;
45 else
46 return SYSCLK_66;
47
48 return 0;
49 }
50
51 #ifdef CONFIG_QE
52
53 #define PCA_IOPORT_I2C_ADDR 0x23
54 #define PCA_IOPORT_OUTPUT_CMD 0x2
55 #define PCA_IOPORT_CFG_CMD 0x6
56
57 const qe_iop_conf_t qe_iop_conf_tab[] = {
58
59 #ifdef CONFIG_TWR_P1025
60 /* GPIO */
61 {1, 0, 1, 0, 0},
62 {1, 18, 1, 0, 0},
63
64 /* GPIO for switch options */
65 {1, 2, 2, 0, 0}, /* PROFIBUS_MODE_SEL */
66 {1, 3, 2, 0, 0}, /* SYS_CLK_SELECT */
67 {1, 29, 2, 0, 0}, /* LOCALBUS_QE_MUXSEL */
68 {1, 30, 2, 0, 0}, /* ETH_TDM_SEL */
69
70 /* QE_MUX_MDC */
71 {1, 19, 1, 0, 1}, /* QE_MUX_MDC */
72
73 /* QE_MUX_MDIO */
74 {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */
75
76 /* UCC_1_MII */
77 {0, 23, 2, 0, 2}, /* CLK12 */
78 {0, 24, 2, 0, 1}, /* CLK9 */
79 {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */
80 {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */
81 {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */
82 {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
83 {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */
84 {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */
85 {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
86 {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
87 {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
88 {0, 13, 1, 0, 2}, /* ENET1_TX_ER */
89 {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */
90 {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */
91 {0, 17, 2, 0, 2}, /* ENET1_CRS */
92 {0, 16, 2, 0, 2}, /* ENET1_COL */
93
94 /* UCC_5_RMII */
95 {1, 11, 2, 0, 1}, /* CLK13 */
96 {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */
97 {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */
98 {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */
99 {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */
100 {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */
101 {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */
102 {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */
103
104 /* TDMA - clock option is configured in OS based on board setting */
105 {1, 23, 2, 0, 2}, /* TDMA_TXD */
106 {1, 25, 2, 0, 2}, /* TDMA_RXD */
107 {1, 26, 1, 0, 2}, /* TDMA_SYNC */
108 #endif
109
110 {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
111 };
112 #endif
113
board_early_init_f(void)114 int board_early_init_f(void)
115 {
116 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
117
118 setbits_be32(&gur->pmuxcr,
119 (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
120
121 /* SDHC_DAT[4:7] not exposed to pins (use as SPI) */
122 clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
123
124 return 0;
125 }
126
checkboard(void)127 int checkboard(void)
128 {
129 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
130 u8 boot_status;
131
132 printf("Board: %s\n", CONFIG_BOARDNAME);
133
134 boot_status = ((gur->porbmsr) >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;
135 puts("rom_loc: ");
136 if (boot_status == PORBMSR_ROMLOC_NOR)
137 puts("nor flash");
138 else if (boot_status == PORBMSR_ROMLOC_SDHC)
139 puts("sd");
140 else
141 puts("unknown");
142 puts("\n");
143
144 return 0;
145 }
146
147 #ifdef CONFIG_PCI
pci_init_board(void)148 void pci_init_board(void)
149 {
150 fsl_pcie_init_board(0);
151 }
152 #endif
153
board_early_init_r(void)154 int board_early_init_r(void)
155 {
156 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
157 int flash_esel = find_tlb_idx((void *)flashbase, 1);
158
159 /*
160 * Remap Boot flash region to caching-inhibited
161 * so that flash can be erased properly.
162 */
163
164 /* Flush d-cache and invalidate i-cache of any FLASH data */
165 flush_dcache();
166 invalidate_icache();
167
168 if (flash_esel == -1) {
169 /* very unlikely unless something is messed up */
170 puts("Error: Could not find TLB for FLASH BASE\n");
171 flash_esel = 2; /* give our best effort to continue */
172 } else {
173 /* invalidate existing TLB entry for flash */
174 disable_tlb(flash_esel);
175 }
176
177 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
178 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
179 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
180 return 0;
181 }
182
board_eth_init(bd_t * bis)183 int board_eth_init(bd_t *bis)
184 {
185 struct fsl_pq_mdio_info mdio_info;
186 struct tsec_info_struct tsec_info[4];
187 ccsr_gur_t *gur __attribute__((unused)) =
188 (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
189 int num = 0;
190
191 #ifdef CONFIG_TSEC1
192 SET_STD_TSEC_INFO(tsec_info[num], 1);
193 num++;
194 #endif
195 #ifdef CONFIG_TSEC2
196 SET_STD_TSEC_INFO(tsec_info[num], 2);
197 if (is_serdes_configured(SGMII_TSEC2)) {
198 printf("eTSEC2 is in sgmii mode.\n");
199 tsec_info[num].flags |= TSEC_SGMII;
200 }
201 num++;
202 #endif
203 #ifdef CONFIG_TSEC3
204 SET_STD_TSEC_INFO(tsec_info[num], 3);
205 num++;
206 #endif
207
208 if (!num) {
209 printf("No TSECs initialized\n");
210 return 0;
211 }
212
213 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
214 mdio_info.name = DEFAULT_MII_NAME;
215
216 fsl_pq_mdio_init(bis, &mdio_info);
217
218 tsec_eth_init(bis, tsec_info, num);
219
220 #if defined(CONFIG_UEC_ETH)
221 /* QE0 and QE3 need to be exposed for UCC1
222 * and UCC5 Eth mode (in PMUXCR register).
223 * Currently QE/LBC muxed pins assumed to be
224 * LBC for U-Boot and PMUXCR updated by OS if required */
225
226 uec_standard_init(bis);
227 #endif
228
229 return pci_eth_init(bis);
230 }
231
232 #if defined(CONFIG_QE)
fdt_board_fixup_qe_pins(void * blob)233 static void fdt_board_fixup_qe_pins(void *blob)
234 {
235 int node;
236
237 if (!hwconfig("qe")) {
238 /* For QE and eLBC pins multiplexing,
239 * When don't use QE function, remove
240 * qe node from dt blob.
241 */
242 node = fdt_path_offset(blob, "/qe");
243 if (node >= 0)
244 fdt_del_node(blob, node);
245 } else {
246 /* For TWR Peripheral Modules - TWR-SER2
247 * board only can support Signal Port MII,
248 * so delete one UEC node when use MII port.
249 */
250 if (hwconfig("mii"))
251 node = fdt_path_offset(blob, "/qe/ucc@2400");
252 else
253 node = fdt_path_offset(blob, "/qe/ucc@2000");
254 if (node >= 0)
255 fdt_del_node(blob, node);
256 }
257
258 return;
259 }
260 #endif
261
262 #ifdef CONFIG_OF_BOARD_SETUP
ft_board_setup(void * blob,bd_t * bd)263 int ft_board_setup(void *blob, bd_t *bd)
264 {
265 phys_addr_t base;
266 phys_size_t size;
267
268 ft_cpu_setup(blob, bd);
269
270 base = env_get_bootm_low();
271 size = env_get_bootm_size();
272
273 fdt_fixup_memory(blob, (u64)base, (u64)size);
274
275 FT_FSL_PCI_SETUP;
276
277 #ifdef CONFIG_QE
278 do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
279 sizeof("okay"), 0);
280 #endif
281 #if defined(CONFIG_TWR_P1025)
282 fdt_board_fixup_qe_pins(blob);
283 #endif
284 fsl_fdt_fixup_dr_usb(blob, bd);
285
286 return 0;
287 }
288 #endif
289