1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2013 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <i2c.h>
8 #include <hwconfig.h>
9 #include <asm/mmu.h>
10 #include <fsl_ddr_sdram.h>
11 #include <fsl_ddr_dimm_params.h>
12 #include <asm/fsl_law.h>
13 #include "ddr.h"
14
15 DECLARE_GLOBAL_DATA_PTR;
16
fsl_ddr_board_options(memctl_options_t * popts,dimm_params_t * pdimm,unsigned int ctrl_num)17 void fsl_ddr_board_options(memctl_options_t *popts,
18 dimm_params_t *pdimm,
19 unsigned int ctrl_num)
20 {
21 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
22 ulong ddr_freq;
23
24 if (ctrl_num > 1) {
25 printf("Not supported controller number %d\n", ctrl_num);
26 return;
27 }
28 if (!pdimm->n_ranks)
29 return;
30
31 /*
32 * we use identical timing for all slots. If needed, change the code
33 * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
34 */
35 if (popts->registered_dimm_en)
36 pbsp = rdimms[0];
37 else
38 pbsp = udimms[0];
39
40 /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
41 * freqency and n_banks specified in board_specific_parameters table.
42 */
43 ddr_freq = get_ddr_freq(0) / 1000000;
44 while (pbsp->datarate_mhz_high) {
45 if (pbsp->n_ranks == pdimm->n_ranks &&
46 (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
47 if (ddr_freq <= pbsp->datarate_mhz_high) {
48 popts->clk_adjust = pbsp->clk_adjust;
49 popts->wrlvl_start = pbsp->wrlvl_start;
50 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
51 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
52 goto found;
53 }
54 pbsp_highest = pbsp;
55 }
56 pbsp++;
57 }
58
59 if (pbsp_highest) {
60 printf("Error: board specific timing not found");
61 printf("for data rate %lu MT/s\n", ddr_freq);
62 printf("Trying to use the highest speed (%u) parameters\n",
63 pbsp_highest->datarate_mhz_high);
64 popts->clk_adjust = pbsp_highest->clk_adjust;
65 popts->wrlvl_start = pbsp_highest->wrlvl_start;
66 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
67 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
68 } else {
69 panic("DIMM is not supported by this board");
70 }
71 found:
72 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
73 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
74 "wrlvl_ctrl_3 0x%x\n",
75 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
76 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
77 pbsp->wrlvl_ctl_3);
78
79 /*
80 * Factors to consider for half-strength driver enable:
81 * - number of DIMMs installed
82 */
83 popts->half_strength_driver_enable = 0;
84 /*
85 * Write leveling override
86 */
87 popts->wrlvl_override = 1;
88 popts->wrlvl_sample = 0xf;
89
90 /*
91 * Rtt and Rtt_WR override
92 */
93 popts->rtt_override = 0;
94
95 /* Enable ZQ calibration */
96 popts->zq_en = 1;
97
98 /* DHC_EN =1, ODT = 75 Ohm */
99 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
100 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
101
102 /* optimize cpo for erratum A-009942 */
103 popts->cpo_sample = 0x64;
104 }
105
dram_init(void)106 int dram_init(void)
107 {
108 phys_size_t dram_size;
109
110 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
111 puts("Initializing....using SPD\n");
112 dram_size = fsl_ddr_sdram();
113 #else
114 /* DDR has been initialised by first stage boot loader */
115 dram_size = fsl_ddr_sdram_size();
116 #endif
117 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
118 dram_size *= 0x100000;
119
120 gd->ram_size = dram_size;
121
122 return 0;
123 }
124