1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright 2013 Freescale Semiconductor, Inc.
3 */
4
5 #include <common.h>
6 #include <console.h>
7 #include <environment.h>
8 #include <malloc.h>
9 #include <ns16550.h>
10 #include <nand.h>
11 #include <i2c.h>
12 #include <mmc.h>
13 #include <fsl_esdhc.h>
14 #include <spi_flash.h>
15 #include "../common/qixis.h"
16 #include "t208xqds_qixis.h"
17 #include "../common/spl.h"
18
19 DECLARE_GLOBAL_DATA_PTR;
20
get_effective_memsize(void)21 phys_size_t get_effective_memsize(void)
22 {
23 return CONFIG_SYS_L3_SIZE;
24 }
25
get_board_sys_clk(void)26 unsigned long get_board_sys_clk(void)
27 {
28 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
29
30 switch (sysclk_conf & 0x0F) {
31 case QIXIS_SYSCLK_83:
32 return 83333333;
33 case QIXIS_SYSCLK_100:
34 return 100000000;
35 case QIXIS_SYSCLK_125:
36 return 125000000;
37 case QIXIS_SYSCLK_133:
38 return 133333333;
39 case QIXIS_SYSCLK_150:
40 return 150000000;
41 case QIXIS_SYSCLK_160:
42 return 160000000;
43 case QIXIS_SYSCLK_166:
44 return 166666666;
45 }
46 return 66666666;
47 }
48
get_board_ddr_clk(void)49 unsigned long get_board_ddr_clk(void)
50 {
51 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
52
53 switch ((ddrclk_conf & 0x30) >> 4) {
54 case QIXIS_DDRCLK_100:
55 return 100000000;
56 case QIXIS_DDRCLK_125:
57 return 125000000;
58 case QIXIS_DDRCLK_133:
59 return 133333333;
60 }
61 return 66666666;
62 }
63
board_init_f(ulong bootflag)64 void board_init_f(ulong bootflag)
65 {
66 u32 plat_ratio, sys_clk, ccb_clk;
67 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
68
69 /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
70 memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
71
72 /* Update GD pointer */
73 gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
74
75 console_init_f();
76
77 /* initialize selected port with appropriate baud rate */
78 sys_clk = get_board_sys_clk();
79 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
80 ccb_clk = sys_clk * plat_ratio / 2;
81
82 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
83 ccb_clk / 16 / CONFIG_BAUDRATE);
84
85 #if defined(CONFIG_SPL_MMC_BOOT)
86 puts("\nSD boot...\n");
87 #elif defined(CONFIG_SPL_SPI_BOOT)
88 puts("\nSPI boot...\n");
89 #elif defined(CONFIG_SPL_NAND_BOOT)
90 puts("\nNAND boot...\n");
91 #endif
92
93 relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
94 }
95
board_init_r(gd_t * gd,ulong dest_addr)96 void board_init_r(gd_t *gd, ulong dest_addr)
97 {
98 bd_t *bd;
99
100 bd = (bd_t *)(gd + sizeof(gd_t));
101 memset(bd, 0, sizeof(bd_t));
102 gd->bd = bd;
103 bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
104 bd->bi_memsize = CONFIG_SYS_L3_SIZE;
105
106 arch_cpu_init();
107 get_clocks();
108 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
109 CONFIG_SPL_RELOC_MALLOC_SIZE);
110 gd->flags |= GD_FLG_FULL_MALLOC_INIT;
111
112 #ifdef CONFIG_SPL_NAND_BOOT
113 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
114 (uchar *)CONFIG_ENV_ADDR);
115 #endif
116 #ifdef CONFIG_SPL_MMC_BOOT
117 mmc_initialize(bd);
118 mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
119 (uchar *)CONFIG_ENV_ADDR);
120 #endif
121 #ifdef CONFIG_SPL_SPI_BOOT
122 fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
123 (uchar *)CONFIG_ENV_ADDR);
124 #endif
125
126 gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
127 gd->env_valid = ENV_VALID;
128
129 i2c_init_all();
130
131 dram_init();
132
133 #ifdef CONFIG_SPL_MMC_BOOT
134 mmc_boot();
135 #elif defined(CONFIG_SPL_SPI_BOOT)
136 fsl_spi_boot();
137 #elif defined(CONFIG_SPL_NAND_BOOT)
138 nand_boot();
139 #endif
140 }
141