1# 2# Copyright 2013 Freescale Semiconductor, Inc. 3# 4# SPDX-License-Identifier: GPL-2.0+ 5# 6# Refer doc/README.pblimage for more details about how-to configure 7# and create PBL boot image 8# 9 10#PBI commands 11#Initialize CPC1 1209010000 00200400 1309138000 00000000 14091380c0 00000100 15#512KB SRAM 1609010100 00000000 1709010104 fff80009 1809010f00 08000000 19#enable CPC1 2009010000 80000000 21#Configure LAW for CPC1 2209000d00 00000000 2309000d04 fff80000 2409000d08 81000012 25#Initialize eSPI controller, default configuration is slow for eSPI to 26#load data, this configuration comes from u-boot eSPI driver. 2709110000 80000403 2809110020 2d170008 2909110024 00100008 3009110028 00100008 310911002c 00100008 32#Errata for slowing down the MDC clock to make it <= 2.5 MHZ 33094fc030 00008148 34094fd030 00008148 35#Configure alternate space 3609000010 00000000 3709000014 ff000000 3809000018 81000000 39#Flush PBL data 40091380c0 00100000 41