1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (C) 2013 Renesas Solutions Corp. 4 */ 5 6#include <config.h> 7#include <asm/processor.h> 8#include <asm/macro.h> 9 10.macro or32, addr, data 11 mov.l \addr, r1 12 mov.l \data, r0 13 mov.l @r1, r2 14 or r2, r0 15 mov.l r0, @r1 16.endm 17 18.macro wait_DBCMD 19 mov.l DBWAIT_A, r0 20 mov.l @r0, r1 21.endm 22 23 .global lowlevel_init 24 .section .spiboot1.text 25 .align 2 26 27lowlevel_init: 28 mov #0, r14 29 mova 2f, r0 30 mov.l PC_MASK, r1 31 tst r0, r1 32 bf 2f 33 34 bra exit_pmb 35 nop 36 37 .align 2 38 39/* If CPU runs on SDRAM (PC=0x5???????) or not. */ 40PC_MASK: .long 0x20000000 41 422: 43 mov #1, r14 44 45 mov.l EXPEVT_A, r0 46 mov.l @r0, r0 47 mov.l EXPEVT_POWER_ON_RESET, r1 48 cmp/eq r0, r1 49 bt 1f 50 51 /* 52 * If EXPEVT value is manual reset or tlb multipul-hit, 53 * initialization of DBSC3 is not necessary. 54 */ 55 bra exit_ddr 56 nop 57 581: 59 /*------- Reset -------*/ 60 write32 MRSTCR0_A, MRSTCR0_D 61 write32 MRSTCR1_A, MRSTCR1_D 62 63 /* For Core Reset */ 64 mov.l DBACEN_A, r0 65 mov.l @r0, r0 66 cmp/eq #0, r0 67 bt 3f 68 69 /* 70 * If DBACEN == 1(DBSC was already enabled), we have to avoid the 71 * initialization of DDR3-SDRAM. 72 */ 73 bra exit_ddr 74 nop 75 763: 77 /*------- DBSC3 -------*/ 78 /* oscillation stabilization time */ 79 wait_timer WAIT_OSC_TIME 80 81 /* step 3 */ 82 write32 DBKIND_A, DBKIND_D 83 84 /* step 4 */ 85 write32 DBCONF_A, DBCONF_D 86 write32 DBTR0_A, DBTR0_D 87 write32 DBTR1_A, DBTR1_D 88 write32 DBTR2_A, DBTR2_D 89 write32 DBTR3_A, DBTR3_D 90 write32 DBTR4_A, DBTR4_D 91 write32 DBTR5_A, DBTR5_D 92 write32 DBTR6_A, DBTR6_D 93 write32 DBTR7_A, DBTR7_D 94 write32 DBTR8_A, DBTR8_D 95 write32 DBTR9_A, DBTR9_D 96 write32 DBTR10_A, DBTR10_D 97 write32 DBTR11_A, DBTR11_D 98 write32 DBTR12_A, DBTR12_D 99 write32 DBTR13_A, DBTR13_D 100 write32 DBTR14_A, DBTR14_D 101 write32 DBTR15_A, DBTR15_D 102 write32 DBTR16_A, DBTR16_D 103 write32 DBTR17_A, DBTR17_D 104 write32 DBTR18_A, DBTR18_D 105 write32 DBTR19_A, DBTR19_D 106 write32 DBRNK0_A, DBRNK0_D 107 write32 DBADJ0_A, DBADJ0_D 108 write32 DBADJ2_A, DBADJ2_D 109 110 /* step 5 */ 111 write32 DBCMD_A, DBCMD_RSTL_VAL 112 wait_timer WAIT_30US 113 114 /* step 6 */ 115 write32 DBCMD_A, DBCMD_PDEN_VAL 116 117 /* step 7 */ 118 write32 DBPDCNT3_A, DBPDCNT3_D 119 120 /* step 8 */ 121 write32 DBPDCNT1_A, DBPDCNT1_D 122 write32 DBPDCNT2_A, DBPDCNT2_D 123 write32 DBPDLCK_A, DBPDLCK_D 124 write32 DBPDRGA_A, DBPDRGA_D 125 write32 DBPDRGD_A, DBPDRGD_D 126 127 /* step 9 */ 128 wait_timer WAIT_30US 129 130 /* step 10 */ 131 write32 DBPDCNT0_A, DBPDCNT0_D 132 133 /* step 11 */ 134 wait_timer WAIT_30US 135 wait_timer WAIT_30US 136 137 /* step 12 */ 138 write32 DBCMD_A, DBCMD_WAIT_VAL 139 wait_DBCMD 140 141 /* step 13 */ 142 write32 DBCMD_A, DBCMD_RSTH_VAL 143 wait_DBCMD 144 145 /* step 14 */ 146 write32 DBCMD_A, DBCMD_WAIT_VAL 147 write32 DBCMD_A, DBCMD_WAIT_VAL 148 write32 DBCMD_A, DBCMD_WAIT_VAL 149 write32 DBCMD_A, DBCMD_WAIT_VAL 150 151 /* step 15 */ 152 write32 DBCMD_A, DBCMD_PDXT_VAL 153 154 /* step 16 */ 155 write32 DBCMD_A, DBCMD_MRS2_VAL 156 157 /* step 17 */ 158 write32 DBCMD_A, DBCMD_MRS3_VAL 159 160 /* step 18 */ 161 write32 DBCMD_A, DBCMD_MRS1_VAL 162 163 /* step 19 */ 164 write32 DBCMD_A, DBCMD_MRS0_VAL 165 write32 DBPDNCNF_A, DBPDNCNF_D 166 167 /* step 20 */ 168 write32 DBCMD_A, DBCMD_ZQCL_VAL 169 170 write32 DBCMD_A, DBCMD_REF_VAL 171 write32 DBCMD_A, DBCMD_REF_VAL 172 wait_DBCMD 173 174 /* step 21 */ 175 write32 DBCALTR_A, DBCALTR_D 176 177 /* step 22 */ 178 write32 DBRFCNF0_A, DBRFCNF0_D 179 write32 DBRFCNF1_A, DBRFCNF1_D 180 write32 DBRFCNF2_A, DBRFCNF2_D 181 182 /* step 23 */ 183 write32 DBCALCNF_A, DBCALCNF_D 184 185 /* step 24 */ 186 write32 DBRFEN_A, DBRFEN_D 187 write32 DBCMD_A, DBCMD_SRXT_VAL 188 189 /* step 25 */ 190 write32 DBACEN_A, DBACEN_D 191 192 /* step 26 */ 193 wait_DBCMD 194 195 bra exit_ddr 196 nop 197 198 .align 2 199 200EXPEVT_A: .long 0xff000024 201EXPEVT_POWER_ON_RESET: .long 0x00000000 202 203/*------- Reset -------*/ 204MRSTCR0_A: .long 0xffd50030 205MRSTCR0_D: .long 0xfe1ffe7f 206MRSTCR1_A: .long 0xffd50034 207MRSTCR1_D: .long 0xfff3ffff 208 209/*------- DBSC3 -------*/ 210DBCMD_A: .long 0xfe800018 211DBKIND_A: .long 0xfe800020 212DBCONF_A: .long 0xfe800024 213DBTR0_A: .long 0xfe800040 214DBTR1_A: .long 0xfe800044 215DBTR2_A: .long 0xfe800048 216DBTR3_A: .long 0xfe800050 217DBTR4_A: .long 0xfe800054 218DBTR5_A: .long 0xfe800058 219DBTR6_A: .long 0xfe80005c 220DBTR7_A: .long 0xfe800060 221DBTR8_A: .long 0xfe800064 222DBTR9_A: .long 0xfe800068 223DBTR10_A: .long 0xfe80006c 224DBTR11_A: .long 0xfe800070 225DBTR12_A: .long 0xfe800074 226DBTR13_A: .long 0xfe800078 227DBTR14_A: .long 0xfe80007c 228DBTR15_A: .long 0xfe800080 229DBTR16_A: .long 0xfe800084 230DBTR17_A: .long 0xfe800088 231DBTR18_A: .long 0xfe80008c 232DBTR19_A: .long 0xfe800090 233DBRNK0_A: .long 0xfe800100 234DBPDCNT0_A: .long 0xfe800200 235DBPDCNT1_A: .long 0xfe800204 236DBPDCNT2_A: .long 0xfe800208 237DBPDCNT3_A: .long 0xfe80020c 238DBPDLCK_A: .long 0xfe800280 239DBPDRGA_A: .long 0xfe800290 240DBPDRGD_A: .long 0xfe8002a0 241DBADJ0_A: .long 0xfe8000c0 242DBADJ2_A: .long 0xfe8000c8 243DBRFCNF0_A: .long 0xfe8000e0 244DBRFCNF1_A: .long 0xfe8000e4 245DBRFCNF2_A: .long 0xfe8000e8 246DBCALCNF_A: .long 0xfe8000f4 247DBRFEN_A: .long 0xfe800014 248DBACEN_A: .long 0xfe800010 249DBWAIT_A: .long 0xfe80001c 250DBCALTR_A: .long 0xfe8000f8 251DBPDNCNF_A: .long 0xfe800180 252 253WAIT_OSC_TIME: .long 6000 254WAIT_30US: .long 13333 255 256DBCMD_RSTL_VAL: .long 0x20000000 257DBCMD_PDEN_VAL: .long 0x1000d73c 258DBCMD_WAIT_VAL: .long 0x0000d73c 259DBCMD_RSTH_VAL: .long 0x2100d73c 260DBCMD_PDXT_VAL: .long 0x110000c8 261DBCMD_MRS0_VAL: .long 0x28000930 262DBCMD_MRS1_VAL: .long 0x29000004 263DBCMD_MRS2_VAL: .long 0x2a000008 264DBCMD_MRS3_VAL: .long 0x2b000000 265DBCMD_ZQCL_VAL: .long 0x03000200 266DBCMD_REF_VAL: .long 0x0c000000 267DBCMD_SRXT_VAL: .long 0x19000000 268DBKIND_D: .long 0x00000007 269DBCONF_D: .long 0x0f030a01 270DBTR0_D: .long 0x00000007 271DBTR1_D: .long 0x00000006 272DBTR2_D: .long 0x00000000 273DBTR3_D: .long 0x00000007 274DBTR4_D: .long 0x00070007 275DBTR5_D: .long 0x0000001b 276DBTR6_D: .long 0x00000014 277DBTR7_D: .long 0x00000004 278DBTR8_D: .long 0x00000014 279DBTR9_D: .long 0x00000004 280DBTR10_D: .long 0x00000008 281DBTR11_D: .long 0x00000007 282DBTR12_D: .long 0x0000000e 283DBTR13_D: .long 0x000000a0 284DBTR14_D: .long 0x00060006 285DBTR15_D: .long 0x00000003 286DBTR16_D: .long 0x00160002 287DBTR17_D: .long 0x000c0000 288DBTR18_D: .long 0x00000200 289DBTR19_D: .long 0x00000040 290DBRNK0_D: .long 0x00000001 291DBPDCNT0_D: .long 0x00000001 292DBPDCNT1_D: .long 0x00000001 293DBPDCNT2_D: .long 0x00000000 294DBPDCNT3_D: .long 0x00004010 295DBPDLCK_D: .long 0x0000a55a 296DBPDRGA_D: .long 0x00000028 297DBPDRGD_D: .long 0x00017100 298 299DBADJ0_D: .long 0x00010000 300DBADJ2_D: .long 0x18061806 301DBRFCNF0_D: .long 0x000001ff 302DBRFCNF1_D: .long 0x00081040 303DBRFCNF2_D: .long 0x00000000 304DBCALCNF_D: .long 0x0000ffff 305DBRFEN_D: .long 0x00000001 306DBACEN_D: .long 0x00000001 307DBCALTR_D: .long 0x08200820 308DBPDNCNF_D: .long 0x00000001 309 310 .align 2 311exit_ddr: 312#if defined(CONFIG_SH_32BIT) 313 /*------- set PMB -------*/ 314 write32 PASCR_A, PASCR_29BIT_D 315 write32 MMUCR_A, MMUCR_D 316 317 /***************************************************************** 318 * ent virt phys v sz c wt 319 * 0 0xa0000000 0x00000000 1 128M 0 1 320 * 1 0xa8000000 0x48000000 1 128M 0 1 321 * 5 0x88000000 0x48000000 1 128M 1 1 322 */ 323 write32 PMB_ADDR_SPIBOOT_A, PMB_ADDR_SPIBOOT_D 324 write32 PMB_DATA_SPIBOOT_A, PMB_DATA_SPIBOOT_D 325 write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D 326 write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D 327 write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D 328 write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D 329 330 write32 PMB_ADDR_ENTRY2, PMB_ADDR_NOT_USE_D 331 write32 PMB_ADDR_ENTRY3, PMB_ADDR_NOT_USE_D 332 write32 PMB_ADDR_ENTRY4, PMB_ADDR_NOT_USE_D 333 write32 PMB_ADDR_ENTRY6, PMB_ADDR_NOT_USE_D 334 write32 PMB_ADDR_ENTRY7, PMB_ADDR_NOT_USE_D 335 write32 PMB_ADDR_ENTRY8, PMB_ADDR_NOT_USE_D 336 write32 PMB_ADDR_ENTRY9, PMB_ADDR_NOT_USE_D 337 write32 PMB_ADDR_ENTRY10, PMB_ADDR_NOT_USE_D 338 write32 PMB_ADDR_ENTRY11, PMB_ADDR_NOT_USE_D 339 write32 PMB_ADDR_ENTRY12, PMB_ADDR_NOT_USE_D 340 write32 PMB_ADDR_ENTRY13, PMB_ADDR_NOT_USE_D 341 write32 PMB_ADDR_ENTRY14, PMB_ADDR_NOT_USE_D 342 write32 PMB_ADDR_ENTRY15, PMB_ADDR_NOT_USE_D 343 344 write32 PASCR_A, PASCR_INIT 345 mov.l DUMMY_ADDR, r0 346 icbi @r0 347#endif /* if defined(CONFIG_SH_32BIT) */ 348 349exit_pmb: 350 /* CPU is running on ILRAM? */ 351 mov r14, r0 352 tst #1, r0 353 bt 1f 354 355 mov.l _stack_ilram, r15 356 mov.l _spiboot_main, r0 357100: bsrf r0 358 nop 359 360 .align 2 361_spiboot_main: .long (spiboot_main - (100b + 4)) 362_stack_ilram: .long 0xe5204000 363 3641: 365 write32 CCR_A, CCR_D 366 367 rts 368 nop 369 370 .align 2 371 372#if defined(CONFIG_SH_32BIT) 373/*------- set PMB -------*/ 374PMB_ADDR_SPIBOOT_A: .long PMB_ADDR_BASE(0) 375PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(1) 376PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(5) 377PMB_ADDR_ENTRY2: .long PMB_ADDR_BASE(2) 378PMB_ADDR_ENTRY3: .long PMB_ADDR_BASE(3) 379PMB_ADDR_ENTRY4: .long PMB_ADDR_BASE(4) 380PMB_ADDR_ENTRY6: .long PMB_ADDR_BASE(6) 381PMB_ADDR_ENTRY7: .long PMB_ADDR_BASE(7) 382PMB_ADDR_ENTRY8: .long PMB_ADDR_BASE(8) 383PMB_ADDR_ENTRY9: .long PMB_ADDR_BASE(9) 384PMB_ADDR_ENTRY10: .long PMB_ADDR_BASE(10) 385PMB_ADDR_ENTRY11: .long PMB_ADDR_BASE(11) 386PMB_ADDR_ENTRY12: .long PMB_ADDR_BASE(12) 387PMB_ADDR_ENTRY13: .long PMB_ADDR_BASE(13) 388PMB_ADDR_ENTRY14: .long PMB_ADDR_BASE(14) 389PMB_ADDR_ENTRY15: .long PMB_ADDR_BASE(15) 390 391PMB_ADDR_SPIBOOT_D: .long mk_pmb_addr_val(0xa0) 392PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88) 393PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8) 394PMB_ADDR_NOT_USE_D: .long 0x00000000 395 396PMB_DATA_SPIBOOT_A: .long PMB_DATA_BASE(0) 397PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(1) 398PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(5) 399 400/* ppn ub v s1 s0 c wt */ 401PMB_DATA_SPIBOOT_D: .long mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1) 402PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1) 403PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1) 404 405PASCR_A: .long 0xff000070 406DUMMY_ADDR: .long 0xa0000000 407PASCR_29BIT_D: .long 0x00000000 408PASCR_INIT: .long 0x80000080 409MMUCR_A: .long 0xff000010 410MMUCR_D: .long 0x00000004 /* clear ITLB */ 411#endif /* CONFIG_SH_32BIT */ 412 413CCR_A: .long CCR 414CCR_D: .long CCR_CACHE_INIT 415