1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
4 */
5
6 #include <common.h>
7 #include <dwmmc.h>
8 #include <malloc.h>
9 #include <asm/arcregs.h>
10 #include "axs10x.h"
11
12 DECLARE_GLOBAL_DATA_PTR;
13
board_mmc_init(bd_t * bis)14 int board_mmc_init(bd_t *bis)
15 {
16 struct dwmci_host *host = NULL;
17
18 host = malloc(sizeof(struct dwmci_host));
19 if (!host) {
20 printf("dwmci_host malloc fail!\n");
21 return 1;
22 }
23
24 memset(host, 0, sizeof(struct dwmci_host));
25 host->name = "Synopsys Mobile storage";
26 host->ioaddr = (void *)ARC_DWMMC_BASE;
27 host->buswidth = 4;
28 host->dev_index = 0;
29 host->bus_hz = 50000000;
30
31 add_dwmci(host, host->bus_hz / 2, 400000);
32
33 return 0;
34 }
35
36 #define AXS_MB_CREG 0xE0011000
37
board_early_init_f(void)38 int board_early_init_f(void)
39 {
40 if (readl((void __iomem *)AXS_MB_CREG + 0x234) & (1 << 28))
41 gd->board_type = AXS_MB_V3;
42 else
43 gd->board_type = AXS_MB_V2;
44
45 return 0;
46 }
47
48 #ifdef CONFIG_ISA_ARCV2
49
board_jump_and_run(ulong entry,int zero,int arch,uint params)50 void board_jump_and_run(ulong entry, int zero, int arch, uint params)
51 {
52 void (*kernel_entry)(int zero, int arch, uint params);
53
54 kernel_entry = (void (*)(int, int, uint))entry;
55
56 smp_set_core_boot_addr(entry, -1);
57 smp_kick_all_cpus();
58 kernel_entry(zero, arch, params);
59 }
60
61 #define RESET_VECTOR_ADDR 0x0
62
smp_set_core_boot_addr(unsigned long addr,int corenr)63 void smp_set_core_boot_addr(unsigned long addr, int corenr)
64 {
65 /* All cores have reset vector pointing to 0 */
66 writel(addr, (void __iomem *)RESET_VECTOR_ADDR);
67
68 /* Make sure other cores see written value in memory */
69 flush_dcache_all();
70 }
71
smp_kick_all_cpus(void)72 void smp_kick_all_cpus(void)
73 {
74 /* CPU start CREG */
75 #define AXC003_CREG_CPU_START 0xF0001400
76 /* Bits positions in CPU start CREG */
77 #define BITS_START 0
78 #define BITS_START_MODE 4
79 #define BITS_CORE_SEL 9
80
81 /*
82 * In axs103 v1.1 START bits semantics has changed quite a bit.
83 * We used to have a generic START bit for all cores selected by CORE_SEL mask.
84 * But now we don't touch CORE_SEL at all because we have a dedicated START bit
85 * for each core:
86 * bit 0: Core 0 (master)
87 * bit 1: Core 1 (slave)
88 */
89 #define BITS_START_CORE1 1
90
91 #define ARCVER_HS38_3_0 0x53
92
93 int core_family = read_aux_reg(ARC_AUX_IDENTITY) & 0xff;
94 int cmd = readl((void __iomem *)AXC003_CREG_CPU_START);
95
96 if (core_family < ARCVER_HS38_3_0) {
97 cmd |= (1 << BITS_CORE_SEL) | (1 << BITS_START);
98 cmd &= ~(1 << BITS_START_MODE);
99 } else {
100 cmd |= (1 << BITS_START_CORE1);
101 }
102 writel(cmd, (void __iomem *)AXC003_CREG_CPU_START);
103 }
104 #endif
105