1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * (C) Copyright 2011 4 * Matthias Weisser <weisserm@arcor.de> 5 * 6 * (C) Copyright 2009 DENX Software Engineering 7 * Author: John Rigby <jrigby@gmail.com> 8 * 9 * Based on U-Boot and RedBoot sources for several different i.mx 10 * platforms. 11 */ 12 13#include <asm/macro.h> 14#include <asm/arch/macro.h> 15#include <asm/arch/imx-regs.h> 16#include <generated/asm-offsets.h> 17 18/* 19 * clocks 20 */ 21.macro init_clocks 22 23 /* disable clock output */ 24 write32 IMX_CCM_BASE + CCM_MCR, 0x00000000 25 write32 IMX_CCM_BASE + CCM_CCTL, 0x50030000 26 27 /* 28 * enable all implemented clocks in all three 29 * clock control registers 30 */ 31 write32 IMX_CCM_BASE + CCM_CGCR0, 0x1fffffff 32 write32 IMX_CCM_BASE + CCM_CGCR1, 0xffffffff 33 write32 IMX_CCM_BASE + CCM_CGCR2, 0xfffff 34 35 /* Devide NAND clock by 32 */ 36 write32 IMX_CCM_BASE + CCM_PCDR2, 0x0101011F 37.endm 38 39/* 40 * sdram controller init 41 */ 42.macro init_lpddr 43 ldr r0, =IMX_ESDRAMC_BASE 44 ldr r2, =IMX_SDRAM_BANK0_BASE 45 46 /* 47 * reset SDRAM controller 48 * then wait for initialization to complete 49 */ 50 ldr r1, =(1 << 1) | (1 << 2) 51 str r1, [r0, #ESDRAMC_ESDMISC] 521: ldr r3, [r0, #ESDRAMC_ESDMISC] 53 tst r3, #(1 << 31) 54 beq 1b 55 ldr r1, =(1 << 2) 56 str r1, [r0, #ESDRAMC_ESDMISC] 57 58 ldr r1, =0x002a7420 59 str r1, [r0, #ESDRAMC_ESDCFG0] 60 61 /* control | precharge */ 62 ldr r1, =0x92216008 63 str r1, [r0, #ESDRAMC_ESDCTL0] 64 /* dram command encoded in address */ 65 str r1, [r2, #0x400] 66 67 /* auto refresh */ 68 ldr r1, =0xa2216008 69 str r1, [r0, #ESDRAMC_ESDCTL0] 70 /* read dram twice to auto refresh */ 71 ldr r3, [r2] 72 ldr r3, [r2] 73 74 /* control | load mode */ 75 ldr r1, =0xb2216008 76 str r1, [r0, #ESDRAMC_ESDCTL0] 77 78 /* mode register of lpddram */ 79 strb r1, [r2, #0x33] 80 81 /* extended mode register of lpddrram */ 82 ldr r2, =0x81000000 83 strb r1, [r2] 84 85 /* control | normal */ 86 ldr r1, =0x82216008 87 str r1, [r0, #ESDRAMC_ESDCTL0] 88.endm 89 90.globl lowlevel_init 91lowlevel_init: 92 init_aips 93 init_max 94 init_clocks 95 init_lpddr 96 mov pc, lr 97