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1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2014 Soeren Moch <smoch@web.de>
4  */
5 
6 #include <asm/arch/clock.h>
7 #include <asm/arch/imx-regs.h>
8 #include <asm/arch/iomux.h>
9 #include <asm/arch/mx6-pins.h>
10 #include <linux/errno.h>
11 #include <asm/gpio.h>
12 #include <asm/mach-imx/mxc_i2c.h>
13 #include <asm/mach-imx/iomux-v3.h>
14 #include <asm/mach-imx/sata.h>
15 #include <asm/mach-imx/boot_mode.h>
16 #include <asm/mach-imx/video.h>
17 #include <mmc.h>
18 #include <fsl_esdhc.h>
19 #include <miiphy.h>
20 #include <netdev.h>
21 #include <asm/arch/mxc_hdmi.h>
22 #include <asm/arch/crm_regs.h>
23 #include <asm/io.h>
24 #include <asm/arch/sys_proto.h>
25 #include <i2c.h>
26 DECLARE_GLOBAL_DATA_PTR;
27 
28 #define WEAK_PULLUP	(PAD_CTL_PUS_47K_UP |			\
29 	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
30 	PAD_CTL_SRE_SLOW)
31 
32 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
33 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
34 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
35 
36 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
37 	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
38 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
39 
40 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
41 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
42 
43 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
44 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
45 	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
46 
47 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
48 
49 #ifdef CONFIG_SYS_I2C
50 /* I2C1, SGTL5000 */
51 static struct i2c_pads_info i2c_pad_info0 = {
52 	.scl = {
53 		.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
54 		.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
55 		.gp = IMX_GPIO_NR(5, 27)
56 	},
57 	.sda = {
58 		.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
59 		.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
60 		.gp = IMX_GPIO_NR(5, 26)
61 	}
62 };
63 
64 /* I2C2 HDMI */
65 static struct i2c_pads_info i2c_pad_info1 = {
66 	.scl = {
67 		.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
68 		.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
69 		.gp = IMX_GPIO_NR(4, 12)
70 	},
71 	.sda = {
72 		.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
73 		.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
74 		.gp = IMX_GPIO_NR(4, 13)
75 	}
76 };
77 
78 /* I2C3, CON11, DS1307, PCIe_SMB */
79 static struct i2c_pads_info i2c_pad_info2 = {
80 	.scl = {
81 		.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
82 		.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
83 		.gp = IMX_GPIO_NR(1, 3)
84 	},
85 	.sda = {
86 		.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
87 		.gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
88 		.gp = IMX_GPIO_NR(1, 6)
89 	}
90 };
91 #endif /* CONFIG_SYS_I2C */
92 
93 static iomux_v3_cfg_t const uart1_pads[] = {
94 	MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
95 	MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
96 };
97 
98 static iomux_v3_cfg_t const uart2_pads[] = {
99 	MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
100 	MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
101 };
102 
103 static iomux_v3_cfg_t const enet_pads[] = {
104 	MX6_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
105 	MX6_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
106 	MX6_PAD_RGMII_TXC__RGMII_TXC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
107 	MX6_PAD_RGMII_TD0__RGMII_TD0		| MUX_PAD_CTRL(ENET_PAD_CTRL),
108 	MX6_PAD_RGMII_TD1__RGMII_TD1		| MUX_PAD_CTRL(ENET_PAD_CTRL),
109 	MX6_PAD_RGMII_TD2__RGMII_TD2		| MUX_PAD_CTRL(ENET_PAD_CTRL),
110 	MX6_PAD_RGMII_TD3__RGMII_TD3		| MUX_PAD_CTRL(ENET_PAD_CTRL),
111 	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
112 	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
113 	MX6_PAD_RGMII_RXC__RGMII_RXC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
114 	MX6_PAD_RGMII_RD0__RGMII_RD0		| MUX_PAD_CTRL(ENET_PAD_CTRL),
115 	MX6_PAD_RGMII_RD1__RGMII_RD1		| MUX_PAD_CTRL(ENET_PAD_CTRL),
116 	MX6_PAD_RGMII_RD2__RGMII_RD2		| MUX_PAD_CTRL(ENET_PAD_CTRL),
117 	MX6_PAD_RGMII_RD3__RGMII_RD3		| MUX_PAD_CTRL(ENET_PAD_CTRL),
118 	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
119 	/* AR8035 PHY Reset */
120 	MX6_PAD_ENET_CRS_DV__GPIO1_IO25		| MUX_PAD_CTRL(NO_PAD_CTRL),
121 };
122 
123 static iomux_v3_cfg_t const pcie_pads[] = {
124 	/* W_DISABLE# */
125 	MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP),
126 	/* PERST# */
127 	MX6_PAD_GPIO_17__GPIO7_IO12  | MUX_PAD_CTRL(NO_PAD_CTRL),
128 };
129 
dram_init(void)130 int dram_init(void)
131 {
132 	gd->ram_size = 2048ul * 1024 * 1024;
133 	return 0;
134 }
135 
setup_iomux_enet(void)136 static void setup_iomux_enet(void)
137 {
138 	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
139 
140 	/* Reset AR8035 PHY */
141 	gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
142 	udelay(500);
143 	gpio_set_value(IMX_GPIO_NR(1, 25), 1);
144 }
145 
setup_pcie(void)146 static void setup_pcie(void)
147 {
148 	imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
149 }
150 
setup_iomux_uart(void)151 static void setup_iomux_uart(void)
152 {
153 	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
154 	imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
155 }
156 
157 #ifdef CONFIG_FSL_ESDHC
158 static iomux_v3_cfg_t const usdhc2_pads[] = {
159 	MX6_PAD_SD2_CLK__SD2_CLK     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
160 	MX6_PAD_SD2_CMD__SD2_CMD     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
161 	MX6_PAD_SD2_DAT0__SD2_DATA0  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
162 	MX6_PAD_SD2_DAT1__SD2_DATA1  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
163 	MX6_PAD_SD2_DAT2__SD2_DATA2  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
164 	MX6_PAD_SD2_DAT3__SD2_DATA3  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
165 	MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
166 };
167 
168 static iomux_v3_cfg_t const usdhc3_pads[] = {
169 	MX6_PAD_SD3_CLK__SD3_CLK     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
170 	MX6_PAD_SD3_CMD__SD3_CMD     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
171 	MX6_PAD_SD3_DAT0__SD3_DATA0  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
172 	MX6_PAD_SD3_DAT1__SD3_DATA1  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
173 	MX6_PAD_SD3_DAT2__SD3_DATA2  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
174 	MX6_PAD_SD3_DAT3__SD3_DATA3  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
175 	MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
176 };
177 
178 static iomux_v3_cfg_t const usdhc4_pads[] = {
179 	MX6_PAD_SD4_CLK__SD4_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
180 	MX6_PAD_SD4_CMD__SD4_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
181 	MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
182 	MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
183 	MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
184 	MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
185 	MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
186 	MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
187 	MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
188 	MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
189 };
190 
191 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
192 	{USDHC2_BASE_ADDR},
193 	{USDHC3_BASE_ADDR},
194 	{USDHC4_BASE_ADDR},
195 };
196 
197 #define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 2)
198 #define USDHC3_CD_GPIO	IMX_GPIO_NR(2, 0)
199 
board_mmc_getcd(struct mmc * mmc)200 int board_mmc_getcd(struct mmc *mmc)
201 {
202 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
203 	int ret = 0;
204 
205 	switch (cfg->esdhc_base) {
206 	case USDHC2_BASE_ADDR:
207 		ret = !gpio_get_value(USDHC2_CD_GPIO);
208 		break;
209 	case USDHC3_BASE_ADDR:
210 		ret = !gpio_get_value(USDHC3_CD_GPIO);
211 		break;
212 	case USDHC4_BASE_ADDR:
213 		ret = 1; /* eMMC/uSDHC4 is always present */
214 		break;
215 	}
216 	return ret;
217 }
218 
board_mmc_init(bd_t * bis)219 int board_mmc_init(bd_t *bis)
220 {
221 	/*
222 	 * (U-Boot device node)    (Physical Port)
223 	 * mmc0                    SD2
224 	 * mmc1                    SD3
225 	 * mmc2                    eMMC
226 	 */
227 	int i, ret;
228 	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
229 		switch (i) {
230 		case 0:
231 			imx_iomux_v3_setup_multiple_pads(
232 				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
233 			gpio_direction_input(USDHC2_CD_GPIO);
234 			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
235 			break;
236 		case 1:
237 			imx_iomux_v3_setup_multiple_pads(
238 				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
239 			gpio_direction_input(USDHC3_CD_GPIO);
240 			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
241 			break;
242 		case 2:
243 			imx_iomux_v3_setup_multiple_pads(
244 				usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
245 			usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
246 			break;
247 		default:
248 			printf("Warning: you configured more USDHC controllers"
249 			       "(%d) then supported by the board (%d)\n",
250 			       i + 1, CONFIG_SYS_FSL_USDHC_NUM);
251 			return -EINVAL;
252 		}
253 		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
254 		if (ret)
255 			return ret;
256 	}
257 	return 0;
258 }
259 
260 /* set environment device to boot device when booting from SD */
board_mmc_get_env_dev(int devno)261 int board_mmc_get_env_dev(int devno)
262 {
263 	return devno - 1;
264 }
265 
board_mmc_get_env_part(int devno)266 int board_mmc_get_env_part(int devno)
267 {
268 	return (devno == 3) ? 1 : 0; /* part 0 for SD2 / SD3, part 1 for eMMC */
269 }
270 #endif /* CONFIG_FSL_ESDHC */
271 
272 #ifdef CONFIG_VIDEO_IPUV3
do_enable_hdmi(struct display_info_t const * dev)273 static void do_enable_hdmi(struct display_info_t const *dev)
274 {
275 	imx_enable_hdmi_phy();
276 }
277 
278 struct display_info_t const displays[] = {{
279 	.bus	= -1,
280 	.addr	= 0,
281 	.pixfmt	= IPU_PIX_FMT_RGB24,
282 	.detect	= detect_hdmi,
283 	.enable	= do_enable_hdmi,
284 	.mode	= {
285 		.name           = "HDMI",
286 		/* 1024x768@60Hz (VESA)*/
287 		.refresh        = 60,
288 		.xres           = 1024,
289 		.yres           = 768,
290 		.pixclock       = 15384,
291 		.left_margin    = 160,
292 		.right_margin   = 24,
293 		.upper_margin   = 29,
294 		.lower_margin   = 3,
295 		.hsync_len      = 136,
296 		.vsync_len      = 6,
297 		.sync           = FB_SYNC_EXT,
298 		.vmode          = FB_VMODE_NONINTERLACED
299 } } };
300 size_t display_count = ARRAY_SIZE(displays);
301 
setup_display(void)302 static void setup_display(void)
303 {
304 	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
305 	int reg;
306 	s32 timeout = 100000;
307 
308 	enable_ipu_clock();
309 	imx_setup_hdmi();
310 
311 	/* set video pll to 455MHz (24MHz * (37+11/12) / 2) */
312 	reg = readl(&ccm->analog_pll_video);
313 	reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
314 	writel(reg, &ccm->analog_pll_video);
315 
316 	reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
317 	reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37);
318 	reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
319 	reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1);
320 	writel(reg, &ccm->analog_pll_video);
321 
322 	writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
323 	writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
324 
325 	reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
326 	writel(reg, &ccm->analog_pll_video);
327 
328 	while (timeout--)
329 		if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
330 			break;
331 	if (timeout < 0)
332 		printf("Warning: video pll lock timeout!\n");
333 
334 	reg = readl(&ccm->analog_pll_video);
335 	reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
336 	reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
337 	writel(reg, &ccm->analog_pll_video);
338 
339 	/* gate ipu1_di0_clk */
340 	reg = readl(&ccm->CCGR3);
341 	reg &= ~MXC_CCM_CCGR3_LDB_DI0_MASK;
342 	writel(reg, &ccm->CCGR3);
343 
344 	/* select video_pll clock / 7  for ipu1_di0_clk -> 65MHz pixclock */
345 	reg = readl(&ccm->chsccdr);
346 	reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
347 		 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK |
348 		 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
349 	reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) |
350 	       (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
351 	       (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
352 	writel(reg, &ccm->chsccdr);
353 
354 	/* enable ipu1_di0_clk */
355 	reg = readl(&ccm->CCGR3);
356 	reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
357 	writel(reg, &ccm->CCGR3);
358 }
359 #endif /* CONFIG_VIDEO_IPUV3 */
360 
ar8035_phy_fixup(struct phy_device * phydev)361 static int ar8035_phy_fixup(struct phy_device *phydev)
362 {
363 	unsigned short val;
364 
365 	/* To enable AR8035 ouput a 125MHz clk from CLK_25M */
366 	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
367 	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
368 	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
369 
370 	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
371 	val &= 0xffe3;
372 	val |= 0x18;
373 	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
374 
375 	/* introduce tx clock delay */
376 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
377 	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
378 	val |= 0x0100;
379 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
380 
381 	return 0;
382 }
383 
board_phy_config(struct phy_device * phydev)384 int board_phy_config(struct phy_device *phydev)
385 {
386 	ar8035_phy_fixup(phydev);
387 
388 	if (phydev->drv->config)
389 		phydev->drv->config(phydev);
390 
391 	return 0;
392 }
393 
board_eth_init(bd_t * bis)394 int board_eth_init(bd_t *bis)
395 {
396 	setup_iomux_enet();
397 	setup_pcie();
398 	return cpu_eth_init(bis);
399 }
400 
board_early_init_f(void)401 int board_early_init_f(void)
402 {
403 	setup_iomux_uart();
404 	return 0;
405 }
406 
407 #ifdef CONFIG_CMD_BMODE
408 static const struct boot_mode board_boot_modes[] = {
409 	/* 4 bit bus width */
410 	{"sd2",	 MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
411 	{"sd3",	 MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
412 	/* 8 bit bus width */
413 	{"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
414 	{NULL,	 0},
415 };
416 #endif
417 
418 #ifdef CONFIG_USB_EHCI_MX6
419 static iomux_v3_cfg_t const usb_otg_pads[] = {
420 	MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
421 };
422 #endif
423 
board_init(void)424 int board_init(void)
425 {
426 	/* address of boot parameters */
427 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
428 
429 #ifdef CONFIG_VIDEO_IPUV3
430 	setup_display();
431 #endif
432 #ifdef CONFIG_SYS_I2C
433 	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
434 	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
435 	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
436 #endif
437 #ifdef CONFIG_DWC_AHSATA
438 	setup_sata();
439 #endif
440 #ifdef CONFIG_CMD_BMODE
441 	add_board_boot_modes(board_boot_modes);
442 #endif
443 #ifdef CONFIG_USB_EHCI_MX6
444 	imx_iomux_v3_setup_multiple_pads(
445 		usb_otg_pads, ARRAY_SIZE(usb_otg_pads));
446 #endif
447 	return 0;
448 }
449 
checkboard(void)450 int checkboard(void)
451 {
452 	puts("Board: TBS2910 Matrix ARM mini PC\n");
453 	return 0;
454 }
455