1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (C) 2013 Boundary Devices 4 * Copyright (C) 2014-2016, Toradex AG 5 * 6 * Device Configuration Data (DCD) 7 * 8 * Each entry must have the format: 9 * Addr-type Address Value 10 * 11 * where: 12 * Addr-type register length (1,2 or 4 bytes) 13 * Address absolute address of the register 14 * value value to be stored in the register 15 */ 16 17/* set the default clock gate to save power */ 18DATA 4, CCM_CCGR0, 0x00C03F3F 19DATA 4, CCM_CCGR1, 0x0030FC03 20DATA 4, CCM_CCGR2, 0x0FFFC000 21DATA 4, CCM_CCGR3, 0x3FF00000 22DATA 4, CCM_CCGR4, 0x00FFF300 23DATA 4, CCM_CCGR5, 0x0F0000C3 24DATA 4, CCM_CCGR6, 0x000003FF 25 26/* enable AXI cache for VDOA/VPU/IPU */ 27DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF 28/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ 29DATA 4, MX6_IOMUXC_GPR6, 0x007F007F 30DATA 4, MX6_IOMUXC_GPR7, 0x007F007F 31 32/* 33 * Setup CCM_CCOSR register as follows: 34 * 35 * cko1_en = 1 --> CKO1 enabled 36 * cko1_div = 111 --> divide by 8 37 * cko1_sel = 1011 --> ahb_clk_root 38 * 39 * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz 40 */ 41DATA 4, CCM_CCOSR, 0x000000fb 42