1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2013 Freescale Semiconductor, Inc.
4 * Copyright (C) 2014 O.S. Systems Software LTDA.
5 *
6 * Author: Fabio Estevam <fabio.estevam@freescale.com>
7 */
8
9 #include <asm/arch/clock.h>
10 #include <asm/arch/crm_regs.h>
11 #include <asm/arch/iomux.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/arch/mxc_hdmi.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/gpio.h>
17 #include <asm/mach-imx/iomux-v3.h>
18 #include <asm/mach-imx/mxc_i2c.h>
19 #include <asm/mach-imx/boot_mode.h>
20 #include <asm/mach-imx/video.h>
21 #include <asm/mach-imx/sata.h>
22 #include <asm/io.h>
23 #include <linux/sizes.h>
24 #include <common.h>
25 #include <fsl_esdhc.h>
26 #include <mmc.h>
27 #include <miiphy.h>
28 #include <netdev.h>
29 #include <phy.h>
30 #include <i2c.h>
31 #include <power/pmic.h>
32 #include <power/pfuze100_pmic.h>
33
34 DECLARE_GLOBAL_DATA_PTR;
35
36 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
37 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
38 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
39
40 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
41 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
42 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
43
44 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
45 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
46
47 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
48 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
49 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
50
51 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 2)
52 #define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9)
53 #define ETH_PHY_RESET IMX_GPIO_NR(3, 29)
54 #define ETH_PHY_AR8035_POWER IMX_GPIO_NR(7, 13)
55 #define REV_DETECTION IMX_GPIO_NR(2, 28)
56
57 static bool with_pmic;
58
dram_init(void)59 int dram_init(void)
60 {
61 gd->ram_size = imx_ddr_size();
62
63 return 0;
64 }
65
66 static iomux_v3_cfg_t const uart1_pads[] = {
67 IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
68 IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
69 };
70
71 static iomux_v3_cfg_t const usdhc1_pads[] = {
72 IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
73 IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
74 IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
75 IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
76 IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
77 IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
78 /* Carrier MicroSD Card Detect */
79 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
80 };
81
82 static iomux_v3_cfg_t const usdhc3_pads[] = {
83 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
84 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
85 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
86 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
87 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
88 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
89 /* SOM MicroSD Card Detect */
90 IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
91 };
92
93 static iomux_v3_cfg_t const enet_pads[] = {
94 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
95 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
96 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
97 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
98 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
99 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
100 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
101 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
102 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
103 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
104 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
105 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
106 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
107 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
108 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
109 /* AR8031 PHY Reset */
110 IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
111 };
112
113 static iomux_v3_cfg_t const enet_ar8035_power_pads[] = {
114 /* AR8035 POWER */
115 IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)),
116 };
117
118 static iomux_v3_cfg_t const rev_detection_pad[] = {
119 IOMUX_PADS(PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
120 };
121
setup_iomux_uart(void)122 static void setup_iomux_uart(void)
123 {
124 SETUP_IOMUX_PADS(uart1_pads);
125 }
126
setup_iomux_enet(void)127 static void setup_iomux_enet(void)
128 {
129 SETUP_IOMUX_PADS(enet_pads);
130
131 if (with_pmic) {
132 SETUP_IOMUX_PADS(enet_ar8035_power_pads);
133 /* enable AR8035 POWER */
134 gpio_direction_output(ETH_PHY_AR8035_POWER, 0);
135 }
136 /* wait until 3.3V of PHY and clock become stable */
137 mdelay(10);
138
139 /* Reset AR8031 PHY */
140 gpio_direction_output(ETH_PHY_RESET, 0);
141 mdelay(10);
142 gpio_set_value(ETH_PHY_RESET, 1);
143 udelay(100);
144 }
145
146 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
147 {USDHC3_BASE_ADDR},
148 {USDHC1_BASE_ADDR},
149 };
150
board_mmc_getcd(struct mmc * mmc)151 int board_mmc_getcd(struct mmc *mmc)
152 {
153 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
154 int ret = 0;
155
156 switch (cfg->esdhc_base) {
157 case USDHC1_BASE_ADDR:
158 ret = !gpio_get_value(USDHC1_CD_GPIO);
159 break;
160 case USDHC3_BASE_ADDR:
161 ret = !gpio_get_value(USDHC3_CD_GPIO);
162 break;
163 }
164
165 return ret;
166 }
167
board_mmc_init(bd_t * bis)168 int board_mmc_init(bd_t *bis)
169 {
170 int ret;
171 u32 index = 0;
172
173 /*
174 * Following map is done:
175 * (U-Boot device node) (Physical Port)
176 * mmc0 SOM MicroSD
177 * mmc1 Carrier board MicroSD
178 */
179 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
180 switch (index) {
181 case 0:
182 SETUP_IOMUX_PADS(usdhc3_pads);
183 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
184 usdhc_cfg[0].max_bus_width = 4;
185 gpio_direction_input(USDHC3_CD_GPIO);
186 break;
187 case 1:
188 SETUP_IOMUX_PADS(usdhc1_pads);
189 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
190 usdhc_cfg[1].max_bus_width = 4;
191 gpio_direction_input(USDHC1_CD_GPIO);
192 break;
193 default:
194 printf("Warning: you configured more USDHC controllers"
195 "(%d) then supported by the board (%d)\n",
196 index + 1, CONFIG_SYS_FSL_USDHC_NUM);
197 return -EINVAL;
198 }
199
200 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
201 if (ret)
202 return ret;
203 }
204
205 return 0;
206 }
207
ar8031_phy_fixup(struct phy_device * phydev)208 static int ar8031_phy_fixup(struct phy_device *phydev)
209 {
210 unsigned short val;
211 int mask;
212
213 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
214 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
215 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
216 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
217
218 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
219 if (with_pmic)
220 mask = 0xffe7; /* AR8035 */
221 else
222 mask = 0xffe3; /* AR8031 */
223
224 val &= mask;
225 val |= 0x18;
226 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
227
228 /* introduce tx clock delay */
229 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
230 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
231 val |= 0x0100;
232 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
233
234 return 0;
235 }
236
board_phy_config(struct phy_device * phydev)237 int board_phy_config(struct phy_device *phydev)
238 {
239 ar8031_phy_fixup(phydev);
240
241 if (phydev->drv->config)
242 phydev->drv->config(phydev);
243
244 return 0;
245 }
246
247 #if defined(CONFIG_VIDEO_IPUV3)
248 struct i2c_pads_info mx6q_i2c2_pad_info = {
249 .scl = {
250 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL
251 | MUX_PAD_CTRL(I2C_PAD_CTRL),
252 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12
253 | MUX_PAD_CTRL(I2C_PAD_CTRL),
254 .gp = IMX_GPIO_NR(4, 12)
255 },
256 .sda = {
257 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA
258 | MUX_PAD_CTRL(I2C_PAD_CTRL),
259 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13
260 | MUX_PAD_CTRL(I2C_PAD_CTRL),
261 .gp = IMX_GPIO_NR(4, 13)
262 }
263 };
264
265 struct i2c_pads_info mx6dl_i2c2_pad_info = {
266 .scl = {
267 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL
268 | MUX_PAD_CTRL(I2C_PAD_CTRL),
269 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12
270 | MUX_PAD_CTRL(I2C_PAD_CTRL),
271 .gp = IMX_GPIO_NR(4, 12)
272 },
273 .sda = {
274 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA
275 | MUX_PAD_CTRL(I2C_PAD_CTRL),
276 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13
277 | MUX_PAD_CTRL(I2C_PAD_CTRL),
278 .gp = IMX_GPIO_NR(4, 13)
279 }
280 };
281
282 struct i2c_pads_info mx6q_i2c3_pad_info = {
283 .scl = {
284 .i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL
285 | MUX_PAD_CTRL(I2C_PAD_CTRL),
286 .gpio_mode = MX6Q_PAD_GPIO_5__GPIO1_IO05
287 | MUX_PAD_CTRL(I2C_PAD_CTRL),
288 .gp = IMX_GPIO_NR(1, 5)
289 },
290 .sda = {
291 .i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA
292 | MUX_PAD_CTRL(I2C_PAD_CTRL),
293 .gpio_mode = MX6Q_PAD_GPIO_16__GPIO7_IO11
294 | MUX_PAD_CTRL(I2C_PAD_CTRL),
295 .gp = IMX_GPIO_NR(7, 11)
296 }
297 };
298
299 struct i2c_pads_info mx6dl_i2c3_pad_info = {
300 .scl = {
301 .i2c_mode = MX6DL_PAD_GPIO_5__I2C3_SCL
302 | MUX_PAD_CTRL(I2C_PAD_CTRL),
303 .gpio_mode = MX6DL_PAD_GPIO_5__GPIO1_IO05
304 | MUX_PAD_CTRL(I2C_PAD_CTRL),
305 .gp = IMX_GPIO_NR(1, 5)
306 },
307 .sda = {
308 .i2c_mode = MX6DL_PAD_GPIO_16__I2C3_SDA
309 | MUX_PAD_CTRL(I2C_PAD_CTRL),
310 .gpio_mode = MX6DL_PAD_GPIO_16__GPIO7_IO11
311 | MUX_PAD_CTRL(I2C_PAD_CTRL),
312 .gp = IMX_GPIO_NR(7, 11)
313 }
314 };
315
316 static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = {
317 IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
318 IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
319 IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */
320 IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */
321 IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */
322 IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
323 IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
324 IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
325 IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
326 IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
327 IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
328 IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
329 IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
330 IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
331 IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
332 IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
333 IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
334 IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
335 IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
336 IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
337 IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
338 IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
339 IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
340 IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */
341 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */
342 };
343
do_enable_hdmi(struct display_info_t const * dev)344 static void do_enable_hdmi(struct display_info_t const *dev)
345 {
346 imx_enable_hdmi_phy();
347 }
348
detect_i2c(struct display_info_t const * dev)349 static int detect_i2c(struct display_info_t const *dev)
350 {
351 return (0 == i2c_set_bus_num(dev->bus)) &&
352 (0 == i2c_probe(dev->addr));
353 }
354
enable_fwadapt_7wvga(struct display_info_t const * dev)355 static void enable_fwadapt_7wvga(struct display_info_t const *dev)
356 {
357 SETUP_IOMUX_PADS(fwadapt_7wvga_pads);
358
359 gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
360 gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
361 }
362
363 struct display_info_t const displays[] = {{
364 .bus = -1,
365 .addr = 0,
366 .pixfmt = IPU_PIX_FMT_RGB24,
367 .detect = detect_hdmi,
368 .enable = do_enable_hdmi,
369 .mode = {
370 .name = "HDMI",
371 .refresh = 60,
372 .xres = 1024,
373 .yres = 768,
374 .pixclock = 15385,
375 .left_margin = 220,
376 .right_margin = 40,
377 .upper_margin = 21,
378 .lower_margin = 7,
379 .hsync_len = 60,
380 .vsync_len = 10,
381 .sync = FB_SYNC_EXT,
382 .vmode = FB_VMODE_NONINTERLACED
383 } }, {
384 .bus = 1,
385 .addr = 0x10,
386 .pixfmt = IPU_PIX_FMT_RGB666,
387 .detect = detect_i2c,
388 .enable = enable_fwadapt_7wvga,
389 .mode = {
390 .name = "FWBADAPT-LCD-F07A-0102",
391 .refresh = 60,
392 .xres = 800,
393 .yres = 480,
394 .pixclock = 33260,
395 .left_margin = 128,
396 .right_margin = 128,
397 .upper_margin = 22,
398 .lower_margin = 22,
399 .hsync_len = 1,
400 .vsync_len = 1,
401 .sync = 0,
402 .vmode = FB_VMODE_NONINTERLACED
403 } } };
404 size_t display_count = ARRAY_SIZE(displays);
405
setup_display(void)406 static void setup_display(void)
407 {
408 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
409 int reg;
410
411 enable_ipu_clock();
412 imx_setup_hdmi();
413
414 reg = readl(&mxc_ccm->chsccdr);
415 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
416 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
417 writel(reg, &mxc_ccm->chsccdr);
418
419 /* Disable LCD backlight */
420 SETUP_IOMUX_PAD(PAD_DI0_PIN4__GPIO4_IO20);
421 gpio_direction_input(IMX_GPIO_NR(4, 20));
422 }
423 #endif /* CONFIG_VIDEO_IPUV3 */
424
board_eth_init(bd_t * bis)425 int board_eth_init(bd_t *bis)
426 {
427 setup_iomux_enet();
428
429 return cpu_eth_init(bis);
430 }
431
board_early_init_f(void)432 int board_early_init_f(void)
433 {
434 setup_iomux_uart();
435 #ifdef CONFIG_SATA
436 setup_sata();
437 #endif
438
439 return 0;
440 }
441
442 #define PMIC_I2C_BUS 2
443
power_init_board(void)444 int power_init_board(void)
445 {
446 struct pmic *p;
447 u32 reg;
448
449 /* configure PFUZE100 PMIC */
450 power_pfuze100_init(PMIC_I2C_BUS);
451 p = pmic_get("PFUZE100");
452 if (p && !pmic_probe(p)) {
453 pmic_reg_read(p, PFUZE100_DEVICEID, ®);
454 printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
455 with_pmic = true;
456
457 /* Set VGEN2 to 1.5V and enable */
458 pmic_reg_read(p, PFUZE100_VGEN2VOL, ®);
459 reg &= ~(LDO_VOL_MASK);
460 reg |= (LDOA_1_50V | (1 << (LDO_EN)));
461 pmic_reg_write(p, PFUZE100_VGEN2VOL, reg);
462 }
463
464 return 0;
465 }
466
467 /*
468 * Do not overwrite the console
469 * Use always serial for U-Boot console
470 */
overwrite_console(void)471 int overwrite_console(void)
472 {
473 return 1;
474 }
475
476 #ifdef CONFIG_CMD_BMODE
477 static const struct boot_mode board_boot_modes[] = {
478 /* 4 bit bus width */
479 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
480 {"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
481 {NULL, 0},
482 };
483 #endif
484
is_revc1(void)485 static bool is_revc1(void)
486 {
487 SETUP_IOMUX_PADS(rev_detection_pad);
488 gpio_direction_input(REV_DETECTION);
489
490 if (gpio_get_value(REV_DETECTION))
491 return true;
492 else
493 return false;
494 }
495
is_revd1(void)496 static bool is_revd1(void)
497 {
498 if (with_pmic)
499 return true;
500 else
501 return false;
502 }
503
board_late_init(void)504 int board_late_init(void)
505 {
506 #ifdef CONFIG_CMD_BMODE
507 add_board_boot_modes(board_boot_modes);
508 #endif
509
510 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
511 if (is_mx6dqp())
512 env_set("board_rev", "MX6QP");
513 else if (is_mx6dq())
514 env_set("board_rev", "MX6Q");
515 else
516 env_set("board_rev", "MX6DL");
517
518 if (is_revd1())
519 env_set("board_name", "D1");
520 else if (is_revc1())
521 env_set("board_name", "C1");
522 else
523 env_set("board_name", "B1");
524 #endif
525 return 0;
526 }
527
board_init(void)528 int board_init(void)
529 {
530 /* address of boot parameters */
531 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
532
533 #if defined(CONFIG_VIDEO_IPUV3)
534 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
535 if (is_mx6dq() || is_mx6dqp()) {
536 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info);
537 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c3_pad_info);
538 } else {
539 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
540 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c3_pad_info);
541 }
542
543 setup_display();
544 #endif
545
546 return 0;
547 }
548
checkboard(void)549 int checkboard(void)
550 {
551 if (is_revd1())
552 puts("Board: Wandboard rev D1\n");
553 else if (is_revc1())
554 puts("Board: Wandboard rev C1\n");
555 else
556 puts("Board: Wandboard rev B1\n");
557
558 return 0;
559 }
560