1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2008 Extreme Engineering Solutions, Inc. 4 * 5 * This driver support NAND devices which have address lines 6 * connected as ALE and CLE inputs. 7 */ 8 9 #include <common.h> 10 #include <nand.h> 11 #include <asm/io.h> 12 13 /* 14 * Hardware specific access to control-lines 15 */ nand_addr_hwcontrol(struct mtd_info * mtd,int cmd,uint ctrl)16static void nand_addr_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl) 17 { 18 struct nand_chip *this = mtd_to_nand(mtd); 19 ulong IO_ADDR_W; 20 21 if (ctrl & NAND_CTRL_CHANGE) { 22 IO_ADDR_W = (ulong)this->IO_ADDR_W; 23 24 IO_ADDR_W &= ~(CONFIG_SYS_NAND_ACTL_CLE | 25 CONFIG_SYS_NAND_ACTL_ALE | 26 CONFIG_SYS_NAND_ACTL_NCE); 27 if (ctrl & NAND_CLE) 28 IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_CLE; 29 if (ctrl & NAND_ALE) 30 IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_ALE; 31 if (ctrl & NAND_NCE) 32 IO_ADDR_W |= CONFIG_SYS_NAND_ACTL_NCE; 33 34 this->IO_ADDR_W = (void *)IO_ADDR_W; 35 } 36 37 if (cmd != NAND_CMD_NONE) 38 writeb(cmd, this->IO_ADDR_W); 39 } 40 board_nand_init(struct nand_chip * nand)41int board_nand_init(struct nand_chip *nand) 42 { 43 nand->ecc.mode = NAND_ECC_SOFT; 44 nand->cmd_ctrl = nand_addr_hwcontrol; 45 nand->chip_delay = CONFIG_SYS_NAND_ACTL_DELAY; 46 47 return 0; 48 } 49