1* Synopsys HSDK clock generation unit 2 3The Synopsys HSDK clock controller generates and supplies clock to various 4controllers and peripherals within the SoC. 5 6Required Properties: 7 8- compatible: should be "snps,hsdk-cgu-clock" 9- reg: the pair of physical base address and length of clock generation unit 10 memory mapped region and creg arc core divider memory mapped region. 11- #clock-cells: should be 1. 12 13Each clock is assigned an identifier and client nodes can use this identifier 14to specify the clock which they consume. All available clocks are defined as 15preprocessor macros in the dt-bindings/clock/snps,hsdk-cgu.h headers and can be 16used in device tree sources. 17 18Example: Clock controller node: 19 20 cgu_clk: cgu-clk@f0000000 { 21 compatible = "snps,hsdk-cgu-clock"; 22 reg = <0xf0000000 0x1000>, <0xf00014B8 0x4>; 23 #clock-cells = <1>; 24 }; 25 26Example: UART controller node that consumes the clock generated by the clock 27controller: 28 29 uart0: serial0@f0005000 { 30 compatible = "snps,dw-apb-uart"; 31 reg = <0xf0005000 0x1000>; 32 reg-shift = <2>; 33 reg-io-width = <4>; 34 clocks = <&cgu_clk CLK_SYS_UART_REF>; 35 }; 36