1* Synopsys DWC Ethernet QoS IP version 4.10 driver (GMAC) 2 3This binding supports the Synopsys Designware Ethernet QoS (Quality Of Service) 4IP block. The IP supports multiple options for bus type, clocking and reset 5structure, and feature list. Consequently, a number of properties and list 6entries in properties are marked as optional, or only required in specific HW 7configurations. 8 9Required properties: 10- compatible: One of: 11 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10" 12 Represents the IP core when integrated into the Axis ARTPEC-6 SoC. 13 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10" 14 Represents the IP core when integrated into the NVIDIA Tegra186 SoC. 15 - "snps,dwc-qos-ethernet-4.10" 16 This combination is deprecated. It should be treated as equivalent to 17 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be 18 compatible with earlier revisions of this binding. 19- reg: Address and length of the register set for the device 20- clocks: Phandle and clock specifiers for each entry in clock-names, in the 21 same order. See ../clock/clock-bindings.txt. 22- clock-names: May contain any/all of the following depending on the IP 23 configuration, in any order: 24 - "tx" 25 The EQOS transmit path clock. The HW signal name is clk_tx_i. 26 In some configurations (e.g. GMII/RGMII), this clock also drives the PHY TX 27 path. In other configurations, other clocks (such as tx_125, rmii) may 28 drive the PHY TX path. 29 - "rx" 30 The EQOS receive path clock. The HW signal name is clk_rx_i. 31 In some configurations (e.g. GMII/RGMII), this clock is derived from the 32 PHY's RX clock output. In other configurations, other clocks (such as 33 rx_125, rmii) may drive the EQOS RX path. 34 In cases where the PHY clock is directly fed into the EQOS receive path 35 without intervening logic, the DT need not represent this clock, since it 36 is assumed to be fully under the control of the PHY device/driver. In 37 cases where SoC integration adds additional logic to this path, such as a 38 SW-controlled clock gate, this clock should be represented in DT. 39 - "slave_bus" 40 The CPU/slave-bus (CSR) interface clock. This applies to any bus type; 41 APB, AHB, AXI, etc. The HW signal name is hclk_i (AHB) or clk_csr_i (other 42 buses). 43 - "master_bus" 44 The master bus interface clock. Only required in configurations that use a 45 separate clock for the master and slave bus interfaces. The HW signal name 46 is hclk_i (AHB) or aclk_i (AXI). 47 - "ptp_ref" 48 The PTP reference clock. The HW signal name is clk_ptp_ref_i. 49 - "phy_ref_clk" 50 This clock is deprecated and should not be used by new compatible values. 51 It is equivalent to "tx". 52 - "apb_pclk" 53 This clock is deprecated and should not be used by new compatible values. 54 It is equivalent to "slave_bus". 55 56 Note: Support for additional IP configurations may require adding the 57 following clocks to this list in the future: clk_rx_125_i, clk_tx_125_i, 58 clk_pmarx_0_i, clk_pmarx1_i, clk_rmii_i, clk_revmii_rx_i, clk_revmii_tx_i. 59 Configurations exist where multiple similar clocks are used at once, e.g. all 60 of clk_rx_125_i, clk_pmarx_0_i, clk_pmarx1_i. For this reason it is best to 61 extend the binding with a separate clock-names entry for each of those RX 62 clocks, rather than repurposing the existing "rx" clock-names entry as a 63 generic/logical clock in a similar fashion to "master_bus" and "slave_bus". 64 This will allow easy support for configurations that support multiple PHY 65 interfaces using a mux, and hence need to have explicit control over 66 specific RX clocks. 67 68 The following compatible values require the following set of clocks: 69 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10": 70 - "slave_bus" 71 - "master_bus" 72 - "rx" 73 - "tx" 74 - "ptp_ref" 75 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10": 76 - "slave_bus" 77 - "master_bus" 78 - "tx" 79 - "ptp_ref" 80 - "snps,dwc-qos-ethernet-4.10" (deprecated): 81 - "phy_ref_clk" 82 - "apb_clk" 83- interrupt-parent: Should be the phandle for the interrupt controller 84 that services interrupts for this device 85- interrupts: Should contain the core's combined interrupt signal 86- phy-mode: See ethernet.txt file in the same directory 87- resets: Phandle and reset specifiers for each entry in reset-names, in the 88 same order. See ../reset/reset.txt. 89- reset-names: May contain any/all of the following depending on the IP 90 configuration, in any order: 91 - "eqos". The reset to the entire module. The HW signal name is hreset_n 92 (AHB) or aresetn_i (AXI). 93 94 The following compatible values require the following set of resets: 95 (the reset properties may be omitted if empty) 96 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10": 97 - "eqos". 98 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10": 99 - None. 100 - "snps,dwc-qos-ethernet-4.10" (deprecated): 101 - None. 102 103Optional properties: 104- dma-coherent: Present if dma operations are coherent 105- mac-address: See ethernet.txt in the same directory 106- local-mac-address: See ethernet.txt in the same directory 107- phy-reset-gpios: Phandle and specifier for any GPIO used to reset the PHY. 108 See ../gpio/gpio.txt. 109- snps,en-lpi: If present it enables use of the AXI low-power interface 110- snps,write-requests: Number of write requests that the AXI port can issue. 111 It depends on the SoC configuration. 112- snps,read-requests: Number of read requests that the AXI port can issue. 113 It depends on the SoC configuration. 114- snps,burst-map: Bitmap of allowed AXI burst lengts, with the LSB 115 representing 4, then 8 etc. 116- snps,txpbl: DMA Programmable burst length for the TX DMA 117- snps,rxpbl: DMA Programmable burst length for the RX DMA 118- snps,en-tx-lpi-clockgating: Enable gating of the MAC TX clock during 119 TX low-power mode. 120- phy-handle: See ethernet.txt file in the same directory 121- mdio device tree subnode: When the GMAC has a phy connected to its local 122 mdio, there must be device tree subnode with the following 123 required properties: 124 - compatible: Must be "snps,dwc-qos-ethernet-mdio". 125 - #address-cells: Must be <1>. 126 - #size-cells: Must be <0>. 127 128 For each phy on the mdio bus, there must be a node with the following 129 fields: 130 131 - reg: phy id used to communicate to phy. 132 - device_type: Must be "ethernet-phy". 133 - fixed-mode device tree subnode: see fixed-link.txt in the same directory 134 135Examples: 136ethernet2@40010000 { 137 clock-names = "phy_ref_clk", "apb_pclk"; 138 clocks = <&clkc 17>, <&clkc 15>; 139 compatible = "snps,dwc-qos-ethernet-4.10"; 140 interrupt-parent = <&intc>; 141 interrupts = <0x0 0x1e 0x4>; 142 reg = <0x40010000 0x4000>; 143 phy-handle = <&phy2>; 144 phy-mode = "gmii"; 145 phy-reset-gpios = <&gpioctlr 43 GPIO_ACTIVE_LOW>; 146 147 snps,en-tx-lpi-clockgating; 148 snps,en-lpi; 149 snps,write-requests = <2>; 150 snps,read-requests = <16>; 151 snps,burst-map = <0x7>; 152 snps,txpbl = <8>; 153 snps,rxpbl = <2>; 154 155 dma-coherent; 156 157 mdio { 158 #address-cells = <0x1>; 159 #size-cells = <0x0>; 160 phy2: phy@1 { 161 compatible = "ethernet-phy-ieee802.3-c22"; 162 device_type = "ethernet-phy"; 163 reg = <0x1>; 164 }; 165 }; 166}; 167