1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) Freescale Semiconductor, Inc. 2006.
4 * Author: Jason Jin<Jason.jin@freescale.com>
5 * Zhang Wei<wei.zhang@freescale.com>
6 *
7 * with the reference on libata and ahci drvier in kernel
8 *
9 * This driver provides a SCSI interface to SATA.
10 */
11 #include <common.h>
12
13 #include <command.h>
14 #include <dm.h>
15 #include <pci.h>
16 #include <asm/processor.h>
17 #include <linux/errno.h>
18 #include <asm/io.h>
19 #include <malloc.h>
20 #include <memalign.h>
21 #include <pci.h>
22 #include <scsi.h>
23 #include <libata.h>
24 #include <linux/ctype.h>
25 #include <ahci.h>
26 #include <dm/device-internal.h>
27 #include <dm/lists.h>
28
29 static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port);
30
31 #ifndef CONFIG_DM_SCSI
32 struct ahci_uc_priv *probe_ent = NULL;
33 #endif
34
35 #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
36
37 /*
38 * Some controllers limit number of blocks they can read/write at once.
39 * Contemporary SSD devices work much faster if the read/write size is aligned
40 * to a power of 2. Let's set default to 128 and allowing to be overwritten if
41 * needed.
42 */
43 #ifndef MAX_SATA_BLOCKS_READ_WRITE
44 #define MAX_SATA_BLOCKS_READ_WRITE 0x80
45 #endif
46
47 /* Maximum timeouts for each event */
48 #define WAIT_MS_SPINUP 20000
49 #define WAIT_MS_DATAIO 10000
50 #define WAIT_MS_FLUSH 5000
51 #define WAIT_MS_LINKUP 200
52
ahci_port_base(void __iomem * base,u32 port)53 __weak void __iomem *ahci_port_base(void __iomem *base, u32 port)
54 {
55 return base + 0x100 + (port * 0x80);
56 }
57
58
ahci_setup_port(struct ahci_ioports * port,void __iomem * base,unsigned int port_idx)59 static void ahci_setup_port(struct ahci_ioports *port, void __iomem *base,
60 unsigned int port_idx)
61 {
62 base = ahci_port_base(base, port_idx);
63
64 port->cmd_addr = base;
65 port->scr_addr = base + PORT_SCR;
66 }
67
68
69 #define msleep(a) udelay(a * 1000)
70
ahci_dcache_flush_range(unsigned long begin,unsigned long len)71 static void ahci_dcache_flush_range(unsigned long begin, unsigned long len)
72 {
73 const unsigned long start = begin;
74 const unsigned long end = start + len;
75
76 debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end);
77 flush_dcache_range(start, end);
78 }
79
80 /*
81 * SATA controller DMAs to physical RAM. Ensure data from the
82 * controller is invalidated from dcache; next access comes from
83 * physical RAM.
84 */
ahci_dcache_invalidate_range(unsigned long begin,unsigned long len)85 static void ahci_dcache_invalidate_range(unsigned long begin, unsigned long len)
86 {
87 const unsigned long start = begin;
88 const unsigned long end = start + len;
89
90 debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end);
91 invalidate_dcache_range(start, end);
92 }
93
94 /*
95 * Ensure data for SATA controller is flushed out of dcache and
96 * written to physical memory.
97 */
ahci_dcache_flush_sata_cmd(struct ahci_ioports * pp)98 static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp)
99 {
100 ahci_dcache_flush_range((unsigned long)pp->cmd_slot,
101 AHCI_PORT_PRIV_DMA_SZ);
102 }
103
waiting_for_cmd_completed(void __iomem * offset,int timeout_msec,u32 sign)104 static int waiting_for_cmd_completed(void __iomem *offset,
105 int timeout_msec,
106 u32 sign)
107 {
108 int i;
109 u32 status;
110
111 for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
112 msleep(1);
113
114 return (i < timeout_msec) ? 0 : -1;
115 }
116
ahci_link_up(struct ahci_uc_priv * uc_priv,u8 port)117 int __weak ahci_link_up(struct ahci_uc_priv *uc_priv, u8 port)
118 {
119 u32 tmp;
120 int j = 0;
121 void __iomem *port_mmio = uc_priv->port[port].port_mmio;
122
123 /*
124 * Bring up SATA link.
125 * SATA link bringup time is usually less than 1 ms; only very
126 * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
127 */
128 while (j < WAIT_MS_LINKUP) {
129 tmp = readl(port_mmio + PORT_SCR_STAT);
130 tmp &= PORT_SCR_STAT_DET_MASK;
131 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
132 return 0;
133 udelay(1000);
134 j++;
135 }
136 return 1;
137 }
138
139 #ifdef CONFIG_SUNXI_AHCI
140 /* The sunxi AHCI controller requires this undocumented setup */
sunxi_dma_init(void __iomem * port_mmio)141 static void sunxi_dma_init(void __iomem *port_mmio)
142 {
143 clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400);
144 }
145 #endif
146
ahci_reset(void __iomem * base)147 int ahci_reset(void __iomem *base)
148 {
149 int i = 1000;
150 u32 __iomem *host_ctl_reg = base + HOST_CTL;
151 u32 tmp = readl(host_ctl_reg); /* global controller reset */
152
153 if ((tmp & HOST_RESET) == 0)
154 writel_with_flush(tmp | HOST_RESET, host_ctl_reg);
155
156 /*
157 * reset must complete within 1 second, or
158 * the hardware should be considered fried.
159 */
160 do {
161 udelay(1000);
162 tmp = readl(host_ctl_reg);
163 i--;
164 } while ((i > 0) && (tmp & HOST_RESET));
165
166 if (i == 0) {
167 printf("controller reset failed (0x%x)\n", tmp);
168 return -1;
169 }
170
171 return 0;
172 }
173
ahci_host_init(struct ahci_uc_priv * uc_priv)174 static int ahci_host_init(struct ahci_uc_priv *uc_priv)
175 {
176 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
177 # ifdef CONFIG_DM_PCI
178 struct udevice *dev = uc_priv->dev;
179 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
180 # else
181 pci_dev_t pdev = uc_priv->dev;
182 unsigned short vendor;
183 # endif
184 u16 tmp16;
185 #endif
186 void __iomem *mmio = uc_priv->mmio_base;
187 u32 tmp, cap_save, cmd;
188 int i, j, ret;
189 void __iomem *port_mmio;
190 u32 port_map;
191
192 debug("ahci_host_init: start\n");
193
194 cap_save = readl(mmio + HOST_CAP);
195 cap_save &= ((1 << 28) | (1 << 17));
196 cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */
197
198 ret = ahci_reset(uc_priv->mmio_base);
199 if (ret)
200 return ret;
201
202 writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
203 writel(cap_save, mmio + HOST_CAP);
204 writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
205
206 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
207 # ifdef CONFIG_DM_PCI
208 if (pplat->vendor == PCI_VENDOR_ID_INTEL) {
209 u16 tmp16;
210
211 dm_pci_read_config16(dev, 0x92, &tmp16);
212 dm_pci_write_config16(dev, 0x92, tmp16 | 0xf);
213 }
214 # else
215 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
216
217 if (vendor == PCI_VENDOR_ID_INTEL) {
218 u16 tmp16;
219 pci_read_config_word(pdev, 0x92, &tmp16);
220 tmp16 |= 0xf;
221 pci_write_config_word(pdev, 0x92, tmp16);
222 }
223 # endif
224 #endif
225 uc_priv->cap = readl(mmio + HOST_CAP);
226 uc_priv->port_map = readl(mmio + HOST_PORTS_IMPL);
227 port_map = uc_priv->port_map;
228 uc_priv->n_ports = (uc_priv->cap & 0x1f) + 1;
229
230 debug("cap 0x%x port_map 0x%x n_ports %d\n",
231 uc_priv->cap, uc_priv->port_map, uc_priv->n_ports);
232
233 if (uc_priv->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID)
234 uc_priv->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID;
235
236 for (i = 0; i < uc_priv->n_ports; i++) {
237 if (!(port_map & (1 << i)))
238 continue;
239 uc_priv->port[i].port_mmio = ahci_port_base(mmio, i);
240 port_mmio = (u8 *)uc_priv->port[i].port_mmio;
241 ahci_setup_port(&uc_priv->port[i], mmio, i);
242
243 /* make sure port is not active */
244 tmp = readl(port_mmio + PORT_CMD);
245 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
246 PORT_CMD_FIS_RX | PORT_CMD_START)) {
247 debug("Port %d is active. Deactivating.\n", i);
248 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
249 PORT_CMD_FIS_RX | PORT_CMD_START);
250 writel_with_flush(tmp, port_mmio + PORT_CMD);
251
252 /* spec says 500 msecs for each bit, so
253 * this is slightly incorrect.
254 */
255 msleep(500);
256 }
257
258 #ifdef CONFIG_SUNXI_AHCI
259 sunxi_dma_init(port_mmio);
260 #endif
261
262 /* Add the spinup command to whatever mode bits may
263 * already be on in the command register.
264 */
265 cmd = readl(port_mmio + PORT_CMD);
266 cmd |= PORT_CMD_SPIN_UP;
267 writel_with_flush(cmd, port_mmio + PORT_CMD);
268
269 /* Bring up SATA link. */
270 ret = ahci_link_up(uc_priv, i);
271 if (ret) {
272 printf("SATA link %d timeout.\n", i);
273 continue;
274 } else {
275 debug("SATA link ok.\n");
276 }
277
278 /* Clear error status */
279 tmp = readl(port_mmio + PORT_SCR_ERR);
280 if (tmp)
281 writel(tmp, port_mmio + PORT_SCR_ERR);
282
283 debug("Spinning up device on SATA port %d... ", i);
284
285 j = 0;
286 while (j < WAIT_MS_SPINUP) {
287 tmp = readl(port_mmio + PORT_TFDATA);
288 if (!(tmp & (ATA_BUSY | ATA_DRQ)))
289 break;
290 udelay(1000);
291 tmp = readl(port_mmio + PORT_SCR_STAT);
292 tmp &= PORT_SCR_STAT_DET_MASK;
293 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
294 break;
295 j++;
296 }
297
298 tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK;
299 if (tmp == PORT_SCR_STAT_DET_COMINIT) {
300 debug("SATA link %d down (COMINIT received), retrying...\n", i);
301 i--;
302 continue;
303 }
304
305 printf("Target spinup took %d ms.\n", j);
306 if (j == WAIT_MS_SPINUP)
307 debug("timeout.\n");
308 else
309 debug("ok.\n");
310
311 tmp = readl(port_mmio + PORT_SCR_ERR);
312 debug("PORT_SCR_ERR 0x%x\n", tmp);
313 writel(tmp, port_mmio + PORT_SCR_ERR);
314
315 /* ack any pending irq events for this port */
316 tmp = readl(port_mmio + PORT_IRQ_STAT);
317 debug("PORT_IRQ_STAT 0x%x\n", tmp);
318 if (tmp)
319 writel(tmp, port_mmio + PORT_IRQ_STAT);
320
321 writel(1 << i, mmio + HOST_IRQ_STAT);
322
323 /* register linkup ports */
324 tmp = readl(port_mmio + PORT_SCR_STAT);
325 debug("SATA port %d status: 0x%x\n", i, tmp);
326 if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY)
327 uc_priv->link_port_map |= (0x01 << i);
328 }
329
330 tmp = readl(mmio + HOST_CTL);
331 debug("HOST_CTL 0x%x\n", tmp);
332 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
333 tmp = readl(mmio + HOST_CTL);
334 debug("HOST_CTL 0x%x\n", tmp);
335 #if !defined(CONFIG_DM_SCSI)
336 #ifndef CONFIG_SCSI_AHCI_PLAT
337 # ifdef CONFIG_DM_PCI
338 dm_pci_read_config16(dev, PCI_COMMAND, &tmp16);
339 tmp |= PCI_COMMAND_MASTER;
340 dm_pci_write_config16(dev, PCI_COMMAND, tmp16);
341 # else
342 pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
343 tmp |= PCI_COMMAND_MASTER;
344 pci_write_config_word(pdev, PCI_COMMAND, tmp16);
345 # endif
346 #endif
347 #endif
348 return 0;
349 }
350
351
ahci_print_info(struct ahci_uc_priv * uc_priv)352 static void ahci_print_info(struct ahci_uc_priv *uc_priv)
353 {
354 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
355 # if defined(CONFIG_DM_PCI)
356 struct udevice *dev = uc_priv->dev;
357 # else
358 pci_dev_t pdev = uc_priv->dev;
359 # endif
360 u16 cc;
361 #endif
362 void __iomem *mmio = uc_priv->mmio_base;
363 u32 vers, cap, cap2, impl, speed;
364 const char *speed_s;
365 const char *scc_s;
366
367 vers = readl(mmio + HOST_VERSION);
368 cap = uc_priv->cap;
369 cap2 = readl(mmio + HOST_CAP2);
370 impl = uc_priv->port_map;
371
372 speed = (cap >> 20) & 0xf;
373 if (speed == 1)
374 speed_s = "1.5";
375 else if (speed == 2)
376 speed_s = "3";
377 else if (speed == 3)
378 speed_s = "6";
379 else
380 speed_s = "?";
381
382 #if defined(CONFIG_SCSI_AHCI_PLAT) || defined(CONFIG_DM_SCSI)
383 scc_s = "SATA";
384 #else
385 # ifdef CONFIG_DM_PCI
386 dm_pci_read_config16(dev, 0x0a, &cc);
387 # else
388 pci_read_config_word(pdev, 0x0a, &cc);
389 # endif
390 if (cc == 0x0101)
391 scc_s = "IDE";
392 else if (cc == 0x0106)
393 scc_s = "SATA";
394 else if (cc == 0x0104)
395 scc_s = "RAID";
396 else
397 scc_s = "unknown";
398 #endif
399 printf("AHCI %02x%02x.%02x%02x "
400 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
401 (vers >> 24) & 0xff,
402 (vers >> 16) & 0xff,
403 (vers >> 8) & 0xff,
404 vers & 0xff,
405 ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
406
407 printf("flags: "
408 "%s%s%s%s%s%s%s"
409 "%s%s%s%s%s%s%s"
410 "%s%s%s%s%s%s\n",
411 cap & (1 << 31) ? "64bit " : "",
412 cap & (1 << 30) ? "ncq " : "",
413 cap & (1 << 28) ? "ilck " : "",
414 cap & (1 << 27) ? "stag " : "",
415 cap & (1 << 26) ? "pm " : "",
416 cap & (1 << 25) ? "led " : "",
417 cap & (1 << 24) ? "clo " : "",
418 cap & (1 << 19) ? "nz " : "",
419 cap & (1 << 18) ? "only " : "",
420 cap & (1 << 17) ? "pmp " : "",
421 cap & (1 << 16) ? "fbss " : "",
422 cap & (1 << 15) ? "pio " : "",
423 cap & (1 << 14) ? "slum " : "",
424 cap & (1 << 13) ? "part " : "",
425 cap & (1 << 7) ? "ccc " : "",
426 cap & (1 << 6) ? "ems " : "",
427 cap & (1 << 5) ? "sxs " : "",
428 cap2 & (1 << 2) ? "apst " : "",
429 cap2 & (1 << 1) ? "nvmp " : "",
430 cap2 & (1 << 0) ? "boh " : "");
431 }
432
433 #if defined(CONFIG_DM_SCSI) || !defined(CONFIG_SCSI_AHCI_PLAT)
434 # if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
ahci_init_one(struct ahci_uc_priv * uc_priv,struct udevice * dev)435 static int ahci_init_one(struct ahci_uc_priv *uc_priv, struct udevice *dev)
436 # else
437 static int ahci_init_one(struct ahci_uc_priv *uc_priv, pci_dev_t dev)
438 # endif
439 {
440 #if !defined(CONFIG_DM_SCSI)
441 u16 vendor;
442 #endif
443 int rc;
444
445 uc_priv->dev = dev;
446
447 uc_priv->host_flags = ATA_FLAG_SATA
448 | ATA_FLAG_NO_LEGACY
449 | ATA_FLAG_MMIO
450 | ATA_FLAG_PIO_DMA
451 | ATA_FLAG_NO_ATAPI;
452 uc_priv->pio_mask = 0x1f;
453 uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
454
455 #if !defined(CONFIG_DM_SCSI)
456 #ifdef CONFIG_DM_PCI
457 uc_priv->mmio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_5,
458 PCI_REGION_MEM);
459
460 /* Take from kernel:
461 * JMicron-specific fixup:
462 * make sure we're in AHCI mode
463 */
464 dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor);
465 if (vendor == 0x197b)
466 dm_pci_write_config8(dev, 0x41, 0xa1);
467 #else
468 uc_priv->mmio_base = pci_map_bar(dev, PCI_BASE_ADDRESS_5,
469 PCI_REGION_MEM);
470
471 /* Take from kernel:
472 * JMicron-specific fixup:
473 * make sure we're in AHCI mode
474 */
475 pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
476 if (vendor == 0x197b)
477 pci_write_config_byte(dev, 0x41, 0xa1);
478 #endif
479 #else
480 struct scsi_platdata *plat = dev_get_uclass_platdata(dev);
481 uc_priv->mmio_base = (void *)plat->base;
482 #endif
483
484 debug("ahci mmio_base=0x%p\n", uc_priv->mmio_base);
485 /* initialize adapter */
486 rc = ahci_host_init(uc_priv);
487 if (rc)
488 goto err_out;
489
490 ahci_print_info(uc_priv);
491
492 return 0;
493
494 err_out:
495 return rc;
496 }
497 #endif
498
499 #define MAX_DATA_BYTE_COUNT (4*1024*1024)
500
ahci_fill_sg(struct ahci_uc_priv * uc_priv,u8 port,unsigned char * buf,int buf_len)501 static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,
502 unsigned char *buf, int buf_len)
503 {
504 struct ahci_ioports *pp = &(uc_priv->port[port]);
505 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
506 u32 sg_count;
507 int i;
508
509 sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
510 if (sg_count > AHCI_MAX_SG) {
511 printf("Error:Too much sg!\n");
512 return -1;
513 }
514
515 for (i = 0; i < sg_count; i++) {
516 ahci_sg->addr =
517 cpu_to_le32((unsigned long) buf + i * MAX_DATA_BYTE_COUNT);
518 ahci_sg->addr_hi = 0;
519 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
520 (buf_len < MAX_DATA_BYTE_COUNT
521 ? (buf_len - 1)
522 : (MAX_DATA_BYTE_COUNT - 1)));
523 ahci_sg++;
524 buf_len -= MAX_DATA_BYTE_COUNT;
525 }
526
527 return sg_count;
528 }
529
530
ahci_fill_cmd_slot(struct ahci_ioports * pp,u32 opts)531 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
532 {
533 pp->cmd_slot->opts = cpu_to_le32(opts);
534 pp->cmd_slot->status = 0;
535 pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff);
536 #ifdef CONFIG_PHYS_64BIT
537 pp->cmd_slot->tbl_addr_hi =
538 cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16));
539 #endif
540 }
541
wait_spinup(void __iomem * port_mmio)542 static int wait_spinup(void __iomem *port_mmio)
543 {
544 ulong start;
545 u32 tf_data;
546
547 start = get_timer(0);
548 do {
549 tf_data = readl(port_mmio + PORT_TFDATA);
550 if (!(tf_data & ATA_BUSY))
551 return 0;
552 } while (get_timer(start) < WAIT_MS_SPINUP);
553
554 return -ETIMEDOUT;
555 }
556
ahci_port_start(struct ahci_uc_priv * uc_priv,u8 port)557 static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
558 {
559 struct ahci_ioports *pp = &(uc_priv->port[port]);
560 void __iomem *port_mmio = pp->port_mmio;
561 u32 port_status;
562 void __iomem *mem;
563
564 debug("Enter start port: %d\n", port);
565 port_status = readl(port_mmio + PORT_SCR_STAT);
566 debug("Port %d status: %x\n", port, port_status);
567 if ((port_status & 0xf) != 0x03) {
568 printf("No Link on this port!\n");
569 return -1;
570 }
571
572 mem = malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
573 if (!mem) {
574 free(pp);
575 printf("%s: No mem for table!\n", __func__);
576 return -ENOMEM;
577 }
578
579 /* Aligned to 2048-bytes */
580 mem = memalign(2048, AHCI_PORT_PRIV_DMA_SZ);
581 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
582
583 /*
584 * First item in chunk of DMA memory: 32-slot command table,
585 * 32 bytes each in size
586 */
587 pp->cmd_slot =
588 (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem);
589 debug("cmd_slot = %p\n", pp->cmd_slot);
590 mem += (AHCI_CMD_SLOT_SZ + 224);
591
592 /*
593 * Second item: Received-FIS area
594 */
595 pp->rx_fis = virt_to_phys((void *)mem);
596 mem += AHCI_RX_FIS_SZ;
597
598 /*
599 * Third item: data area for storing a single command
600 * and its scatter-gather table
601 */
602 pp->cmd_tbl = virt_to_phys((void *)mem);
603 debug("cmd_tbl_dma = %lx\n", pp->cmd_tbl);
604
605 mem += AHCI_CMD_TBL_HDR;
606 pp->cmd_tbl_sg =
607 (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
608
609 writel_with_flush((unsigned long)pp->cmd_slot,
610 port_mmio + PORT_LST_ADDR);
611
612 writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
613
614 #ifdef CONFIG_SUNXI_AHCI
615 sunxi_dma_init(port_mmio);
616 #endif
617
618 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
619 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
620 PORT_CMD_START, port_mmio + PORT_CMD);
621
622 debug("Exit start port %d\n", port);
623
624 /*
625 * Make sure interface is not busy based on error and status
626 * information from task file data register before proceeding
627 */
628 return wait_spinup(port_mmio);
629 }
630
631
ahci_device_data_io(struct ahci_uc_priv * uc_priv,u8 port,u8 * fis,int fis_len,u8 * buf,int buf_len,u8 is_write)632 static int ahci_device_data_io(struct ahci_uc_priv *uc_priv, u8 port, u8 *fis,
633 int fis_len, u8 *buf, int buf_len, u8 is_write)
634 {
635
636 struct ahci_ioports *pp = &(uc_priv->port[port]);
637 void __iomem *port_mmio = pp->port_mmio;
638 u32 opts;
639 u32 port_status;
640 int sg_count;
641
642 debug("Enter %s: for port %d\n", __func__, port);
643
644 if (port > uc_priv->n_ports) {
645 printf("Invalid port number %d\n", port);
646 return -1;
647 }
648
649 port_status = readl(port_mmio + PORT_SCR_STAT);
650 if ((port_status & 0xf) != 0x03) {
651 debug("No Link on port %d!\n", port);
652 return -1;
653 }
654
655 memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
656
657 sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len);
658 opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6);
659 ahci_fill_cmd_slot(pp, opts);
660
661 ahci_dcache_flush_sata_cmd(pp);
662 ahci_dcache_flush_range((unsigned long)buf, (unsigned long)buf_len);
663
664 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
665
666 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
667 WAIT_MS_DATAIO, 0x1)) {
668 printf("timeout exit!\n");
669 return -1;
670 }
671
672 ahci_dcache_invalidate_range((unsigned long)buf,
673 (unsigned long)buf_len);
674 debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status);
675
676 return 0;
677 }
678
679
ata_id_strcpy(u16 * target,u16 * src,int len)680 static char *ata_id_strcpy(u16 *target, u16 *src, int len)
681 {
682 int i;
683 for (i = 0; i < len / 2; i++)
684 target[i] = swab16(src[i]);
685 return (char *)target;
686 }
687
688 /*
689 * SCSI INQUIRY command operation.
690 */
ata_scsiop_inquiry(struct ahci_uc_priv * uc_priv,struct scsi_cmd * pccb)691 static int ata_scsiop_inquiry(struct ahci_uc_priv *uc_priv,
692 struct scsi_cmd *pccb)
693 {
694 static const u8 hdr[] = {
695 0,
696 0,
697 0x5, /* claim SPC-3 version compatibility */
698 2,
699 95 - 4,
700 };
701 u8 fis[20];
702 u16 *idbuf;
703 ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS);
704 u8 port;
705
706 /* Clean ccb data buffer */
707 memset(pccb->pdata, 0, pccb->datalen);
708
709 memcpy(pccb->pdata, hdr, sizeof(hdr));
710
711 if (pccb->datalen <= 35)
712 return 0;
713
714 memset(fis, 0, sizeof(fis));
715 /* Construct the FIS */
716 fis[0] = 0x27; /* Host to device FIS. */
717 fis[1] = 1 << 7; /* Command FIS. */
718 fis[2] = ATA_CMD_ID_ATA; /* Command byte. */
719
720 /* Read id from sata */
721 port = pccb->target;
722
723 if (ahci_device_data_io(uc_priv, port, (u8 *)&fis, sizeof(fis),
724 (u8 *)tmpid, ATA_ID_WORDS * 2, 0)) {
725 debug("scsi_ahci: SCSI inquiry command failure.\n");
726 return -EIO;
727 }
728
729 if (!uc_priv->ataid[port]) {
730 uc_priv->ataid[port] = malloc(ATA_ID_WORDS * 2);
731 if (!uc_priv->ataid[port]) {
732 printf("%s: No memory for ataid[port]\n", __func__);
733 return -ENOMEM;
734 }
735 }
736
737 idbuf = uc_priv->ataid[port];
738
739 memcpy(idbuf, tmpid, ATA_ID_WORDS * 2);
740 ata_swap_buf_le16(idbuf, ATA_ID_WORDS);
741
742 memcpy(&pccb->pdata[8], "ATA ", 8);
743 ata_id_strcpy((u16 *)&pccb->pdata[16], &idbuf[ATA_ID_PROD], 16);
744 ata_id_strcpy((u16 *)&pccb->pdata[32], &idbuf[ATA_ID_FW_REV], 4);
745
746 #ifdef DEBUG
747 ata_dump_id(idbuf);
748 #endif
749 return 0;
750 }
751
752
753 /*
754 * SCSI READ10/WRITE10 command operation.
755 */
ata_scsiop_read_write(struct ahci_uc_priv * uc_priv,struct scsi_cmd * pccb,u8 is_write)756 static int ata_scsiop_read_write(struct ahci_uc_priv *uc_priv,
757 struct scsi_cmd *pccb, u8 is_write)
758 {
759 lbaint_t lba = 0;
760 u16 blocks = 0;
761 u8 fis[20];
762 u8 *user_buffer = pccb->pdata;
763 u32 user_buffer_size = pccb->datalen;
764
765 /* Retrieve the base LBA number from the ccb structure. */
766 if (pccb->cmd[0] == SCSI_READ16) {
767 memcpy(&lba, pccb->cmd + 2, 8);
768 lba = be64_to_cpu(lba);
769 } else {
770 u32 temp;
771 memcpy(&temp, pccb->cmd + 2, 4);
772 lba = be32_to_cpu(temp);
773 }
774
775 /*
776 * Retrieve the base LBA number and the block count from
777 * the ccb structure.
778 *
779 * For 10-byte and 16-byte SCSI R/W commands, transfer
780 * length 0 means transfer 0 block of data.
781 * However, for ATA R/W commands, sector count 0 means
782 * 256 or 65536 sectors, not 0 sectors as in SCSI.
783 *
784 * WARNING: one or two older ATA drives treat 0 as 0...
785 */
786 if (pccb->cmd[0] == SCSI_READ16)
787 blocks = (((u16)pccb->cmd[13]) << 8) | ((u16) pccb->cmd[14]);
788 else
789 blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
790
791 debug("scsi_ahci: %s %u blocks starting from lba 0x" LBAFU "\n",
792 is_write ? "write" : "read", blocks, lba);
793
794 /* Preset the FIS */
795 memset(fis, 0, sizeof(fis));
796 fis[0] = 0x27; /* Host to device FIS. */
797 fis[1] = 1 << 7; /* Command FIS. */
798 /* Command byte (read/write). */
799 fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
800
801 while (blocks) {
802 u16 now_blocks; /* number of blocks per iteration */
803 u32 transfer_size; /* number of bytes per iteration */
804
805 now_blocks = min((u16)MAX_SATA_BLOCKS_READ_WRITE, blocks);
806
807 transfer_size = ATA_SECT_SIZE * now_blocks;
808 if (transfer_size > user_buffer_size) {
809 printf("scsi_ahci: Error: buffer too small.\n");
810 return -EIO;
811 }
812
813 /*
814 * LBA48 SATA command but only use 32bit address range within
815 * that (unless we've enabled 64bit LBA support). The next
816 * smaller command range (28bit) is too small.
817 */
818 fis[4] = (lba >> 0) & 0xff;
819 fis[5] = (lba >> 8) & 0xff;
820 fis[6] = (lba >> 16) & 0xff;
821 fis[7] = 1 << 6; /* device reg: set LBA mode */
822 fis[8] = ((lba >> 24) & 0xff);
823 #ifdef CONFIG_SYS_64BIT_LBA
824 if (pccb->cmd[0] == SCSI_READ16) {
825 fis[9] = ((lba >> 32) & 0xff);
826 fis[10] = ((lba >> 40) & 0xff);
827 }
828 #endif
829
830 fis[3] = 0xe0; /* features */
831
832 /* Block (sector) count */
833 fis[12] = (now_blocks >> 0) & 0xff;
834 fis[13] = (now_blocks >> 8) & 0xff;
835
836 /* Read/Write from ahci */
837 if (ahci_device_data_io(uc_priv, pccb->target, (u8 *)&fis,
838 sizeof(fis), user_buffer, transfer_size,
839 is_write)) {
840 debug("scsi_ahci: SCSI %s10 command failure.\n",
841 is_write ? "WRITE" : "READ");
842 return -EIO;
843 }
844
845 /* If this transaction is a write, do a following flush.
846 * Writes in u-boot are so rare, and the logic to know when is
847 * the last write and do a flush only there is sufficiently
848 * difficult. Just do a flush after every write. This incurs,
849 * usually, one extra flush when the rare writes do happen.
850 */
851 if (is_write) {
852 if (-EIO == ata_io_flush(uc_priv, pccb->target))
853 return -EIO;
854 }
855 user_buffer += transfer_size;
856 user_buffer_size -= transfer_size;
857 blocks -= now_blocks;
858 lba += now_blocks;
859 }
860
861 return 0;
862 }
863
864
865 /*
866 * SCSI READ CAPACITY10 command operation.
867 */
ata_scsiop_read_capacity10(struct ahci_uc_priv * uc_priv,struct scsi_cmd * pccb)868 static int ata_scsiop_read_capacity10(struct ahci_uc_priv *uc_priv,
869 struct scsi_cmd *pccb)
870 {
871 u32 cap;
872 u64 cap64;
873 u32 block_size;
874
875 if (!uc_priv->ataid[pccb->target]) {
876 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
877 "\tNo ATA info!\n"
878 "\tPlease run SCSI command INQUIRY first!\n");
879 return -EPERM;
880 }
881
882 cap64 = ata_id_n_sectors(uc_priv->ataid[pccb->target]);
883 if (cap64 > 0x100000000ULL)
884 cap64 = 0xffffffff;
885
886 cap = cpu_to_be32(cap64);
887 memcpy(pccb->pdata, &cap, sizeof(cap));
888
889 block_size = cpu_to_be32((u32)512);
890 memcpy(&pccb->pdata[4], &block_size, 4);
891
892 return 0;
893 }
894
895
896 /*
897 * SCSI READ CAPACITY16 command operation.
898 */
ata_scsiop_read_capacity16(struct ahci_uc_priv * uc_priv,struct scsi_cmd * pccb)899 static int ata_scsiop_read_capacity16(struct ahci_uc_priv *uc_priv,
900 struct scsi_cmd *pccb)
901 {
902 u64 cap;
903 u64 block_size;
904
905 if (!uc_priv->ataid[pccb->target]) {
906 printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "
907 "\tNo ATA info!\n"
908 "\tPlease run SCSI command INQUIRY first!\n");
909 return -EPERM;
910 }
911
912 cap = ata_id_n_sectors(uc_priv->ataid[pccb->target]);
913 cap = cpu_to_be64(cap);
914 memcpy(pccb->pdata, &cap, sizeof(cap));
915
916 block_size = cpu_to_be64((u64)512);
917 memcpy(&pccb->pdata[8], &block_size, 8);
918
919 return 0;
920 }
921
922
923 /*
924 * SCSI TEST UNIT READY command operation.
925 */
ata_scsiop_test_unit_ready(struct ahci_uc_priv * uc_priv,struct scsi_cmd * pccb)926 static int ata_scsiop_test_unit_ready(struct ahci_uc_priv *uc_priv,
927 struct scsi_cmd *pccb)
928 {
929 return (uc_priv->ataid[pccb->target]) ? 0 : -EPERM;
930 }
931
932
ahci_scsi_exec(struct udevice * dev,struct scsi_cmd * pccb)933 static int ahci_scsi_exec(struct udevice *dev, struct scsi_cmd *pccb)
934 {
935 struct ahci_uc_priv *uc_priv;
936 #ifdef CONFIG_DM_SCSI
937 uc_priv = dev_get_uclass_priv(dev->parent);
938 #else
939 uc_priv = probe_ent;
940 #endif
941 int ret;
942
943 switch (pccb->cmd[0]) {
944 case SCSI_READ16:
945 case SCSI_READ10:
946 ret = ata_scsiop_read_write(uc_priv, pccb, 0);
947 break;
948 case SCSI_WRITE10:
949 ret = ata_scsiop_read_write(uc_priv, pccb, 1);
950 break;
951 case SCSI_RD_CAPAC10:
952 ret = ata_scsiop_read_capacity10(uc_priv, pccb);
953 break;
954 case SCSI_RD_CAPAC16:
955 ret = ata_scsiop_read_capacity16(uc_priv, pccb);
956 break;
957 case SCSI_TST_U_RDY:
958 ret = ata_scsiop_test_unit_ready(uc_priv, pccb);
959 break;
960 case SCSI_INQUIRY:
961 ret = ata_scsiop_inquiry(uc_priv, pccb);
962 break;
963 default:
964 printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
965 return -ENOTSUPP;
966 }
967
968 if (ret) {
969 debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
970 return ret;
971 }
972 return 0;
973
974 }
975
ahci_start_ports(struct ahci_uc_priv * uc_priv)976 static int ahci_start_ports(struct ahci_uc_priv *uc_priv)
977 {
978 u32 linkmap;
979 int i;
980
981 linkmap = uc_priv->link_port_map;
982
983 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
984 if (((linkmap >> i) & 0x01)) {
985 if (ahci_port_start(uc_priv, (u8) i)) {
986 printf("Can not start port %d\n", i);
987 continue;
988 }
989 }
990 }
991
992 return 0;
993 }
994
995 #ifndef CONFIG_DM_SCSI
scsi_low_level_init(int busdevfunc)996 void scsi_low_level_init(int busdevfunc)
997 {
998 struct ahci_uc_priv *uc_priv;
999
1000 #ifndef CONFIG_SCSI_AHCI_PLAT
1001 probe_ent = calloc(1, sizeof(struct ahci_uc_priv));
1002 if (!probe_ent) {
1003 printf("%s: No memory for uc_priv\n", __func__);
1004 return;
1005 }
1006 uc_priv = probe_ent;
1007 # if defined(CONFIG_DM_PCI)
1008 struct udevice *dev;
1009 int ret;
1010
1011 ret = dm_pci_bus_find_bdf(busdevfunc, &dev);
1012 if (ret)
1013 return;
1014 ahci_init_one(uc_priv, dev);
1015 # else
1016 ahci_init_one(uc_priv, busdevfunc);
1017 # endif
1018 #else
1019 uc_priv = probe_ent;
1020 #endif
1021
1022 ahci_start_ports(uc_priv);
1023 }
1024 #endif
1025
1026 #ifndef CONFIG_SCSI_AHCI_PLAT
1027 # if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
ahci_init_one_dm(struct udevice * dev)1028 int ahci_init_one_dm(struct udevice *dev)
1029 {
1030 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
1031
1032 return ahci_init_one(uc_priv, dev);
1033 }
1034 #endif
1035 #endif
1036
ahci_start_ports_dm(struct udevice * dev)1037 int ahci_start_ports_dm(struct udevice *dev)
1038 {
1039 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
1040
1041 return ahci_start_ports(uc_priv);
1042 }
1043
1044 #ifdef CONFIG_SCSI_AHCI_PLAT
ahci_init_common(struct ahci_uc_priv * uc_priv,void __iomem * base)1045 static int ahci_init_common(struct ahci_uc_priv *uc_priv, void __iomem *base)
1046 {
1047 int rc;
1048
1049 uc_priv->host_flags = ATA_FLAG_SATA
1050 | ATA_FLAG_NO_LEGACY
1051 | ATA_FLAG_MMIO
1052 | ATA_FLAG_PIO_DMA
1053 | ATA_FLAG_NO_ATAPI;
1054 uc_priv->pio_mask = 0x1f;
1055 uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
1056
1057 uc_priv->mmio_base = base;
1058
1059 /* initialize adapter */
1060 rc = ahci_host_init(uc_priv);
1061 if (rc)
1062 goto err_out;
1063
1064 ahci_print_info(uc_priv);
1065
1066 rc = ahci_start_ports(uc_priv);
1067
1068 err_out:
1069 return rc;
1070 }
1071
1072 #ifndef CONFIG_DM_SCSI
ahci_init(void __iomem * base)1073 int ahci_init(void __iomem *base)
1074 {
1075 struct ahci_uc_priv *uc_priv;
1076
1077 probe_ent = malloc(sizeof(struct ahci_uc_priv));
1078 if (!probe_ent) {
1079 printf("%s: No memory for uc_priv\n", __func__);
1080 return -ENOMEM;
1081 }
1082
1083 uc_priv = probe_ent;
1084 memset(uc_priv, 0, sizeof(struct ahci_uc_priv));
1085
1086 return ahci_init_common(uc_priv, base);
1087 }
1088 #endif
1089
ahci_init_dm(struct udevice * dev,void __iomem * base)1090 int ahci_init_dm(struct udevice *dev, void __iomem *base)
1091 {
1092 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
1093
1094 return ahci_init_common(uc_priv, base);
1095 }
1096
scsi_init(void)1097 void __weak scsi_init(void)
1098 {
1099 }
1100
1101 #endif /* CONFIG_SCSI_AHCI_PLAT */
1102
1103 /*
1104 * In the general case of generic rotating media it makes sense to have a
1105 * flush capability. It probably even makes sense in the case of SSDs because
1106 * one cannot always know for sure what kind of internal cache/flush mechanism
1107 * is embodied therein. At first it was planned to invoke this after the last
1108 * write to disk and before rebooting. In practice, knowing, a priori, which
1109 * is the last write is difficult. Because writing to the disk in u-boot is
1110 * very rare, this flush command will be invoked after every block write.
1111 */
ata_io_flush(struct ahci_uc_priv * uc_priv,u8 port)1112 static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port)
1113 {
1114 u8 fis[20];
1115 struct ahci_ioports *pp = &(uc_priv->port[port]);
1116 void __iomem *port_mmio = pp->port_mmio;
1117 u32 cmd_fis_len = 5; /* five dwords */
1118
1119 /* Preset the FIS */
1120 memset(fis, 0, 20);
1121 fis[0] = 0x27; /* Host to device FIS. */
1122 fis[1] = 1 << 7; /* Command FIS. */
1123 fis[2] = ATA_CMD_FLUSH_EXT;
1124
1125 memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
1126 ahci_fill_cmd_slot(pp, cmd_fis_len);
1127 ahci_dcache_flush_sata_cmd(pp);
1128 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
1129
1130 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
1131 WAIT_MS_FLUSH, 0x1)) {
1132 debug("scsi_ahci: flush command timeout on port %d.\n", port);
1133 return -EIO;
1134 }
1135
1136 return 0;
1137 }
1138
ahci_scsi_bus_reset(struct udevice * dev)1139 static int ahci_scsi_bus_reset(struct udevice *dev)
1140 {
1141 /* Not implemented */
1142
1143 return 0;
1144 }
1145
1146 #ifdef CONFIG_DM_SCSI
ahci_bind_scsi(struct udevice * ahci_dev,struct udevice ** devp)1147 int ahci_bind_scsi(struct udevice *ahci_dev, struct udevice **devp)
1148 {
1149 struct udevice *dev;
1150 int ret;
1151
1152 ret = device_bind_driver(ahci_dev, "ahci_scsi", "ahci_scsi", &dev);
1153 if (ret)
1154 return ret;
1155 *devp = dev;
1156
1157 return 0;
1158 }
1159
ahci_probe_scsi(struct udevice * ahci_dev,ulong base)1160 int ahci_probe_scsi(struct udevice *ahci_dev, ulong base)
1161 {
1162 struct ahci_uc_priv *uc_priv;
1163 struct scsi_platdata *uc_plat;
1164 struct udevice *dev;
1165 int ret;
1166
1167 device_find_first_child(ahci_dev, &dev);
1168 if (!dev)
1169 return -ENODEV;
1170 uc_plat = dev_get_uclass_platdata(dev);
1171 uc_plat->base = base;
1172 uc_plat->max_lun = 1;
1173 uc_plat->max_id = 2;
1174
1175 uc_priv = dev_get_uclass_priv(ahci_dev);
1176 ret = ahci_init_one(uc_priv, dev);
1177 if (ret)
1178 return ret;
1179 ret = ahci_start_ports(uc_priv);
1180 if (ret)
1181 return ret;
1182
1183 return 0;
1184 }
1185
1186 #ifdef CONFIG_DM_PCI
ahci_probe_scsi_pci(struct udevice * ahci_dev)1187 int ahci_probe_scsi_pci(struct udevice *ahci_dev)
1188 {
1189 ulong base;
1190
1191 base = (ulong)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_5,
1192 PCI_REGION_MEM);
1193
1194 return ahci_probe_scsi(ahci_dev, base);
1195 }
1196 #endif
1197
1198 struct scsi_ops scsi_ops = {
1199 .exec = ahci_scsi_exec,
1200 .bus_reset = ahci_scsi_bus_reset,
1201 };
1202
1203 U_BOOT_DRIVER(ahci_scsi) = {
1204 .name = "ahci_scsi",
1205 .id = UCLASS_SCSI,
1206 .ops = &scsi_ops,
1207 };
1208 #else
scsi_exec(struct udevice * dev,struct scsi_cmd * pccb)1209 int scsi_exec(struct udevice *dev, struct scsi_cmd *pccb)
1210 {
1211 return ahci_scsi_exec(dev, pccb);
1212 }
1213
scsi_bus_reset(struct udevice * dev)1214 __weak int scsi_bus_reset(struct udevice *dev)
1215 {
1216 return ahci_scsi_bus_reset(dev);
1217
1218 return 0;
1219 }
1220 #endif
1221