1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
4 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
5 */
6
7 #include <common.h>
8 #include <clk.h>
9 #include <dm.h>
10 #include <fdtdec.h>
11 #include <asm/arch/gpio.h>
12 #include <asm/arch/stm32.h>
13 #include <asm/gpio.h>
14 #include <asm/io.h>
15 #include <linux/errno.h>
16 #include <linux/io.h>
17
18 #define STM32_GPIOS_PER_BANK 16
19 #define MODE_BITS(gpio_pin) (gpio_pin * 2)
20 #define MODE_BITS_MASK 3
21 #define IN_OUT_BIT_INDEX(gpio_pin) (1UL << (gpio_pin))
22
stm32_gpio_direction_input(struct udevice * dev,unsigned offset)23 static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset)
24 {
25 struct stm32_gpio_priv *priv = dev_get_priv(dev);
26 struct stm32_gpio_regs *regs = priv->regs;
27 int bits_index = MODE_BITS(offset);
28 int mask = MODE_BITS_MASK << bits_index;
29
30 clrsetbits_le32(®s->moder, mask, STM32_GPIO_MODE_IN << bits_index);
31
32 return 0;
33 }
34
stm32_gpio_direction_output(struct udevice * dev,unsigned offset,int value)35 static int stm32_gpio_direction_output(struct udevice *dev, unsigned offset,
36 int value)
37 {
38 struct stm32_gpio_priv *priv = dev_get_priv(dev);
39 struct stm32_gpio_regs *regs = priv->regs;
40 int bits_index = MODE_BITS(offset);
41 int mask = MODE_BITS_MASK << bits_index;
42
43 clrsetbits_le32(®s->moder, mask, STM32_GPIO_MODE_OUT << bits_index);
44 mask = IN_OUT_BIT_INDEX(offset);
45 clrsetbits_le32(®s->odr, mask, value ? mask : 0);
46
47 return 0;
48 }
49
stm32_gpio_get_value(struct udevice * dev,unsigned offset)50 static int stm32_gpio_get_value(struct udevice *dev, unsigned offset)
51 {
52 struct stm32_gpio_priv *priv = dev_get_priv(dev);
53 struct stm32_gpio_regs *regs = priv->regs;
54
55 return readl(®s->idr) & IN_OUT_BIT_INDEX(offset) ? 1 : 0;
56 }
57
stm32_gpio_set_value(struct udevice * dev,unsigned offset,int value)58 static int stm32_gpio_set_value(struct udevice *dev, unsigned offset, int value)
59 {
60 struct stm32_gpio_priv *priv = dev_get_priv(dev);
61 struct stm32_gpio_regs *regs = priv->regs;
62 int mask = IN_OUT_BIT_INDEX(offset);
63
64 clrsetbits_le32(®s->odr, mask, value ? mask : 0);
65
66 return 0;
67 }
68
69 static const struct dm_gpio_ops gpio_stm32_ops = {
70 .direction_input = stm32_gpio_direction_input,
71 .direction_output = stm32_gpio_direction_output,
72 .get_value = stm32_gpio_get_value,
73 .set_value = stm32_gpio_set_value,
74 };
75
gpio_stm32_probe(struct udevice * dev)76 static int gpio_stm32_probe(struct udevice *dev)
77 {
78 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
79 struct stm32_gpio_priv *priv = dev_get_priv(dev);
80 fdt_addr_t addr;
81 const char *name;
82
83 addr = dev_read_addr(dev);
84 if (addr == FDT_ADDR_T_NONE)
85 return -EINVAL;
86
87 priv->regs = (struct stm32_gpio_regs *)addr;
88 name = dev_read_string(dev, "st,bank-name");
89 if (!name)
90 return -EINVAL;
91 uc_priv->bank_name = name;
92 uc_priv->gpio_count = dev_read_u32_default(dev, "ngpios",
93 STM32_GPIOS_PER_BANK);
94 debug("%s, addr = 0x%p, bank_name = %s\n", __func__, (u32 *)priv->regs,
95 uc_priv->bank_name);
96
97 #ifdef CONFIG_CLK
98 struct clk clk;
99 int ret;
100 ret = clk_get_by_index(dev, 0, &clk);
101 if (ret < 0)
102 return ret;
103
104 ret = clk_enable(&clk);
105
106 if (ret) {
107 dev_err(dev, "failed to enable clock\n");
108 return ret;
109 }
110 debug("clock enabled for device %s\n", dev->name);
111 #endif
112
113 return 0;
114 }
115
116 static const struct udevice_id stm32_gpio_ids[] = {
117 { .compatible = "st,stm32-gpio" },
118 { }
119 };
120
121 U_BOOT_DRIVER(gpio_stm32) = {
122 .name = "gpio_stm32",
123 .id = UCLASS_GPIO,
124 .of_match = stm32_gpio_ids,
125 .probe = gpio_stm32_probe,
126 .ops = &gpio_stm32_ops,
127 .flags = DM_FLAG_PRE_RELOC | DM_UC_FLAG_SEQ_ALIAS,
128 .priv_auto_alloc_size = sizeof(struct stm32_gpio_priv),
129 };
130