1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2009
4 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
5 */
6
7 #include <common.h>
8 #include <dm.h>
9 #include <i2c.h>
10 #include <pci.h>
11 #include <reset.h>
12 #include <asm/io.h>
13 #include "designware_i2c.h"
14
15 struct dw_scl_sda_cfg {
16 u32 ss_hcnt;
17 u32 fs_hcnt;
18 u32 ss_lcnt;
19 u32 fs_lcnt;
20 u32 sda_hold;
21 };
22
23 #ifdef CONFIG_X86
24 /* BayTrail HCNT/LCNT/SDA hold time */
25 static struct dw_scl_sda_cfg byt_config = {
26 .ss_hcnt = 0x200,
27 .fs_hcnt = 0x55,
28 .ss_lcnt = 0x200,
29 .fs_lcnt = 0x99,
30 .sda_hold = 0x6,
31 };
32 #endif
33
34 struct dw_i2c {
35 struct i2c_regs *regs;
36 struct dw_scl_sda_cfg *scl_sda_cfg;
37 struct reset_ctl reset_ctl;
38 };
39
40 #ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
dw_i2c_enable(struct i2c_regs * i2c_base,bool enable)41 static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
42 {
43 u32 ena = enable ? IC_ENABLE_0B : 0;
44
45 writel(ena, &i2c_base->ic_enable);
46 }
47 #else
dw_i2c_enable(struct i2c_regs * i2c_base,bool enable)48 static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
49 {
50 u32 ena = enable ? IC_ENABLE_0B : 0;
51 int timeout = 100;
52
53 do {
54 writel(ena, &i2c_base->ic_enable);
55 if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
56 return;
57
58 /*
59 * Wait 10 times the signaling period of the highest I2C
60 * transfer supported by the driver (for 400KHz this is
61 * 25us) as described in the DesignWare I2C databook.
62 */
63 udelay(25);
64 } while (timeout--);
65
66 printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
67 }
68 #endif
69
70 /*
71 * i2c_set_bus_speed - Set the i2c speed
72 * @speed: required i2c speed
73 *
74 * Set the i2c speed.
75 */
__dw_i2c_set_bus_speed(struct i2c_regs * i2c_base,struct dw_scl_sda_cfg * scl_sda_cfg,unsigned int speed)76 static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base,
77 struct dw_scl_sda_cfg *scl_sda_cfg,
78 unsigned int speed)
79 {
80 unsigned int cntl;
81 unsigned int hcnt, lcnt;
82 int i2c_spd;
83
84 if (speed >= I2C_MAX_SPEED)
85 i2c_spd = IC_SPEED_MODE_MAX;
86 else if (speed >= I2C_FAST_SPEED)
87 i2c_spd = IC_SPEED_MODE_FAST;
88 else
89 i2c_spd = IC_SPEED_MODE_STANDARD;
90
91 /* to set speed cltr must be disabled */
92 dw_i2c_enable(i2c_base, false);
93
94 cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
95
96 switch (i2c_spd) {
97 #ifndef CONFIG_X86 /* No High-speed for BayTrail yet */
98 case IC_SPEED_MODE_MAX:
99 cntl |= IC_CON_SPD_SS;
100 if (scl_sda_cfg) {
101 hcnt = scl_sda_cfg->fs_hcnt;
102 lcnt = scl_sda_cfg->fs_lcnt;
103 } else {
104 hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
105 lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
106 }
107 writel(hcnt, &i2c_base->ic_hs_scl_hcnt);
108 writel(lcnt, &i2c_base->ic_hs_scl_lcnt);
109 break;
110 #endif
111
112 case IC_SPEED_MODE_STANDARD:
113 cntl |= IC_CON_SPD_SS;
114 if (scl_sda_cfg) {
115 hcnt = scl_sda_cfg->ss_hcnt;
116 lcnt = scl_sda_cfg->ss_lcnt;
117 } else {
118 hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
119 lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
120 }
121 writel(hcnt, &i2c_base->ic_ss_scl_hcnt);
122 writel(lcnt, &i2c_base->ic_ss_scl_lcnt);
123 break;
124
125 case IC_SPEED_MODE_FAST:
126 default:
127 cntl |= IC_CON_SPD_FS;
128 if (scl_sda_cfg) {
129 hcnt = scl_sda_cfg->fs_hcnt;
130 lcnt = scl_sda_cfg->fs_lcnt;
131 } else {
132 hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
133 lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
134 }
135 writel(hcnt, &i2c_base->ic_fs_scl_hcnt);
136 writel(lcnt, &i2c_base->ic_fs_scl_lcnt);
137 break;
138 }
139
140 writel(cntl, &i2c_base->ic_con);
141
142 /* Configure SDA Hold Time if required */
143 if (scl_sda_cfg)
144 writel(scl_sda_cfg->sda_hold, &i2c_base->ic_sda_hold);
145
146 /* Enable back i2c now speed set */
147 dw_i2c_enable(i2c_base, true);
148
149 return 0;
150 }
151
152 /*
153 * i2c_setaddress - Sets the target slave address
154 * @i2c_addr: target i2c address
155 *
156 * Sets the target slave address.
157 */
i2c_setaddress(struct i2c_regs * i2c_base,unsigned int i2c_addr)158 static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
159 {
160 /* Disable i2c */
161 dw_i2c_enable(i2c_base, false);
162
163 writel(i2c_addr, &i2c_base->ic_tar);
164
165 /* Enable i2c */
166 dw_i2c_enable(i2c_base, true);
167 }
168
169 /*
170 * i2c_flush_rxfifo - Flushes the i2c RX FIFO
171 *
172 * Flushes the i2c RX FIFO
173 */
i2c_flush_rxfifo(struct i2c_regs * i2c_base)174 static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
175 {
176 while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
177 readl(&i2c_base->ic_cmd_data);
178 }
179
180 /*
181 * i2c_wait_for_bb - Waits for bus busy
182 *
183 * Waits for bus busy
184 */
i2c_wait_for_bb(struct i2c_regs * i2c_base)185 static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
186 {
187 unsigned long start_time_bb = get_timer(0);
188
189 while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
190 !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
191
192 /* Evaluate timeout */
193 if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
194 return 1;
195 }
196
197 return 0;
198 }
199
i2c_xfer_init(struct i2c_regs * i2c_base,uchar chip,uint addr,int alen)200 static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
201 int alen)
202 {
203 if (i2c_wait_for_bb(i2c_base))
204 return 1;
205
206 i2c_setaddress(i2c_base, chip);
207 while (alen) {
208 alen--;
209 /* high byte address going out first */
210 writel((addr >> (alen * 8)) & 0xff,
211 &i2c_base->ic_cmd_data);
212 }
213 return 0;
214 }
215
i2c_xfer_finish(struct i2c_regs * i2c_base)216 static int i2c_xfer_finish(struct i2c_regs *i2c_base)
217 {
218 ulong start_stop_det = get_timer(0);
219
220 while (1) {
221 if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
222 readl(&i2c_base->ic_clr_stop_det);
223 break;
224 } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
225 break;
226 }
227 }
228
229 if (i2c_wait_for_bb(i2c_base)) {
230 printf("Timed out waiting for bus\n");
231 return 1;
232 }
233
234 i2c_flush_rxfifo(i2c_base);
235
236 return 0;
237 }
238
239 /*
240 * i2c_read - Read from i2c memory
241 * @chip: target i2c address
242 * @addr: address to read from
243 * @alen:
244 * @buffer: buffer for read data
245 * @len: no of bytes to be read
246 *
247 * Read from i2c memory.
248 */
__dw_i2c_read(struct i2c_regs * i2c_base,u8 dev,uint addr,int alen,u8 * buffer,int len)249 static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
250 int alen, u8 *buffer, int len)
251 {
252 unsigned long start_time_rx;
253 unsigned int active = 0;
254
255 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
256 /*
257 * EEPROM chips that implement "address overflow" are ones
258 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
259 * address and the extra bits end up in the "chip address"
260 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
261 * four 256 byte chips.
262 *
263 * Note that we consider the length of the address field to
264 * still be one byte because the extra address bits are
265 * hidden in the chip address.
266 */
267 dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
268 addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
269
270 debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
271 addr);
272 #endif
273
274 if (i2c_xfer_init(i2c_base, dev, addr, alen))
275 return 1;
276
277 start_time_rx = get_timer(0);
278 while (len) {
279 if (!active) {
280 /*
281 * Avoid writing to ic_cmd_data multiple times
282 * in case this loop spins too quickly and the
283 * ic_status RFNE bit isn't set after the first
284 * write. Subsequent writes to ic_cmd_data can
285 * trigger spurious i2c transfer.
286 */
287 if (len == 1)
288 writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
289 else
290 writel(IC_CMD, &i2c_base->ic_cmd_data);
291 active = 1;
292 }
293
294 if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
295 *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
296 len--;
297 start_time_rx = get_timer(0);
298 active = 0;
299 } else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
300 return 1;
301 }
302 }
303
304 return i2c_xfer_finish(i2c_base);
305 }
306
307 /*
308 * i2c_write - Write to i2c memory
309 * @chip: target i2c address
310 * @addr: address to read from
311 * @alen:
312 * @buffer: buffer for read data
313 * @len: no of bytes to be read
314 *
315 * Write to i2c memory.
316 */
__dw_i2c_write(struct i2c_regs * i2c_base,u8 dev,uint addr,int alen,u8 * buffer,int len)317 static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
318 int alen, u8 *buffer, int len)
319 {
320 int nb = len;
321 unsigned long start_time_tx;
322
323 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
324 /*
325 * EEPROM chips that implement "address overflow" are ones
326 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
327 * address and the extra bits end up in the "chip address"
328 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
329 * four 256 byte chips.
330 *
331 * Note that we consider the length of the address field to
332 * still be one byte because the extra address bits are
333 * hidden in the chip address.
334 */
335 dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
336 addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
337
338 debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
339 addr);
340 #endif
341
342 if (i2c_xfer_init(i2c_base, dev, addr, alen))
343 return 1;
344
345 start_time_tx = get_timer(0);
346 while (len) {
347 if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
348 if (--len == 0) {
349 writel(*buffer | IC_STOP,
350 &i2c_base->ic_cmd_data);
351 } else {
352 writel(*buffer, &i2c_base->ic_cmd_data);
353 }
354 buffer++;
355 start_time_tx = get_timer(0);
356
357 } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
358 printf("Timed out. i2c write Failed\n");
359 return 1;
360 }
361 }
362
363 return i2c_xfer_finish(i2c_base);
364 }
365
366 /*
367 * __dw_i2c_init - Init function
368 * @speed: required i2c speed
369 * @slaveaddr: slave address for the device
370 *
371 * Initialization function.
372 */
__dw_i2c_init(struct i2c_regs * i2c_base,int speed,int slaveaddr)373 static void __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
374 {
375 /* Disable i2c */
376 dw_i2c_enable(i2c_base, false);
377
378 writel(IC_CON_SD | IC_CON_RE | IC_CON_SPD_FS | IC_CON_MM,
379 &i2c_base->ic_con);
380 writel(IC_RX_TL, &i2c_base->ic_rx_tl);
381 writel(IC_TX_TL, &i2c_base->ic_tx_tl);
382 writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
383 #ifndef CONFIG_DM_I2C
384 __dw_i2c_set_bus_speed(i2c_base, NULL, speed);
385 writel(slaveaddr, &i2c_base->ic_sar);
386 #endif
387
388 /* Enable i2c */
389 dw_i2c_enable(i2c_base, true);
390 }
391
392 #ifndef CONFIG_DM_I2C
393 /*
394 * The legacy I2C functions. These need to get removed once
395 * all users of this driver are converted to DM.
396 */
i2c_get_base(struct i2c_adapter * adap)397 static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
398 {
399 switch (adap->hwadapnr) {
400 #if CONFIG_SYS_I2C_BUS_MAX >= 4
401 case 3:
402 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
403 #endif
404 #if CONFIG_SYS_I2C_BUS_MAX >= 3
405 case 2:
406 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
407 #endif
408 #if CONFIG_SYS_I2C_BUS_MAX >= 2
409 case 1:
410 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
411 #endif
412 case 0:
413 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
414 default:
415 printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
416 }
417
418 return NULL;
419 }
420
dw_i2c_set_bus_speed(struct i2c_adapter * adap,unsigned int speed)421 static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
422 unsigned int speed)
423 {
424 adap->speed = speed;
425 return __dw_i2c_set_bus_speed(i2c_get_base(adap), NULL, speed);
426 }
427
dw_i2c_init(struct i2c_adapter * adap,int speed,int slaveaddr)428 static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
429 {
430 __dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
431 }
432
dw_i2c_read(struct i2c_adapter * adap,u8 dev,uint addr,int alen,u8 * buffer,int len)433 static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
434 int alen, u8 *buffer, int len)
435 {
436 return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
437 }
438
dw_i2c_write(struct i2c_adapter * adap,u8 dev,uint addr,int alen,u8 * buffer,int len)439 static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
440 int alen, u8 *buffer, int len)
441 {
442 return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
443 }
444
445 /* dw_i2c_probe - Probe the i2c chip */
dw_i2c_probe(struct i2c_adapter * adap,u8 dev)446 static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
447 {
448 struct i2c_regs *i2c_base = i2c_get_base(adap);
449 u32 tmp;
450 int ret;
451
452 /*
453 * Try to read the first location of the chip.
454 */
455 ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
456 if (ret)
457 dw_i2c_init(adap, adap->speed, adap->slaveaddr);
458
459 return ret;
460 }
461
462 U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
463 dw_i2c_write, dw_i2c_set_bus_speed,
464 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
465
466 #if CONFIG_SYS_I2C_BUS_MAX >= 2
467 U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
468 dw_i2c_write, dw_i2c_set_bus_speed,
469 CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
470 #endif
471
472 #if CONFIG_SYS_I2C_BUS_MAX >= 3
473 U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
474 dw_i2c_write, dw_i2c_set_bus_speed,
475 CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
476 #endif
477
478 #if CONFIG_SYS_I2C_BUS_MAX >= 4
479 U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
480 dw_i2c_write, dw_i2c_set_bus_speed,
481 CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
482 #endif
483
484 #else /* CONFIG_DM_I2C */
485 /* The DM I2C functions */
486
487 static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
488 int nmsgs)
489 {
490 struct dw_i2c *i2c = dev_get_priv(bus);
491 int ret;
492
493 debug("i2c_xfer: %d messages\n", nmsgs);
494 for (; nmsgs > 0; nmsgs--, msg++) {
495 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
496 if (msg->flags & I2C_M_RD) {
497 ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
498 msg->buf, msg->len);
499 } else {
500 ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
501 msg->buf, msg->len);
502 }
503 if (ret) {
504 debug("i2c_write: error sending\n");
505 return -EREMOTEIO;
506 }
507 }
508
509 return 0;
510 }
511
512 static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
513 {
514 struct dw_i2c *i2c = dev_get_priv(bus);
515
516 return __dw_i2c_set_bus_speed(i2c->regs, i2c->scl_sda_cfg, speed);
517 }
518
519 static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
520 uint chip_flags)
521 {
522 struct dw_i2c *i2c = dev_get_priv(bus);
523 struct i2c_regs *i2c_base = i2c->regs;
524 u32 tmp;
525 int ret;
526
527 /* Try to read the first location of the chip */
528 ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
529 if (ret)
530 __dw_i2c_init(i2c_base, 0, 0);
531
532 return ret;
533 }
534
535 static int designware_i2c_probe(struct udevice *bus)
536 {
537 struct dw_i2c *priv = dev_get_priv(bus);
538 int ret;
539
540 if (device_is_on_pci_bus(bus)) {
541 #ifdef CONFIG_DM_PCI
542 /* Save base address from PCI BAR */
543 priv->regs = (struct i2c_regs *)
544 dm_pci_map_bar(bus, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
545 #ifdef CONFIG_X86
546 /* Use BayTrail specific timing values */
547 priv->scl_sda_cfg = &byt_config;
548 #endif
549 #endif
550 } else {
551 priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus);
552 }
553
554 ret = reset_get_by_name(bus, "i2c", &priv->reset_ctl);
555 if (ret)
556 pr_info("reset_get_by_name() failed: %d\n", ret);
557
558 if (&priv->reset_ctl)
559 reset_deassert(&priv->reset_ctl);
560
561 __dw_i2c_init(priv->regs, 0, 0);
562
563 return 0;
564 }
565
566 static int designware_i2c_bind(struct udevice *dev)
567 {
568 static int num_cards;
569 char name[20];
570
571 /* Create a unique device name for PCI type devices */
572 if (device_is_on_pci_bus(dev)) {
573 /*
574 * ToDo:
575 * Setting req_seq in the driver is probably not recommended.
576 * But without a DT alias the number is not configured. And
577 * using this driver is impossible for PCIe I2C devices.
578 * This can be removed, once a better (correct) way for this
579 * is found and implemented.
580 */
581 dev->req_seq = num_cards;
582 sprintf(name, "i2c_designware#%u", num_cards++);
583 device_set_name(dev, name);
584 }
585
586 return 0;
587 }
588
589 static const struct dm_i2c_ops designware_i2c_ops = {
590 .xfer = designware_i2c_xfer,
591 .probe_chip = designware_i2c_probe_chip,
592 .set_bus_speed = designware_i2c_set_bus_speed,
593 };
594
595 static const struct udevice_id designware_i2c_ids[] = {
596 { .compatible = "snps,designware-i2c" },
597 { }
598 };
599
600 U_BOOT_DRIVER(i2c_designware) = {
601 .name = "i2c_designware",
602 .id = UCLASS_I2C,
603 .of_match = designware_i2c_ids,
604 .bind = designware_i2c_bind,
605 .probe = designware_i2c_probe,
606 .priv_auto_alloc_size = sizeof(struct dw_i2c),
607 .ops = &designware_i2c_ops,
608 };
609
610 #ifdef CONFIG_X86
611 static struct pci_device_id designware_pci_supported[] = {
612 /* Intel BayTrail has 7 I2C controller located on the PCI bus */
613 { PCI_VDEVICE(INTEL, 0x0f41) },
614 { PCI_VDEVICE(INTEL, 0x0f42) },
615 { PCI_VDEVICE(INTEL, 0x0f43) },
616 { PCI_VDEVICE(INTEL, 0x0f44) },
617 { PCI_VDEVICE(INTEL, 0x0f45) },
618 { PCI_VDEVICE(INTEL, 0x0f46) },
619 { PCI_VDEVICE(INTEL, 0x0f47) },
620 {},
621 };
622
623 U_BOOT_PCI_DEVICE(i2c_designware, designware_pci_supported);
624 #endif
625
626 #endif /* CONFIG_DM_I2C */
627