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1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * drivers/i2c/rcar_i2c.c
4  *
5  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
6  *
7  * Clock configuration based on Linux i2c-rcar.c:
8  * Copyright (C) 2014-15 Wolfram Sang <wsa@sang-engineering.com>
9  * Copyright (C) 2011-2015 Renesas Electronics Corporation
10  * Copyright (C) 2012-14 Renesas Solutions Corp.
11  *   Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
12  */
13 
14 #include <common.h>
15 #include <clk.h>
16 #include <dm.h>
17 #include <i2c.h>
18 #include <asm/io.h>
19 #include <wait_bit.h>
20 
21 #define RCAR_I2C_ICSCR			0x00
22 #define RCAR_I2C_ICMCR			0x04
23 #define RCAR_I2C_ICMCR_MDBS		BIT(7)
24 #define RCAR_I2C_ICMCR_FSCL		BIT(6)
25 #define RCAR_I2C_ICMCR_FSDA		BIT(5)
26 #define RCAR_I2C_ICMCR_OBPC		BIT(4)
27 #define RCAR_I2C_ICMCR_MIE		BIT(3)
28 #define RCAR_I2C_ICMCR_TSBE		BIT(2)
29 #define RCAR_I2C_ICMCR_FSB		BIT(1)
30 #define RCAR_I2C_ICMCR_ESG		BIT(0)
31 #define RCAR_I2C_ICSSR			0x08
32 #define RCAR_I2C_ICMSR			0x0c
33 #define RCAR_I2C_ICMSR_MASK		0x7f
34 #define RCAR_I2C_ICMSR_MNR		BIT(6)
35 #define RCAR_I2C_ICMSR_MAL		BIT(5)
36 #define RCAR_I2C_ICMSR_MST		BIT(4)
37 #define RCAR_I2C_ICMSR_MDE		BIT(3)
38 #define RCAR_I2C_ICMSR_MDT		BIT(2)
39 #define RCAR_I2C_ICMSR_MDR		BIT(1)
40 #define RCAR_I2C_ICMSR_MAT		BIT(0)
41 #define RCAR_I2C_ICSIER			0x10
42 #define RCAR_I2C_ICMIER			0x14
43 #define RCAR_I2C_ICCCR			0x18
44 #define RCAR_I2C_ICCCR_SCGD_OFF		3
45 #define RCAR_I2C_ICSAR			0x1c
46 #define RCAR_I2C_ICMAR			0x20
47 #define RCAR_I2C_ICRXD_ICTXD		0x24
48 
49 struct rcar_i2c_priv {
50 	void __iomem		*base;
51 	struct clk		clk;
52 	u32			intdelay;
53 	u32			icccr;
54 };
55 
rcar_i2c_finish(struct udevice * dev)56 static int rcar_i2c_finish(struct udevice *dev)
57 {
58 	struct rcar_i2c_priv *priv = dev_get_priv(dev);
59 	int ret;
60 
61 	ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR, RCAR_I2C_ICMSR_MST,
62 				true, 10, true);
63 
64 	writel(0, priv->base + RCAR_I2C_ICSSR);
65 	writel(0, priv->base + RCAR_I2C_ICMSR);
66 	writel(0, priv->base + RCAR_I2C_ICMCR);
67 
68 	return ret;
69 }
70 
rcar_i2c_recover(struct udevice * dev)71 static void rcar_i2c_recover(struct udevice *dev)
72 {
73 	struct rcar_i2c_priv *priv = dev_get_priv(dev);
74 	u32 mcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_OBPC;
75 	u32 mcra = mcr | RCAR_I2C_ICMCR_FSDA;
76 	int i;
77 
78 	/* Send 9 SCL pulses */
79 	for (i = 0; i < 9; i++) {
80 		writel(mcra | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR);
81 		udelay(5);
82 		writel(mcra, priv->base + RCAR_I2C_ICMCR);
83 		udelay(5);
84 	}
85 
86 	/* Send stop condition */
87 	udelay(5);
88 	writel(mcra, priv->base + RCAR_I2C_ICMCR);
89 	udelay(5);
90 	writel(mcr, priv->base + RCAR_I2C_ICMCR);
91 	udelay(5);
92 	writel(mcr | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR);
93 	udelay(5);
94 	writel(mcra | RCAR_I2C_ICMCR_FSCL, priv->base + RCAR_I2C_ICMCR);
95 	udelay(5);
96 }
97 
rcar_i2c_set_addr(struct udevice * dev,u8 chip,u8 read)98 static int rcar_i2c_set_addr(struct udevice *dev, u8 chip, u8 read)
99 {
100 	struct rcar_i2c_priv *priv = dev_get_priv(dev);
101 	u32 mask = RCAR_I2C_ICMSR_MAT |
102 		   (read ? RCAR_I2C_ICMSR_MDR : RCAR_I2C_ICMSR_MDE);
103 	u32 val;
104 	int ret;
105 
106 	writel(0, priv->base + RCAR_I2C_ICMIER);
107 	writel(RCAR_I2C_ICMCR_MDBS, priv->base + RCAR_I2C_ICMCR);
108 	writel(0, priv->base + RCAR_I2C_ICMSR);
109 	writel(priv->icccr, priv->base + RCAR_I2C_ICCCR);
110 
111 	ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMCR,
112 				RCAR_I2C_ICMCR_FSDA, false, 2, true);
113 	if (ret) {
114 		rcar_i2c_recover(dev);
115 		val = readl(priv->base + RCAR_I2C_ICMSR);
116 		if (val & RCAR_I2C_ICMCR_FSDA) {
117 			dev_err(dev, "Bus busy, aborting\n");
118 			return ret;
119 		}
120 	}
121 
122 	writel((chip << 1) | read, priv->base + RCAR_I2C_ICMAR);
123 	writel(0, priv->base + RCAR_I2C_ICMSR);
124 	writel(RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE | RCAR_I2C_ICMCR_ESG,
125 	       priv->base + RCAR_I2C_ICMCR);
126 
127 	ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR, mask,
128 				true, 100, true);
129 	if (ret)
130 		return ret;
131 
132 	/* Check NAK */
133 	if (readl(priv->base + RCAR_I2C_ICMSR) & RCAR_I2C_ICMSR_MNR)
134 		return -EREMOTEIO;
135 
136 	return 0;
137 }
138 
rcar_i2c_read_common(struct udevice * dev,struct i2c_msg * msg)139 static int rcar_i2c_read_common(struct udevice *dev, struct i2c_msg *msg)
140 {
141 	struct rcar_i2c_priv *priv = dev_get_priv(dev);
142 	u32 icmcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE;
143 	int i, ret = -EREMOTEIO;
144 
145 	ret = rcar_i2c_set_addr(dev, msg->addr, 1);
146 	if (ret)
147 		return ret;
148 
149 	for (i = 0; i < msg->len; i++) {
150 		if (msg->len - 1 == i)
151 			icmcr |= RCAR_I2C_ICMCR_FSB;
152 
153 		writel(icmcr, priv->base + RCAR_I2C_ICMCR);
154 		writel(~RCAR_I2C_ICMSR_MDR, priv->base + RCAR_I2C_ICMSR);
155 
156 		ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR,
157 					RCAR_I2C_ICMSR_MDR, true, 100, true);
158 		if (ret)
159 			return ret;
160 
161 		msg->buf[i] = readl(priv->base + RCAR_I2C_ICRXD_ICTXD) & 0xff;
162 	}
163 
164 	writel(~RCAR_I2C_ICMSR_MDR, priv->base + RCAR_I2C_ICMSR);
165 
166 	return rcar_i2c_finish(dev);
167 }
168 
rcar_i2c_write_common(struct udevice * dev,struct i2c_msg * msg)169 static int rcar_i2c_write_common(struct udevice *dev, struct i2c_msg *msg)
170 {
171 	struct rcar_i2c_priv *priv = dev_get_priv(dev);
172 	u32 icmcr = RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE;
173 	int i, ret = -EREMOTEIO;
174 
175 	ret = rcar_i2c_set_addr(dev, msg->addr, 0);
176 	if (ret)
177 		return ret;
178 
179 	for (i = 0; i < msg->len; i++) {
180 		writel(msg->buf[i], priv->base + RCAR_I2C_ICRXD_ICTXD);
181 		writel(icmcr, priv->base + RCAR_I2C_ICMCR);
182 		writel(~RCAR_I2C_ICMSR_MDE, priv->base + RCAR_I2C_ICMSR);
183 
184 		ret = wait_for_bit_le32(priv->base + RCAR_I2C_ICMSR,
185 					RCAR_I2C_ICMSR_MDE, true, 100, true);
186 		if (ret)
187 			return ret;
188 	}
189 
190 	writel(~RCAR_I2C_ICMSR_MDE, priv->base + RCAR_I2C_ICMSR);
191 	icmcr |= RCAR_I2C_ICMCR_FSB;
192 	writel(icmcr, priv->base + RCAR_I2C_ICMCR);
193 
194 	return rcar_i2c_finish(dev);
195 }
196 
rcar_i2c_xfer(struct udevice * dev,struct i2c_msg * msg,int nmsgs)197 static int rcar_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
198 {
199 	int ret;
200 
201 	for (; nmsgs > 0; nmsgs--, msg++) {
202 		if (msg->flags & I2C_M_RD)
203 			ret = rcar_i2c_read_common(dev, msg);
204 		else
205 			ret = rcar_i2c_write_common(dev, msg);
206 
207 		if (ret)
208 			return -EREMOTEIO;
209 	}
210 
211 	return ret;
212 }
213 
rcar_i2c_probe_chip(struct udevice * dev,uint addr,uint flags)214 static int rcar_i2c_probe_chip(struct udevice *dev, uint addr, uint flags)
215 {
216 	struct rcar_i2c_priv *priv = dev_get_priv(dev);
217 	int ret;
218 
219 	/* Ignore address 0, slave address */
220 	if (addr == 0)
221 		return -EINVAL;
222 
223 	ret = rcar_i2c_set_addr(dev, addr, 1);
224 	writel(0, priv->base + RCAR_I2C_ICMSR);
225 	return ret;
226 }
227 
rcar_i2c_set_speed(struct udevice * dev,uint bus_freq_hz)228 static int rcar_i2c_set_speed(struct udevice *dev, uint bus_freq_hz)
229 {
230 	struct rcar_i2c_priv *priv = dev_get_priv(dev);
231 	u32 scgd, cdf, round, ick, sum, scl;
232 	unsigned long rate;
233 
234 	/*
235 	 * calculate SCL clock
236 	 * see
237 	 *	ICCCR
238 	 *
239 	 * ick	= clkp / (1 + CDF)
240 	 * SCL	= ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
241 	 *
242 	 * ick  : I2C internal clock < 20 MHz
243 	 * ticf : I2C SCL falling time
244 	 * tr   : I2C SCL rising  time
245 	 * intd : LSI internal delay
246 	 * clkp : peripheral_clk
247 	 * F[]  : integer up-valuation
248 	 */
249 	rate = clk_get_rate(&priv->clk);
250 	cdf = rate / 20000000;
251 	if (cdf >= 8) {
252 		dev_err(dev, "Input clock %lu too high\n", rate);
253 		return -EIO;
254 	}
255 	ick = rate / (cdf + 1);
256 
257 	/*
258 	 * it is impossible to calculate large scale
259 	 * number on u32. separate it
260 	 *
261 	 * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd)
262 	 *  = F[sum * ick / 1000000000]
263 	 *  = F[(ick / 1000000) * sum / 1000]
264 	 */
265 	sum = 35 + 200 + priv->intdelay;
266 	round = (ick + 500000) / 1000000 * sum;
267 	round = (round + 500) / 1000;
268 
269 	/*
270 	 * SCL	= ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
271 	 *
272 	 * Calculation result (= SCL) should be less than
273 	 * bus_speed for hardware safety
274 	 *
275 	 * We could use something along the lines of
276 	 *	div = ick / (bus_speed + 1) + 1;
277 	 *	scgd = (div - 20 - round + 7) / 8;
278 	 *	scl = ick / (20 + (scgd * 8) + round);
279 	 * (not fully verified) but that would get pretty involved
280 	 */
281 	for (scgd = 0; scgd < 0x40; scgd++) {
282 		scl = ick / (20 + (scgd * 8) + round);
283 		if (scl <= bus_freq_hz)
284 			goto scgd_find;
285 	}
286 	dev_err(dev, "it is impossible to calculate best SCL\n");
287 	return -EIO;
288 
289 scgd_find:
290 	dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
291 		scl, bus_freq_hz, clk_get_rate(&priv->clk), round, cdf, scgd);
292 
293 	priv->icccr = (scgd << RCAR_I2C_ICCCR_SCGD_OFF) | cdf;
294 	writel(priv->icccr, priv->base + RCAR_I2C_ICCCR);
295 
296 	return 0;
297 }
298 
rcar_i2c_probe(struct udevice * dev)299 static int rcar_i2c_probe(struct udevice *dev)
300 {
301 	struct rcar_i2c_priv *priv = dev_get_priv(dev);
302 	int ret;
303 
304 	priv->base = dev_read_addr_ptr(dev);
305 	priv->intdelay = dev_read_u32_default(dev,
306 					      "i2c-scl-internal-delay-ns", 5);
307 
308 	ret = clk_get_by_index(dev, 0, &priv->clk);
309 	if (ret)
310 		return ret;
311 
312 	ret = clk_enable(&priv->clk);
313 	if (ret)
314 		return ret;
315 
316 	/* reset slave mode */
317 	writel(0, priv->base + RCAR_I2C_ICSIER);
318 	writel(0, priv->base + RCAR_I2C_ICSAR);
319 	writel(0, priv->base + RCAR_I2C_ICSCR);
320 	writel(0, priv->base + RCAR_I2C_ICSSR);
321 
322 	/* reset master mode */
323 	writel(0, priv->base + RCAR_I2C_ICMIER);
324 	writel(0, priv->base + RCAR_I2C_ICMCR);
325 	writel(0, priv->base + RCAR_I2C_ICMSR);
326 	writel(0, priv->base + RCAR_I2C_ICMAR);
327 
328 	ret = rcar_i2c_set_speed(dev, 100000);
329 	if (ret)
330 		clk_disable(&priv->clk);
331 
332 	return ret;
333 }
334 
335 static const struct dm_i2c_ops rcar_i2c_ops = {
336 	.xfer		= rcar_i2c_xfer,
337 	.probe_chip	= rcar_i2c_probe_chip,
338 	.set_bus_speed	= rcar_i2c_set_speed,
339 };
340 
341 static const struct udevice_id rcar_i2c_ids[] = {
342 	{ .compatible = "renesas,rcar-gen2-i2c" },
343 	{ }
344 };
345 
346 U_BOOT_DRIVER(i2c_rcar) = {
347 	.name		= "i2c_rcar",
348 	.id		= UCLASS_I2C,
349 	.of_match	= rcar_i2c_ids,
350 	.probe		= rcar_i2c_probe,
351 	.priv_auto_alloc_size = sizeof(struct rcar_i2c_priv),
352 	.ops		= &rcar_i2c_ops,
353 };
354