1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Error Corrected Code Controller (ECC) - System peripherals regsters. 4 * Based on AT91SAM9260 datasheet revision B. 5 */ 6 7 #ifndef ATMEL_NAND_ECC_H 8 #define ATMEL_NAND_ECC_H 9 10 #define ATMEL_ECC_CR 0x00 /* Control register */ 11 #define ATMEL_ECC_RST (1 << 0) /* Reset parity */ 12 13 #define ATMEL_ECC_MR 0x04 /* Mode register */ 14 #define ATMEL_ECC_PAGESIZE (3 << 0) /* Page Size */ 15 #define ATMEL_ECC_PAGESIZE_528 (0) 16 #define ATMEL_ECC_PAGESIZE_1056 (1) 17 #define ATMEL_ECC_PAGESIZE_2112 (2) 18 #define ATMEL_ECC_PAGESIZE_4224 (3) 19 20 #define ATMEL_ECC_SR 0x08 /* Status register */ 21 #define ATMEL_ECC_RECERR (1 << 0) /* Recoverable Error */ 22 #define ATMEL_ECC_ECCERR (1 << 1) /* ECC Single Bit Error */ 23 #define ATMEL_ECC_MULERR (1 << 2) /* Multiple Errors */ 24 25 #define ATMEL_ECC_PR 0x0c /* Parity register */ 26 #define ATMEL_ECC_BITADDR (0xf << 0) /* Bit Error Address */ 27 #define ATMEL_ECC_WORDADDR (0xfff << 4) /* Word Error Address */ 28 29 #define ATMEL_ECC_NPR 0x10 /* NParity register */ 30 #define ATMEL_ECC_NPARITY (0xffff << 0) /* NParity */ 31 32 /* Register access macros for PMECC */ 33 #define pmecc_readl(addr, reg) \ 34 readl(&addr->reg) 35 36 #define pmecc_readb(addr, reg) \ 37 readb(&addr->reg) 38 39 #define pmecc_writel(addr, reg, value) \ 40 writel((value), &addr->reg) 41 42 /* PMECC Register Definitions */ 43 #define PMECC_MAX_SECTOR_NUM 8 44 struct pmecc_regs { 45 u32 cfg; /* 0x00 PMECC Configuration Register */ 46 u32 sarea; /* 0x04 PMECC Spare Area Size Register */ 47 u32 saddr; /* 0x08 PMECC Start Address Register */ 48 u32 eaddr; /* 0x0C PMECC End Address Register */ 49 u32 clk; /* 0x10 PMECC Clock Control Register */ 50 u32 ctrl; /* 0x14 PMECC Control Register */ 51 u32 sr; /* 0x18 PMECC Status Register */ 52 u32 ier; /* 0x1C PMECC Interrupt Enable Register */ 53 u32 idr; /* 0x20 PMECC Interrupt Disable Register */ 54 u32 imr; /* 0x24 PMECC Interrupt Mask Register */ 55 u32 isr; /* 0x28 PMECC Interrupt Status Register */ 56 u32 reserved0[5]; /* 0x2C-0x3C Reserved */ 57 58 /* 0x40 + sector_num * (0x40), Redundancy Registers */ 59 struct { 60 #ifdef CONFIG_SAMA5D2 61 u8 ecc[56]; /* PMECC Generated Redundancy Byte Per Sector */ 62 u32 reserved1[2]; 63 #else 64 u8 ecc[44]; /* PMECC Generated Redundancy Byte Per Sector */ 65 u32 reserved1[5]; 66 #endif 67 } ecc_port[PMECC_MAX_SECTOR_NUM]; 68 69 /* 0x240 + sector_num * (0x40) Remainder Registers */ 70 struct { 71 #ifdef CONFIG_SAMA5D2 72 u32 rem[16]; 73 #else 74 u32 rem[12]; 75 u32 reserved2[4]; 76 #endif 77 } rem_port[PMECC_MAX_SECTOR_NUM]; 78 u32 reserved3[16]; /* 0x440-0x47C Reserved */ 79 }; 80 81 /* For PMECC Configuration Register */ 82 #define PMECC_CFG_BCH_ERR2 (0 << 0) 83 #define PMECC_CFG_BCH_ERR4 (1 << 0) 84 #define PMECC_CFG_BCH_ERR8 (2 << 0) 85 #define PMECC_CFG_BCH_ERR12 (3 << 0) 86 #define PMECC_CFG_BCH_ERR24 (4 << 0) 87 #define PMECC_CFG_BCH_ERR32 (5 << 0) 88 89 #define PMECC_CFG_SECTOR512 (0 << 4) 90 #define PMECC_CFG_SECTOR1024 (1 << 4) 91 92 #define PMECC_CFG_PAGE_1SECTOR (0 << 8) 93 #define PMECC_CFG_PAGE_2SECTORS (1 << 8) 94 #define PMECC_CFG_PAGE_4SECTORS (2 << 8) 95 #define PMECC_CFG_PAGE_8SECTORS (3 << 8) 96 97 #define PMECC_CFG_READ_OP (0 << 12) 98 #define PMECC_CFG_WRITE_OP (1 << 12) 99 100 #define PMECC_CFG_SPARE_ENABLE (1 << 16) 101 #define PMECC_CFG_SPARE_DISABLE (0 << 16) 102 103 #define PMECC_CFG_AUTO_ENABLE (1 << 20) 104 #define PMECC_CFG_AUTO_DISABLE (0 << 20) 105 106 /* For PMECC Clock Control Register */ 107 #define PMECC_CLK_133MHZ (2 << 0) 108 109 /* For PMECC Control Register */ 110 #define PMECC_CTRL_RST (1 << 0) 111 #define PMECC_CTRL_DATA (1 << 1) 112 #define PMECC_CTRL_USER (1 << 2) 113 #define PMECC_CTRL_ENABLE (1 << 4) 114 #define PMECC_CTRL_DISABLE (1 << 5) 115 116 /* For PMECC Status Register */ 117 #define PMECC_SR_BUSY (1 << 0) 118 #define PMECC_SR_ENABLE (1 << 4) 119 120 /* PMERRLOC Register Definitions */ 121 struct pmecc_errloc_regs { 122 u32 elcfg; /* 0x00 Error Location Configuration Register */ 123 u32 elprim; /* 0x04 Error Location Primitive Register */ 124 u32 elen; /* 0x08 Error Location Enable Register */ 125 u32 eldis; /* 0x0C Error Location Disable Register */ 126 u32 elsr; /* 0x10 Error Location Status Register */ 127 u32 elier; /* 0x14 Error Location Interrupt Enable Register */ 128 u32 elidr; /* 0x08 Error Location Interrupt Disable Register */ 129 u32 elimr; /* 0x0C Error Location Interrupt Mask Register */ 130 u32 elisr; /* 0x20 Error Location Interrupt Status Register */ 131 u32 reserved0; /* 0x24 Reserved */ 132 #ifdef CONFIG_SAMA5D2 133 u32 sigma[33]; /* 0x28-0xA8 Error Location Sigma Registers */ 134 u32 el[32]; /* 0xAC-0x128 Error Location Registers */ 135 136 /* 137 * 0x12C-0x1FC: 138 * Reserved for SAMA5D2. 139 */ 140 u32 reserved1[53]; 141 #else 142 u32 sigma[25]; /* 0x28-0x88 Error Location Sigma Registers */ 143 u32 el[24]; /* 0x8C-0xE8 Error Location Registers */ 144 u32 reserved1[5]; /* 0xEC-0xFC Reserved */ 145 #endif 146 147 /* 148 * SAMA5 chip HSMC registers start here. But for 9X5 chip it is just 149 * reserved. 150 * 151 * Offset 0x00-0xF8: 152 */ 153 u32 reserved2[63]; 154 155 /* 156 * Offset 0xFC: 157 * PMECC version for AT91SAM9X5, AT91SAM9N12. 158 * HSMC version for SAMA5D3, SAMA5D4. Can refer as PMECC version. 159 */ 160 u32 version; 161 }; 162 163 /* For Error Location Configuration Register */ 164 #define PMERRLOC_ELCFG_SECTOR_512 (0 << 0) 165 #define PMERRLOC_ELCFG_SECTOR_1024 (1 << 0) 166 #define PMERRLOC_ELCFG_NUM_ERRORS(n) ((n) << 16) 167 168 /* For Error Location Disable Register */ 169 #define PMERRLOC_DISABLE (1 << 0) 170 171 /* For Error Location Interrupt Status Register */ 172 #ifdef CONFIG_SAMA5D2 173 #define PMERRLOC_ERR_NUM_MASK (0x3f << 8) 174 #else 175 #define PMERRLOC_ERR_NUM_MASK (0x1f << 8) 176 #endif 177 178 #define PMERRLOC_CALC_DONE (1 << 0) 179 180 /* PMECC IP version */ 181 #define PMECC_VERSION_SAMA5D2 0x210 182 #define PMECC_VERSION_SAMA5D4 0x113 183 #define PMECC_VERSION_SAMA5D3 0x112 184 #define PMECC_VERSION_AT91SAM9N12 0x102 185 #define PMECC_VERSION_AT91SAM9X5 0x101 186 187 /* Galois field dimension */ 188 #define PMECC_GF_DIMENSION_13 13 189 #define PMECC_GF_DIMENSION_14 14 190 191 /* Primitive Polynomial used by PMECC */ 192 #define PMECC_GF_13_PRIMITIVE_POLY 0x201b 193 #define PMECC_GF_14_PRIMITIVE_POLY 0x4443 194 195 #define PMECC_INDEX_TABLE_SIZE_512 0x2000 196 #define PMECC_INDEX_TABLE_SIZE_1024 0x4000 197 198 #define PMECC_MAX_TIMEOUT_US (100 * 1000) 199 200 /* Reserved bytes in oob area */ 201 #define PMECC_OOB_RESERVED_BYTES 2 202 203 #endif 204