1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 dm9000.c: Version 1.2 12/15/2003
4
5 A Davicom DM9000 ISA NIC fast Ethernet driver for Linux.
6 Copyright (C) 1997 Sten Wang
7
8 (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
9
10 V0.11 06/20/2001 REG_0A bit3=1, default enable BP with DA match
11 06/22/2001 Support DM9801 progrmming
12 E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000
13 E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200
14 R17 = (R17 & 0xfff0) | NF + 3
15 E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200
16 R17 = (R17 & 0xfff0) | NF
17
18 v1.00 modify by simon 2001.9.5
19 change for kernel 2.4.x
20
21 v1.1 11/09/2001 fix force mode bug
22
23 v1.2 03/18/2003 Weilun Huang <weilun_huang@davicom.com.tw>:
24 Fixed phy reset.
25 Added tx/rx 32 bit mode.
26 Cleaned up for kernel merge.
27
28 --------------------------------------
29
30 12/15/2003 Initial port to u-boot by
31 Sascha Hauer <saschahauer@web.de>
32
33 06/03/2008 Remy Bohmer <linux@bohmer.net>
34 - Fixed the driver to work with DM9000A.
35 (check on ISR receive status bit before reading the
36 FIFO as described in DM9000 programming guide and
37 application notes)
38 - Added autodetect of databus width.
39 - Made debug code compile again.
40 - Adapt eth_send such that it matches the DM9000*
41 application notes. Needed to make it work properly
42 for DM9000A.
43 - Adapted reset procedure to match DM9000 application
44 notes (i.e. double reset)
45 - some minor code cleanups
46 These changes are tested with DM9000{A,EP,E} together
47 with a 200MHz Atmel AT91SAM9261 core
48
49 TODO: external MII is not functional, only internal at the moment.
50 */
51
52 #include <common.h>
53 #include <command.h>
54 #include <net.h>
55 #include <asm/io.h>
56 #include <dm9000.h>
57
58 #include "dm9000x.h"
59
60 /* Board/System/Debug information/definition ---------------- */
61
62 /* #define CONFIG_DM9000_DEBUG */
63
64 #ifdef CONFIG_DM9000_DEBUG
65 #define DM9000_DBG(fmt,args...) printf(fmt, ##args)
66 #define DM9000_DMP_PACKET(func,packet,length) \
67 do { \
68 int i; \
69 printf("%s: length: %d\n", func, length); \
70 for (i = 0; i < length; i++) { \
71 if (i % 8 == 0) \
72 printf("\n%s: %02x: ", func, i); \
73 printf("%02x ", ((unsigned char *) packet)[i]); \
74 } printf("\n"); \
75 } while(0)
76 #else
77 #define DM9000_DBG(fmt,args...)
78 #define DM9000_DMP_PACKET(func,packet,length)
79 #endif
80
81 /* Structure/enum declaration ------------------------------- */
82 typedef struct board_info {
83 u32 runt_length_counter; /* counter: RX length < 64byte */
84 u32 long_length_counter; /* counter: RX length > 1514byte */
85 u32 reset_counter; /* counter: RESET */
86 u32 reset_tx_timeout; /* RESET caused by TX Timeout */
87 u32 reset_rx_status; /* RESET caused by RX Statsus wrong */
88 u16 tx_pkt_cnt;
89 u16 queue_start_addr;
90 u16 dbug_cnt;
91 u8 phy_addr;
92 u8 device_wait_reset; /* device state */
93 unsigned char srom[128];
94 void (*outblk)(volatile void *data_ptr, int count);
95 void (*inblk)(void *data_ptr, int count);
96 void (*rx_status)(u16 *RxStatus, u16 *RxLen);
97 struct eth_device netdev;
98 } board_info_t;
99 static board_info_t dm9000_info;
100
101
102 /* function declaration ------------------------------------- */
103 static int dm9000_probe(void);
104 static u16 dm9000_phy_read(int);
105 static void dm9000_phy_write(int, u16);
106 static u8 DM9000_ior(int);
107 static void DM9000_iow(int reg, u8 value);
108
109 /* DM9000 network board routine ---------------------------- */
110 #ifndef CONFIG_DM9000_BYTE_SWAPPED
111 #define DM9000_outb(d,r) writeb(d, (volatile u8 *)(r))
112 #define DM9000_outw(d,r) writew(d, (volatile u16 *)(r))
113 #define DM9000_outl(d,r) writel(d, (volatile u32 *)(r))
114 #define DM9000_inb(r) readb((volatile u8 *)(r))
115 #define DM9000_inw(r) readw((volatile u16 *)(r))
116 #define DM9000_inl(r) readl((volatile u32 *)(r))
117 #else
118 #define DM9000_outb(d, r) __raw_writeb(d, r)
119 #define DM9000_outw(d, r) __raw_writew(d, r)
120 #define DM9000_outl(d, r) __raw_writel(d, r)
121 #define DM9000_inb(r) __raw_readb(r)
122 #define DM9000_inw(r) __raw_readw(r)
123 #define DM9000_inl(r) __raw_readl(r)
124 #endif
125
126 #ifdef CONFIG_DM9000_DEBUG
127 static void
dump_regs(void)128 dump_regs(void)
129 {
130 DM9000_DBG("\n");
131 DM9000_DBG("NCR (0x00): %02x\n", DM9000_ior(0));
132 DM9000_DBG("NSR (0x01): %02x\n", DM9000_ior(1));
133 DM9000_DBG("TCR (0x02): %02x\n", DM9000_ior(2));
134 DM9000_DBG("TSRI (0x03): %02x\n", DM9000_ior(3));
135 DM9000_DBG("TSRII (0x04): %02x\n", DM9000_ior(4));
136 DM9000_DBG("RCR (0x05): %02x\n", DM9000_ior(5));
137 DM9000_DBG("RSR (0x06): %02x\n", DM9000_ior(6));
138 DM9000_DBG("ISR (0xFE): %02x\n", DM9000_ior(DM9000_ISR));
139 DM9000_DBG("\n");
140 }
141 #endif
142
dm9000_outblk_8bit(volatile void * data_ptr,int count)143 static void dm9000_outblk_8bit(volatile void *data_ptr, int count)
144 {
145 int i;
146 for (i = 0; i < count; i++)
147 DM9000_outb((((u8 *) data_ptr)[i] & 0xff), DM9000_DATA);
148 }
149
dm9000_outblk_16bit(volatile void * data_ptr,int count)150 static void dm9000_outblk_16bit(volatile void *data_ptr, int count)
151 {
152 int i;
153 u32 tmplen = (count + 1) / 2;
154
155 for (i = 0; i < tmplen; i++)
156 DM9000_outw(((u16 *) data_ptr)[i], DM9000_DATA);
157 }
dm9000_outblk_32bit(volatile void * data_ptr,int count)158 static void dm9000_outblk_32bit(volatile void *data_ptr, int count)
159 {
160 int i;
161 u32 tmplen = (count + 3) / 4;
162
163 for (i = 0; i < tmplen; i++)
164 DM9000_outl(((u32 *) data_ptr)[i], DM9000_DATA);
165 }
166
dm9000_inblk_8bit(void * data_ptr,int count)167 static void dm9000_inblk_8bit(void *data_ptr, int count)
168 {
169 int i;
170 for (i = 0; i < count; i++)
171 ((u8 *) data_ptr)[i] = DM9000_inb(DM9000_DATA);
172 }
173
dm9000_inblk_16bit(void * data_ptr,int count)174 static void dm9000_inblk_16bit(void *data_ptr, int count)
175 {
176 int i;
177 u32 tmplen = (count + 1) / 2;
178
179 for (i = 0; i < tmplen; i++)
180 ((u16 *) data_ptr)[i] = DM9000_inw(DM9000_DATA);
181 }
dm9000_inblk_32bit(void * data_ptr,int count)182 static void dm9000_inblk_32bit(void *data_ptr, int count)
183 {
184 int i;
185 u32 tmplen = (count + 3) / 4;
186
187 for (i = 0; i < tmplen; i++)
188 ((u32 *) data_ptr)[i] = DM9000_inl(DM9000_DATA);
189 }
190
dm9000_rx_status_32bit(u16 * RxStatus,u16 * RxLen)191 static void dm9000_rx_status_32bit(u16 *RxStatus, u16 *RxLen)
192 {
193 u32 tmpdata;
194
195 DM9000_outb(DM9000_MRCMD, DM9000_IO);
196
197 tmpdata = DM9000_inl(DM9000_DATA);
198 *RxStatus = __le16_to_cpu(tmpdata);
199 *RxLen = __le16_to_cpu(tmpdata >> 16);
200 }
201
dm9000_rx_status_16bit(u16 * RxStatus,u16 * RxLen)202 static void dm9000_rx_status_16bit(u16 *RxStatus, u16 *RxLen)
203 {
204 DM9000_outb(DM9000_MRCMD, DM9000_IO);
205
206 *RxStatus = __le16_to_cpu(DM9000_inw(DM9000_DATA));
207 *RxLen = __le16_to_cpu(DM9000_inw(DM9000_DATA));
208 }
209
dm9000_rx_status_8bit(u16 * RxStatus,u16 * RxLen)210 static void dm9000_rx_status_8bit(u16 *RxStatus, u16 *RxLen)
211 {
212 DM9000_outb(DM9000_MRCMD, DM9000_IO);
213
214 *RxStatus =
215 __le16_to_cpu(DM9000_inb(DM9000_DATA) +
216 (DM9000_inb(DM9000_DATA) << 8));
217 *RxLen =
218 __le16_to_cpu(DM9000_inb(DM9000_DATA) +
219 (DM9000_inb(DM9000_DATA) << 8));
220 }
221
222 /*
223 Search DM9000 board, allocate space and register it
224 */
225 int
dm9000_probe(void)226 dm9000_probe(void)
227 {
228 u32 id_val;
229 id_val = DM9000_ior(DM9000_VIDL);
230 id_val |= DM9000_ior(DM9000_VIDH) << 8;
231 id_val |= DM9000_ior(DM9000_PIDL) << 16;
232 id_val |= DM9000_ior(DM9000_PIDH) << 24;
233 if (id_val == DM9000_ID) {
234 printf("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE,
235 id_val);
236 return 0;
237 } else {
238 printf("dm9000 not found at 0x%08x id: 0x%08x\n",
239 CONFIG_DM9000_BASE, id_val);
240 return -1;
241 }
242 }
243
244 /* General Purpose dm9000 reset routine */
245 static void
dm9000_reset(void)246 dm9000_reset(void)
247 {
248 DM9000_DBG("resetting DM9000\n");
249
250 /* Reset DM9000,
251 see DM9000 Application Notes V1.22 Jun 11, 2004 page 29 */
252
253 /* DEBUG: Make all GPIO0 outputs, all others inputs */
254 DM9000_iow(DM9000_GPCR, GPCR_GPIO0_OUT);
255 /* Step 1: Power internal PHY by writing 0 to GPIO0 pin */
256 DM9000_iow(DM9000_GPR, 0);
257 /* Step 2: Software reset */
258 DM9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST));
259
260 do {
261 DM9000_DBG("resetting the DM9000, 1st reset\n");
262 udelay(25); /* Wait at least 20 us */
263 } while (DM9000_ior(DM9000_NCR) & 1);
264
265 DM9000_iow(DM9000_NCR, 0);
266 DM9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST)); /* Issue a second reset */
267
268 do {
269 DM9000_DBG("resetting the DM9000, 2nd reset\n");
270 udelay(25); /* Wait at least 20 us */
271 } while (DM9000_ior(DM9000_NCR) & 1);
272
273 /* Check whether the ethernet controller is present */
274 if ((DM9000_ior(DM9000_PIDL) != 0x0) ||
275 (DM9000_ior(DM9000_PIDH) != 0x90))
276 printf("ERROR: resetting DM9000 -> not responding\n");
277 }
278
279 /* Initialize dm9000 board
280 */
dm9000_init(struct eth_device * dev,bd_t * bd)281 static int dm9000_init(struct eth_device *dev, bd_t *bd)
282 {
283 int i, oft, lnk;
284 u8 io_mode;
285 struct board_info *db = &dm9000_info;
286
287 DM9000_DBG("%s\n", __func__);
288
289 /* RESET device */
290 dm9000_reset();
291
292 if (dm9000_probe() < 0)
293 return -1;
294
295 /* Auto-detect 8/16/32 bit mode, ISR Bit 6+7 indicate bus width */
296 io_mode = DM9000_ior(DM9000_ISR) >> 6;
297
298 switch (io_mode) {
299 case 0x0: /* 16-bit mode */
300 printf("DM9000: running in 16 bit mode\n");
301 db->outblk = dm9000_outblk_16bit;
302 db->inblk = dm9000_inblk_16bit;
303 db->rx_status = dm9000_rx_status_16bit;
304 break;
305 case 0x01: /* 32-bit mode */
306 printf("DM9000: running in 32 bit mode\n");
307 db->outblk = dm9000_outblk_32bit;
308 db->inblk = dm9000_inblk_32bit;
309 db->rx_status = dm9000_rx_status_32bit;
310 break;
311 case 0x02: /* 8 bit mode */
312 printf("DM9000: running in 8 bit mode\n");
313 db->outblk = dm9000_outblk_8bit;
314 db->inblk = dm9000_inblk_8bit;
315 db->rx_status = dm9000_rx_status_8bit;
316 break;
317 default:
318 /* Assume 8 bit mode, will probably not work anyway */
319 printf("DM9000: Undefined IO-mode:0x%x\n", io_mode);
320 db->outblk = dm9000_outblk_8bit;
321 db->inblk = dm9000_inblk_8bit;
322 db->rx_status = dm9000_rx_status_8bit;
323 break;
324 }
325
326 /* Program operating register, only internal phy supported */
327 DM9000_iow(DM9000_NCR, 0x0);
328 /* TX Polling clear */
329 DM9000_iow(DM9000_TCR, 0);
330 /* Less 3Kb, 200us */
331 DM9000_iow(DM9000_BPTR, BPTR_BPHW(3) | BPTR_JPT_600US);
332 /* Flow Control : High/Low Water */
333 DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8));
334 /* SH FIXME: This looks strange! Flow Control */
335 DM9000_iow(DM9000_FCR, 0x0);
336 /* Special Mode */
337 DM9000_iow(DM9000_SMCR, 0);
338 /* clear TX status */
339 DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);
340 /* Clear interrupt status */
341 DM9000_iow(DM9000_ISR, ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS);
342
343 printf("MAC: %pM\n", dev->enetaddr);
344 if (!is_valid_ethaddr(dev->enetaddr)) {
345 printf("WARNING: Bad MAC address (uninitialized EEPROM?)\n");
346 }
347
348 /* fill device MAC address registers */
349 for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++)
350 DM9000_iow(oft, dev->enetaddr[i]);
351 for (i = 0, oft = 0x16; i < 8; i++, oft++)
352 DM9000_iow(oft, 0xff);
353
354 /* read back mac, just to be sure */
355 for (i = 0, oft = 0x10; i < 6; i++, oft++)
356 DM9000_DBG("%02x:", DM9000_ior(oft));
357 DM9000_DBG("\n");
358
359 /* Activate DM9000 */
360 /* RX enable */
361 DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN);
362 /* Enable TX/RX interrupt mask */
363 DM9000_iow(DM9000_IMR, IMR_PAR);
364
365 i = 0;
366 while (!(dm9000_phy_read(1) & 0x20)) { /* autonegation complete bit */
367 udelay(1000);
368 i++;
369 if (i == 10000) {
370 printf("could not establish link\n");
371 return 0;
372 }
373 }
374
375 /* see what we've got */
376 lnk = dm9000_phy_read(17) >> 12;
377 printf("operating at ");
378 switch (lnk) {
379 case 1:
380 printf("10M half duplex ");
381 break;
382 case 2:
383 printf("10M full duplex ");
384 break;
385 case 4:
386 printf("100M half duplex ");
387 break;
388 case 8:
389 printf("100M full duplex ");
390 break;
391 default:
392 printf("unknown: %d ", lnk);
393 break;
394 }
395 printf("mode\n");
396 return 0;
397 }
398
399 /*
400 Hardware start transmission.
401 Send a packet to media from the upper layer.
402 */
dm9000_send(struct eth_device * netdev,void * packet,int length)403 static int dm9000_send(struct eth_device *netdev, void *packet, int length)
404 {
405 int tmo;
406 struct board_info *db = &dm9000_info;
407
408 DM9000_DMP_PACKET(__func__ , packet, length);
409
410 DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */
411
412 /* Move data to DM9000 TX RAM */
413 DM9000_outb(DM9000_MWCMD, DM9000_IO); /* Prepare for TX-data */
414
415 /* push the data to the TX-fifo */
416 (db->outblk)(packet, length);
417
418 /* Set TX length to DM9000 */
419 DM9000_iow(DM9000_TXPLL, length & 0xff);
420 DM9000_iow(DM9000_TXPLH, (length >> 8) & 0xff);
421
422 /* Issue TX polling command */
423 DM9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
424
425 /* wait for end of transmission */
426 tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
427 while ( !(DM9000_ior(DM9000_NSR) & (NSR_TX1END | NSR_TX2END)) ||
428 !(DM9000_ior(DM9000_ISR) & IMR_PTM) ) {
429 if (get_timer(0) >= tmo) {
430 printf("transmission timeout\n");
431 break;
432 }
433 }
434 DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */
435
436 DM9000_DBG("transmit done\n\n");
437 return 0;
438 }
439
440 /*
441 Stop the interface.
442 The interface is stopped when it is brought.
443 */
dm9000_halt(struct eth_device * netdev)444 static void dm9000_halt(struct eth_device *netdev)
445 {
446 DM9000_DBG("%s\n", __func__);
447
448 /* RESET devie */
449 dm9000_phy_write(0, 0x8000); /* PHY RESET */
450 DM9000_iow(DM9000_GPR, 0x01); /* Power-Down PHY */
451 DM9000_iow(DM9000_IMR, 0x80); /* Disable all interrupt */
452 DM9000_iow(DM9000_RCR, 0x00); /* Disable RX */
453 }
454
455 /*
456 Received a packet and pass to upper layer
457 */
dm9000_rx(struct eth_device * netdev)458 static int dm9000_rx(struct eth_device *netdev)
459 {
460 u8 rxbyte;
461 u8 *rdptr = (u8 *)net_rx_packets[0];
462 u16 RxStatus, RxLen = 0;
463 struct board_info *db = &dm9000_info;
464
465 /* Check packet ready or not, we must check
466 the ISR status first for DM9000A */
467 if (!(DM9000_ior(DM9000_ISR) & 0x01)) /* Rx-ISR bit must be set. */
468 return 0;
469
470 DM9000_iow(DM9000_ISR, 0x01); /* clear PR status latched in bit 0 */
471
472 /* There is _at least_ 1 package in the fifo, read them all */
473 for (;;) {
474 DM9000_ior(DM9000_MRCMDX); /* Dummy read */
475
476 /* Get most updated data,
477 only look at bits 0:1, See application notes DM9000 */
478 rxbyte = DM9000_inb(DM9000_DATA) & 0x03;
479
480 /* Status check: this byte must be 0 or 1 */
481 if (rxbyte > DM9000_PKT_RDY) {
482 DM9000_iow(DM9000_RCR, 0x00); /* Stop Device */
483 DM9000_iow(DM9000_ISR, 0x80); /* Stop INT request */
484 printf("DM9000 error: status check fail: 0x%x\n",
485 rxbyte);
486 return 0;
487 }
488
489 if (rxbyte != DM9000_PKT_RDY)
490 return 0; /* No packet received, ignore */
491
492 DM9000_DBG("receiving packet\n");
493
494 /* A packet ready now & Get status/length */
495 (db->rx_status)(&RxStatus, &RxLen);
496
497 DM9000_DBG("rx status: 0x%04x rx len: %d\n", RxStatus, RxLen);
498
499 /* Move data from DM9000 */
500 /* Read received packet from RX SRAM */
501 (db->inblk)(rdptr, RxLen);
502
503 if ((RxStatus & 0xbf00) || (RxLen < 0x40)
504 || (RxLen > DM9000_PKT_MAX)) {
505 if (RxStatus & 0x100) {
506 printf("rx fifo error\n");
507 }
508 if (RxStatus & 0x200) {
509 printf("rx crc error\n");
510 }
511 if (RxStatus & 0x8000) {
512 printf("rx length error\n");
513 }
514 if (RxLen > DM9000_PKT_MAX) {
515 printf("rx length too big\n");
516 dm9000_reset();
517 }
518 } else {
519 DM9000_DMP_PACKET(__func__ , rdptr, RxLen);
520
521 DM9000_DBG("passing packet to upper layer\n");
522 net_process_received_packet(net_rx_packets[0], RxLen);
523 }
524 }
525 return 0;
526 }
527
528 /*
529 Read a word data from SROM
530 */
531 #if !defined(CONFIG_DM9000_NO_SROM)
dm9000_read_srom_word(int offset,u8 * to)532 void dm9000_read_srom_word(int offset, u8 *to)
533 {
534 DM9000_iow(DM9000_EPAR, offset);
535 DM9000_iow(DM9000_EPCR, 0x4);
536 udelay(8000);
537 DM9000_iow(DM9000_EPCR, 0x0);
538 to[0] = DM9000_ior(DM9000_EPDRL);
539 to[1] = DM9000_ior(DM9000_EPDRH);
540 }
541
dm9000_write_srom_word(int offset,u16 val)542 void dm9000_write_srom_word(int offset, u16 val)
543 {
544 DM9000_iow(DM9000_EPAR, offset);
545 DM9000_iow(DM9000_EPDRH, ((val >> 8) & 0xff));
546 DM9000_iow(DM9000_EPDRL, (val & 0xff));
547 DM9000_iow(DM9000_EPCR, 0x12);
548 udelay(8000);
549 DM9000_iow(DM9000_EPCR, 0);
550 }
551 #endif
552
dm9000_get_enetaddr(struct eth_device * dev)553 static void dm9000_get_enetaddr(struct eth_device *dev)
554 {
555 #if !defined(CONFIG_DM9000_NO_SROM)
556 int i;
557 for (i = 0; i < 3; i++)
558 dm9000_read_srom_word(i, dev->enetaddr + (2 * i));
559 #endif
560 }
561
562 /*
563 Read a byte from I/O port
564 */
565 static u8
DM9000_ior(int reg)566 DM9000_ior(int reg)
567 {
568 DM9000_outb(reg, DM9000_IO);
569 return DM9000_inb(DM9000_DATA);
570 }
571
572 /*
573 Write a byte to I/O port
574 */
575 static void
DM9000_iow(int reg,u8 value)576 DM9000_iow(int reg, u8 value)
577 {
578 DM9000_outb(reg, DM9000_IO);
579 DM9000_outb(value, DM9000_DATA);
580 }
581
582 /*
583 Read a word from phyxcer
584 */
585 static u16
dm9000_phy_read(int reg)586 dm9000_phy_read(int reg)
587 {
588 u16 val;
589
590 /* Fill the phyxcer register into REG_0C */
591 DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);
592 DM9000_iow(DM9000_EPCR, 0xc); /* Issue phyxcer read command */
593 udelay(100); /* Wait read complete */
594 DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer read command */
595 val = (DM9000_ior(DM9000_EPDRH) << 8) | DM9000_ior(DM9000_EPDRL);
596
597 /* The read data keeps on REG_0D & REG_0E */
598 DM9000_DBG("dm9000_phy_read(0x%x): 0x%x\n", reg, val);
599 return val;
600 }
601
602 /*
603 Write a word to phyxcer
604 */
605 static void
dm9000_phy_write(int reg,u16 value)606 dm9000_phy_write(int reg, u16 value)
607 {
608
609 /* Fill the phyxcer register into REG_0C */
610 DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);
611
612 /* Fill the written data into REG_0D & REG_0E */
613 DM9000_iow(DM9000_EPDRL, (value & 0xff));
614 DM9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff));
615 DM9000_iow(DM9000_EPCR, 0xa); /* Issue phyxcer write command */
616 udelay(500); /* Wait write complete */
617 DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer write command */
618 DM9000_DBG("dm9000_phy_write(reg:0x%x, value:0x%x)\n", reg, value);
619 }
620
dm9000_initialize(bd_t * bis)621 int dm9000_initialize(bd_t *bis)
622 {
623 struct eth_device *dev = &(dm9000_info.netdev);
624
625 /* Load MAC address from EEPROM */
626 dm9000_get_enetaddr(dev);
627
628 dev->init = dm9000_init;
629 dev->halt = dm9000_halt;
630 dev->send = dm9000_send;
631 dev->recv = dm9000_rx;
632 strcpy(dev->name, "dm9000");
633
634 eth_register(dev);
635
636 return 0;
637 }
638