1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2011 Michal Simek <monstr@monstr.eu>
4 * Copyright (C) 2011 PetaLogix
5 * Copyright (C) 2010 Xilinx, Inc. All rights reserved.
6 */
7
8 #include <config.h>
9 #include <common.h>
10 #include <dm.h>
11 #include <net.h>
12 #include <malloc.h>
13 #include <asm/io.h>
14 #include <phy.h>
15 #include <miiphy.h>
16 #include <wait_bit.h>
17
18 DECLARE_GLOBAL_DATA_PTR;
19
20 /* Link setup */
21 #define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */
22 #define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */
23 #define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */
24 #define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */
25
26 /* Interrupt Status/Enable/Mask Registers bit definitions */
27 #define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */
28 #define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */
29
30 /* Receive Configuration Word 1 (RCW1) Register bit definitions */
31 #define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */
32
33 /* Transmitter Configuration (TC) Register bit definitions */
34 #define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */
35
36 #define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF
37
38 /* MDIO Management Configuration (MC) Register bit definitions */
39 #define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable*/
40
41 /* MDIO Management Control Register (MCR) Register bit definitions */
42 #define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */
43 #define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */
44 #define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */
45 #define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */
46 #define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */
47 #define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */
48 #define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */
49 #define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */
50
51 #define XAE_MDIO_DIV_DFT 29 /* Default MDIO clock divisor */
52
53 #define XAXIDMA_BD_STS_ACTUAL_LEN_MASK 0x007FFFFF /* Actual len */
54
55 /* DMA macros */
56 /* Bitmasks of XAXIDMA_CR_OFFSET register */
57 #define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */
58 #define XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */
59
60 /* Bitmasks of XAXIDMA_SR_OFFSET register */
61 #define XAXIDMA_HALTED_MASK 0x00000001 /* DMA channel halted */
62
63 /* Bitmask for interrupts */
64 #define XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */
65 #define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */
66 #define XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */
67
68 /* Bitmasks of XAXIDMA_BD_CTRL_OFFSET register */
69 #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
70 #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
71
72 #define DMAALIGN 128
73
74 static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN)));
75
76 /* Reflect dma offsets */
77 struct axidma_reg {
78 u32 control; /* DMACR */
79 u32 status; /* DMASR */
80 u32 current; /* CURDESC low 32 bit */
81 u32 current_hi; /* CURDESC high 32 bit */
82 u32 tail; /* TAILDESC low 32 bit */
83 u32 tail_hi; /* TAILDESC high 32 bit */
84 };
85
86 /* Private driver structures */
87 struct axidma_priv {
88 struct axidma_reg *dmatx;
89 struct axidma_reg *dmarx;
90 int phyaddr;
91 struct axi_regs *iobase;
92 phy_interface_t interface;
93 struct phy_device *phydev;
94 struct mii_dev *bus;
95 u8 eth_hasnobuf;
96 };
97
98 /* BD descriptors */
99 struct axidma_bd {
100 u32 next; /* Next descriptor pointer */
101 u32 reserved1;
102 u32 phys; /* Buffer address */
103 u32 reserved2;
104 u32 reserved3;
105 u32 reserved4;
106 u32 cntrl; /* Control */
107 u32 status; /* Status */
108 u32 app0;
109 u32 app1; /* TX start << 16 | insert */
110 u32 app2; /* TX csum seed */
111 u32 app3;
112 u32 app4;
113 u32 sw_id_offset;
114 u32 reserved5;
115 u32 reserved6;
116 };
117
118 /* Static BDs - driver uses only one BD */
119 static struct axidma_bd tx_bd __attribute((aligned(DMAALIGN)));
120 static struct axidma_bd rx_bd __attribute((aligned(DMAALIGN)));
121
122 struct axi_regs {
123 u32 reserved[3];
124 u32 is; /* 0xC: Interrupt status */
125 u32 reserved2;
126 u32 ie; /* 0x14: Interrupt enable */
127 u32 reserved3[251];
128 u32 rcw1; /* 0x404: Rx Configuration Word 1 */
129 u32 tc; /* 0x408: Tx Configuration */
130 u32 reserved4;
131 u32 emmc; /* 0x410: EMAC mode configuration */
132 u32 reserved5[59];
133 u32 mdio_mc; /* 0x500: MII Management Config */
134 u32 mdio_mcr; /* 0x504: MII Management Control */
135 u32 mdio_mwd; /* 0x508: MII Management Write Data */
136 u32 mdio_mrd; /* 0x50C: MII Management Read Data */
137 u32 reserved6[124];
138 u32 uaw0; /* 0x700: Unicast address word 0 */
139 u32 uaw1; /* 0x704: Unicast address word 1 */
140 };
141
142 /* Use MII register 1 (MII status register) to detect PHY */
143 #define PHY_DETECT_REG 1
144
145 /*
146 * Mask used to verify certain PHY features (or register contents)
147 * in the register above:
148 * 0x1000: 10Mbps full duplex support
149 * 0x0800: 10Mbps half duplex support
150 * 0x0008: Auto-negotiation support
151 */
152 #define PHY_DETECT_MASK 0x1808
153
mdio_wait(struct axi_regs * regs)154 static inline int mdio_wait(struct axi_regs *regs)
155 {
156 u32 timeout = 200;
157
158 /* Wait till MDIO interface is ready to accept a new transaction. */
159 while (timeout && (!(readl(®s->mdio_mcr)
160 & XAE_MDIO_MCR_READY_MASK))) {
161 timeout--;
162 udelay(1);
163 }
164 if (!timeout) {
165 printf("%s: Timeout\n", __func__);
166 return 1;
167 }
168 return 0;
169 }
170
171 /**
172 * axienet_dma_write - Memory mapped Axi DMA register Buffer Descriptor write.
173 * @bd: pointer to BD descriptor structure
174 * @desc: Address offset of DMA descriptors
175 *
176 * This function writes the value into the corresponding Axi DMA register.
177 */
axienet_dma_write(struct axidma_bd * bd,u32 * desc)178 static inline void axienet_dma_write(struct axidma_bd *bd, u32 *desc)
179 {
180 #if defined(CONFIG_PHYS_64BIT)
181 writeq(bd, desc);
182 #else
183 writel((u32)bd, desc);
184 #endif
185 }
186
phyread(struct axidma_priv * priv,u32 phyaddress,u32 registernum,u16 * val)187 static u32 phyread(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
188 u16 *val)
189 {
190 struct axi_regs *regs = priv->iobase;
191 u32 mdioctrlreg = 0;
192
193 if (mdio_wait(regs))
194 return 1;
195
196 mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
197 XAE_MDIO_MCR_PHYAD_MASK) |
198 ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
199 & XAE_MDIO_MCR_REGAD_MASK) |
200 XAE_MDIO_MCR_INITIATE_MASK |
201 XAE_MDIO_MCR_OP_READ_MASK;
202
203 writel(mdioctrlreg, ®s->mdio_mcr);
204
205 if (mdio_wait(regs))
206 return 1;
207
208 /* Read data */
209 *val = readl(®s->mdio_mrd);
210 return 0;
211 }
212
phywrite(struct axidma_priv * priv,u32 phyaddress,u32 registernum,u32 data)213 static u32 phywrite(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
214 u32 data)
215 {
216 struct axi_regs *regs = priv->iobase;
217 u32 mdioctrlreg = 0;
218
219 if (mdio_wait(regs))
220 return 1;
221
222 mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
223 XAE_MDIO_MCR_PHYAD_MASK) |
224 ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
225 & XAE_MDIO_MCR_REGAD_MASK) |
226 XAE_MDIO_MCR_INITIATE_MASK |
227 XAE_MDIO_MCR_OP_WRITE_MASK;
228
229 /* Write data */
230 writel(data, ®s->mdio_mwd);
231
232 writel(mdioctrlreg, ®s->mdio_mcr);
233
234 if (mdio_wait(regs))
235 return 1;
236
237 return 0;
238 }
239
axiemac_phy_init(struct udevice * dev)240 static int axiemac_phy_init(struct udevice *dev)
241 {
242 u16 phyreg;
243 u32 i, ret;
244 struct axidma_priv *priv = dev_get_priv(dev);
245 struct axi_regs *regs = priv->iobase;
246 struct phy_device *phydev;
247
248 u32 supported = SUPPORTED_10baseT_Half |
249 SUPPORTED_10baseT_Full |
250 SUPPORTED_100baseT_Half |
251 SUPPORTED_100baseT_Full |
252 SUPPORTED_1000baseT_Half |
253 SUPPORTED_1000baseT_Full;
254
255 /* Set default MDIO divisor */
256 writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, ®s->mdio_mc);
257
258 if (priv->phyaddr == -1) {
259 /* Detect the PHY address */
260 for (i = 31; i >= 0; i--) {
261 ret = phyread(priv, i, PHY_DETECT_REG, &phyreg);
262 if (!ret && (phyreg != 0xFFFF) &&
263 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
264 /* Found a valid PHY address */
265 priv->phyaddr = i;
266 debug("axiemac: Found valid phy address, %x\n",
267 i);
268 break;
269 }
270 }
271 }
272
273 /* Interface - look at tsec */
274 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
275
276 phydev->supported &= supported;
277 phydev->advertising = phydev->supported;
278 priv->phydev = phydev;
279 phy_config(phydev);
280
281 return 0;
282 }
283
284 /* Setting axi emac and phy to proper setting */
setup_phy(struct udevice * dev)285 static int setup_phy(struct udevice *dev)
286 {
287 u16 temp;
288 u32 speed, emmc_reg, ret;
289 struct axidma_priv *priv = dev_get_priv(dev);
290 struct axi_regs *regs = priv->iobase;
291 struct phy_device *phydev = priv->phydev;
292
293 if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
294 /*
295 * In SGMII cases the isolate bit might set
296 * after DMA and ethernet resets and hence
297 * check and clear if set.
298 */
299 ret = phyread(priv, priv->phyaddr, MII_BMCR, &temp);
300 if (ret)
301 return 0;
302 if (temp & BMCR_ISOLATE) {
303 temp &= ~BMCR_ISOLATE;
304 ret = phywrite(priv, priv->phyaddr, MII_BMCR, temp);
305 if (ret)
306 return 0;
307 }
308 }
309
310 if (phy_startup(phydev)) {
311 printf("axiemac: could not initialize PHY %s\n",
312 phydev->dev->name);
313 return 0;
314 }
315 if (!phydev->link) {
316 printf("%s: No link.\n", phydev->dev->name);
317 return 0;
318 }
319
320 switch (phydev->speed) {
321 case 1000:
322 speed = XAE_EMMC_LINKSPD_1000;
323 break;
324 case 100:
325 speed = XAE_EMMC_LINKSPD_100;
326 break;
327 case 10:
328 speed = XAE_EMMC_LINKSPD_10;
329 break;
330 default:
331 return 0;
332 }
333
334 /* Setup the emac for the phy speed */
335 emmc_reg = readl(®s->emmc);
336 emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
337 emmc_reg |= speed;
338
339 /* Write new speed setting out to Axi Ethernet */
340 writel(emmc_reg, ®s->emmc);
341
342 /*
343 * Setting the operating speed of the MAC needs a delay. There
344 * doesn't seem to be register to poll, so please consider this
345 * during your application design.
346 */
347 udelay(1);
348
349 return 1;
350 }
351
352 /* STOP DMA transfers */
axiemac_stop(struct udevice * dev)353 static void axiemac_stop(struct udevice *dev)
354 {
355 struct axidma_priv *priv = dev_get_priv(dev);
356 u32 temp;
357
358 /* Stop the hardware */
359 temp = readl(&priv->dmatx->control);
360 temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
361 writel(temp, &priv->dmatx->control);
362
363 temp = readl(&priv->dmarx->control);
364 temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
365 writel(temp, &priv->dmarx->control);
366
367 debug("axiemac: Halted\n");
368 }
369
axi_ethernet_init(struct axidma_priv * priv)370 static int axi_ethernet_init(struct axidma_priv *priv)
371 {
372 struct axi_regs *regs = priv->iobase;
373 int err;
374
375 /*
376 * Check the status of the MgtRdy bit in the interrupt status
377 * registers. This must be done to allow the MGT clock to become stable
378 * for the Sgmii and 1000BaseX PHY interfaces. No other register reads
379 * will be valid until this bit is valid.
380 * The bit is always a 1 for all other PHY interfaces.
381 * Interrupt status and enable registers are not available in non
382 * processor mode and hence bypass in this mode
383 */
384 if (!priv->eth_hasnobuf) {
385 err = wait_for_bit_le32(®s->is, XAE_INT_MGTRDY_MASK,
386 true, 200, false);
387 if (err) {
388 printf("%s: Timeout\n", __func__);
389 return 1;
390 }
391
392 /*
393 * Stop the device and reset HW
394 * Disable interrupts
395 */
396 writel(0, ®s->ie);
397 }
398
399 /* Disable the receiver */
400 writel(readl(®s->rcw1) & ~XAE_RCW1_RX_MASK, ®s->rcw1);
401
402 /*
403 * Stopping the receiver in mid-packet causes a dropped packet
404 * indication from HW. Clear it.
405 */
406 if (!priv->eth_hasnobuf) {
407 /* Set the interrupt status register to clear the interrupt */
408 writel(XAE_INT_RXRJECT_MASK, ®s->is);
409 }
410
411 /* Setup HW */
412 /* Set default MDIO divisor */
413 writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, ®s->mdio_mc);
414
415 debug("axiemac: InitHw done\n");
416 return 0;
417 }
418
axiemac_write_hwaddr(struct udevice * dev)419 static int axiemac_write_hwaddr(struct udevice *dev)
420 {
421 struct eth_pdata *pdata = dev_get_platdata(dev);
422 struct axidma_priv *priv = dev_get_priv(dev);
423 struct axi_regs *regs = priv->iobase;
424
425 /* Set the MAC address */
426 int val = ((pdata->enetaddr[3] << 24) | (pdata->enetaddr[2] << 16) |
427 (pdata->enetaddr[1] << 8) | (pdata->enetaddr[0]));
428 writel(val, ®s->uaw0);
429
430 val = (pdata->enetaddr[5] << 8) | pdata->enetaddr[4];
431 val |= readl(®s->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK;
432 writel(val, ®s->uaw1);
433 return 0;
434 }
435
436 /* Reset DMA engine */
axi_dma_init(struct axidma_priv * priv)437 static void axi_dma_init(struct axidma_priv *priv)
438 {
439 u32 timeout = 500;
440
441 /* Reset the engine so the hardware starts from a known state */
442 writel(XAXIDMA_CR_RESET_MASK, &priv->dmatx->control);
443 writel(XAXIDMA_CR_RESET_MASK, &priv->dmarx->control);
444
445 /* At the initialization time, hardware should finish reset quickly */
446 while (timeout--) {
447 /* Check transmit/receive channel */
448 /* Reset is done when the reset bit is low */
449 if (!((readl(&priv->dmatx->control) |
450 readl(&priv->dmarx->control))
451 & XAXIDMA_CR_RESET_MASK)) {
452 break;
453 }
454 }
455 if (!timeout)
456 printf("%s: Timeout\n", __func__);
457 }
458
axiemac_start(struct udevice * dev)459 static int axiemac_start(struct udevice *dev)
460 {
461 struct axidma_priv *priv = dev_get_priv(dev);
462 struct axi_regs *regs = priv->iobase;
463 u32 temp;
464
465 debug("axiemac: Init started\n");
466 /*
467 * Initialize AXIDMA engine. AXIDMA engine must be initialized before
468 * AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is
469 * reset, and since AXIDMA reset line is connected to AxiEthernet, this
470 * would ensure a reset of AxiEthernet.
471 */
472 axi_dma_init(priv);
473
474 /* Initialize AxiEthernet hardware. */
475 if (axi_ethernet_init(priv))
476 return -1;
477
478 /* Disable all RX interrupts before RxBD space setup */
479 temp = readl(&priv->dmarx->control);
480 temp &= ~XAXIDMA_IRQ_ALL_MASK;
481 writel(temp, &priv->dmarx->control);
482
483 /* Start DMA RX channel. Now it's ready to receive data.*/
484 axienet_dma_write(&rx_bd, &priv->dmarx->current);
485
486 /* Setup the BD. */
487 memset(&rx_bd, 0, sizeof(rx_bd));
488 rx_bd.next = (u32)&rx_bd;
489 rx_bd.phys = (u32)&rxframe;
490 rx_bd.cntrl = sizeof(rxframe);
491 /* Flush the last BD so DMA core could see the updates */
492 flush_cache((u32)&rx_bd, sizeof(rx_bd));
493
494 /* It is necessary to flush rxframe because if you don't do it
495 * then cache can contain uninitialized data */
496 flush_cache((u32)&rxframe, sizeof(rxframe));
497
498 /* Start the hardware */
499 temp = readl(&priv->dmarx->control);
500 temp |= XAXIDMA_CR_RUNSTOP_MASK;
501 writel(temp, &priv->dmarx->control);
502
503 /* Rx BD is ready - start */
504 axienet_dma_write(&rx_bd, &priv->dmarx->tail);
505
506 /* Enable TX */
507 writel(XAE_TC_TX_MASK, ®s->tc);
508 /* Enable RX */
509 writel(XAE_RCW1_RX_MASK, ®s->rcw1);
510
511 /* PHY setup */
512 if (!setup_phy(dev)) {
513 axiemac_stop(dev);
514 return -1;
515 }
516
517 debug("axiemac: Init complete\n");
518 return 0;
519 }
520
axiemac_send(struct udevice * dev,void * ptr,int len)521 static int axiemac_send(struct udevice *dev, void *ptr, int len)
522 {
523 struct axidma_priv *priv = dev_get_priv(dev);
524 u32 timeout;
525
526 if (len > PKTSIZE_ALIGN)
527 len = PKTSIZE_ALIGN;
528
529 /* Flush packet to main memory to be trasfered by DMA */
530 flush_cache((u32)ptr, len);
531
532 /* Setup Tx BD */
533 memset(&tx_bd, 0, sizeof(tx_bd));
534 /* At the end of the ring, link the last BD back to the top */
535 tx_bd.next = (u32)&tx_bd;
536 tx_bd.phys = (u32)ptr;
537 /* Save len */
538 tx_bd.cntrl = len | XAXIDMA_BD_CTRL_TXSOF_MASK |
539 XAXIDMA_BD_CTRL_TXEOF_MASK;
540
541 /* Flush the last BD so DMA core could see the updates */
542 flush_cache((u32)&tx_bd, sizeof(tx_bd));
543
544 if (readl(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) {
545 u32 temp;
546 axienet_dma_write(&tx_bd, &priv->dmatx->current);
547 /* Start the hardware */
548 temp = readl(&priv->dmatx->control);
549 temp |= XAXIDMA_CR_RUNSTOP_MASK;
550 writel(temp, &priv->dmatx->control);
551 }
552
553 /* Start transfer */
554 axienet_dma_write(&tx_bd, &priv->dmatx->tail);
555
556 /* Wait for transmission to complete */
557 debug("axiemac: Waiting for tx to be done\n");
558 timeout = 200;
559 while (timeout && (!(readl(&priv->dmatx->status) &
560 (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))) {
561 timeout--;
562 udelay(1);
563 }
564 if (!timeout) {
565 printf("%s: Timeout\n", __func__);
566 return 1;
567 }
568
569 debug("axiemac: Sending complete\n");
570 return 0;
571 }
572
isrxready(struct axidma_priv * priv)573 static int isrxready(struct axidma_priv *priv)
574 {
575 u32 status;
576
577 /* Read pending interrupts */
578 status = readl(&priv->dmarx->status);
579
580 /* Acknowledge pending interrupts */
581 writel(status & XAXIDMA_IRQ_ALL_MASK, &priv->dmarx->status);
582
583 /*
584 * If Reception done interrupt is asserted, call RX call back function
585 * to handle the processed BDs and then raise the according flag.
586 */
587 if ((status & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))
588 return 1;
589
590 return 0;
591 }
592
axiemac_recv(struct udevice * dev,int flags,uchar ** packetp)593 static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp)
594 {
595 u32 length;
596 struct axidma_priv *priv = dev_get_priv(dev);
597 u32 temp;
598
599 /* Wait for an incoming packet */
600 if (!isrxready(priv))
601 return -1;
602
603 debug("axiemac: RX data ready\n");
604
605 /* Disable IRQ for a moment till packet is handled */
606 temp = readl(&priv->dmarx->control);
607 temp &= ~XAXIDMA_IRQ_ALL_MASK;
608 writel(temp, &priv->dmarx->control);
609 if (!priv->eth_hasnobuf)
610 length = rx_bd.app4 & 0xFFFF; /* max length mask */
611 else
612 length = rx_bd.status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
613
614 #ifdef DEBUG
615 print_buffer(&rxframe, &rxframe[0], 1, length, 16);
616 #endif
617
618 *packetp = rxframe;
619 return length;
620 }
621
axiemac_free_pkt(struct udevice * dev,uchar * packet,int length)622 static int axiemac_free_pkt(struct udevice *dev, uchar *packet, int length)
623 {
624 struct axidma_priv *priv = dev_get_priv(dev);
625
626 #ifdef DEBUG
627 /* It is useful to clear buffer to be sure that it is consistent */
628 memset(rxframe, 0, sizeof(rxframe));
629 #endif
630 /* Setup RxBD */
631 /* Clear the whole buffer and setup it again - all flags are cleared */
632 memset(&rx_bd, 0, sizeof(rx_bd));
633 rx_bd.next = (u32)&rx_bd;
634 rx_bd.phys = (u32)&rxframe;
635 rx_bd.cntrl = sizeof(rxframe);
636
637 /* Write bd to HW */
638 flush_cache((u32)&rx_bd, sizeof(rx_bd));
639
640 /* It is necessary to flush rxframe because if you don't do it
641 * then cache will contain previous packet */
642 flush_cache((u32)&rxframe, sizeof(rxframe));
643
644 /* Rx BD is ready - start again */
645 axienet_dma_write(&rx_bd, &priv->dmarx->tail);
646
647 debug("axiemac: RX completed, framelength = %d\n", length);
648
649 return 0;
650 }
651
axiemac_miiphy_read(struct mii_dev * bus,int addr,int devad,int reg)652 static int axiemac_miiphy_read(struct mii_dev *bus, int addr,
653 int devad, int reg)
654 {
655 int ret;
656 u16 value;
657
658 ret = phyread(bus->priv, addr, reg, &value);
659 debug("axiemac: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg,
660 value, ret);
661 return value;
662 }
663
axiemac_miiphy_write(struct mii_dev * bus,int addr,int devad,int reg,u16 value)664 static int axiemac_miiphy_write(struct mii_dev *bus, int addr, int devad,
665 int reg, u16 value)
666 {
667 debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
668 return phywrite(bus->priv, addr, reg, value);
669 }
670
axi_emac_probe(struct udevice * dev)671 static int axi_emac_probe(struct udevice *dev)
672 {
673 struct axidma_priv *priv = dev_get_priv(dev);
674 int ret;
675
676 priv->bus = mdio_alloc();
677 priv->bus->read = axiemac_miiphy_read;
678 priv->bus->write = axiemac_miiphy_write;
679 priv->bus->priv = priv;
680
681 ret = mdio_register_seq(priv->bus, dev->seq);
682 if (ret)
683 return ret;
684
685 axiemac_phy_init(dev);
686
687 return 0;
688 }
689
axi_emac_remove(struct udevice * dev)690 static int axi_emac_remove(struct udevice *dev)
691 {
692 struct axidma_priv *priv = dev_get_priv(dev);
693
694 free(priv->phydev);
695 mdio_unregister(priv->bus);
696 mdio_free(priv->bus);
697
698 return 0;
699 }
700
701 static const struct eth_ops axi_emac_ops = {
702 .start = axiemac_start,
703 .send = axiemac_send,
704 .recv = axiemac_recv,
705 .free_pkt = axiemac_free_pkt,
706 .stop = axiemac_stop,
707 .write_hwaddr = axiemac_write_hwaddr,
708 };
709
axi_emac_ofdata_to_platdata(struct udevice * dev)710 static int axi_emac_ofdata_to_platdata(struct udevice *dev)
711 {
712 struct eth_pdata *pdata = dev_get_platdata(dev);
713 struct axidma_priv *priv = dev_get_priv(dev);
714 int node = dev_of_offset(dev);
715 int offset = 0;
716 const char *phy_mode;
717
718 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
719 priv->iobase = (struct axi_regs *)pdata->iobase;
720
721 offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
722 "axistream-connected");
723 if (offset <= 0) {
724 printf("%s: axistream is not found\n", __func__);
725 return -EINVAL;
726 }
727 priv->dmatx = (struct axidma_reg *)fdtdec_get_addr(gd->fdt_blob,
728 offset, "reg");
729 if (!priv->dmatx) {
730 printf("%s: axi_dma register space not found\n", __func__);
731 return -EINVAL;
732 }
733 /* RX channel offset is 0x30 */
734 priv->dmarx = (struct axidma_reg *)((u32)priv->dmatx + 0x30);
735
736 priv->phyaddr = -1;
737
738 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
739 if (offset > 0)
740 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
741
742 phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
743 if (phy_mode)
744 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
745 if (pdata->phy_interface == -1) {
746 printf("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
747 return -EINVAL;
748 }
749 priv->interface = pdata->phy_interface;
750
751 priv->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node,
752 "xlnx,eth-hasnobuf");
753
754 printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase,
755 priv->phyaddr, phy_string_for_interface(priv->interface));
756
757 return 0;
758 }
759
760 static const struct udevice_id axi_emac_ids[] = {
761 { .compatible = "xlnx,axi-ethernet-1.00.a" },
762 { }
763 };
764
765 U_BOOT_DRIVER(axi_emac) = {
766 .name = "axi_emac",
767 .id = UCLASS_ETH,
768 .of_match = axi_emac_ids,
769 .ofdata_to_platdata = axi_emac_ofdata_to_platdata,
770 .probe = axi_emac_probe,
771 .remove = axi_emac_remove,
772 .ops = &axi_emac_ops,
773 .priv_auto_alloc_size = sizeof(struct axidma_priv),
774 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
775 };
776