1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
4 */
5
6 #include <common.h>
7 #include <dm.h>
8 #include <errno.h>
9 #include <syscon.h>
10 #include <asm/io.h>
11 #include <asm/arch/grf_rk3399.h>
12 #include <asm/arch/hardware.h>
13 #include <asm/arch/periph.h>
14 #include <asm/arch/clock.h>
15 #include <dm/pinctrl.h>
16
17 struct rk3399_pinctrl_priv {
18 struct rk3399_grf_regs *grf;
19 struct rk3399_pmugrf_regs *pmugrf;
20 };
21
pinctrl_rk3399_pwm_config(struct rk3399_grf_regs * grf,struct rk3399_pmugrf_regs * pmugrf,int pwm_id)22 static void pinctrl_rk3399_pwm_config(struct rk3399_grf_regs *grf,
23 struct rk3399_pmugrf_regs *pmugrf, int pwm_id)
24 {
25 switch (pwm_id) {
26 case PERIPH_ID_PWM0:
27 rk_clrsetreg(&grf->gpio4c_iomux,
28 GRF_GPIO4C2_SEL_MASK,
29 GRF_PWM_0 << GRF_GPIO4C2_SEL_SHIFT);
30 break;
31 case PERIPH_ID_PWM1:
32 rk_clrsetreg(&grf->gpio4c_iomux,
33 GRF_GPIO4C6_SEL_MASK,
34 GRF_PWM_1 << GRF_GPIO4C6_SEL_SHIFT);
35 break;
36 case PERIPH_ID_PWM2:
37 rk_clrsetreg(&pmugrf->gpio1c_iomux,
38 PMUGRF_GPIO1C3_SEL_MASK,
39 PMUGRF_PWM_2 << PMUGRF_GPIO1C3_SEL_SHIFT);
40 break;
41 case PERIPH_ID_PWM3:
42 if (readl(&pmugrf->soc_con0) & (1 << 5))
43 rk_clrsetreg(&pmugrf->gpio1b_iomux,
44 PMUGRF_GPIO1B6_SEL_MASK,
45 PMUGRF_PWM_3B << PMUGRF_GPIO1B6_SEL_SHIFT);
46 else
47 rk_clrsetreg(&pmugrf->gpio0a_iomux,
48 PMUGRF_GPIO0A6_SEL_MASK,
49 PMUGRF_PWM_3A << PMUGRF_GPIO0A6_SEL_SHIFT);
50 break;
51 default:
52 debug("pwm id = %d iomux error!\n", pwm_id);
53 break;
54 }
55 }
56
pinctrl_rk3399_i2c_config(struct rk3399_grf_regs * grf,struct rk3399_pmugrf_regs * pmugrf,int i2c_id)57 static void pinctrl_rk3399_i2c_config(struct rk3399_grf_regs *grf,
58 struct rk3399_pmugrf_regs *pmugrf,
59 int i2c_id)
60 {
61 switch (i2c_id) {
62 case PERIPH_ID_I2C0:
63 rk_clrsetreg(&pmugrf->gpio1b_iomux,
64 PMUGRF_GPIO1B7_SEL_MASK,
65 PMUGRF_I2C0PMU_SDA << PMUGRF_GPIO1B7_SEL_SHIFT);
66 rk_clrsetreg(&pmugrf->gpio1c_iomux,
67 PMUGRF_GPIO1C0_SEL_MASK,
68 PMUGRF_I2C0PMU_SCL << PMUGRF_GPIO1C0_SEL_SHIFT);
69 break;
70
71 case PERIPH_ID_I2C1:
72 rk_clrsetreg(&grf->gpio4a_iomux,
73 GRF_GPIO4A1_SEL_MASK,
74 GRF_I2C1_SDA << GRF_GPIO4A1_SEL_SHIFT);
75 rk_clrsetreg(&grf->gpio4a_iomux,
76 GRF_GPIO4A2_SEL_MASK,
77 GRF_I2C1_SCL << GRF_GPIO4A2_SEL_SHIFT);
78 break;
79
80 case PERIPH_ID_I2C2:
81 rk_clrsetreg(&grf->gpio2a_iomux,
82 GRF_GPIO2A0_SEL_MASK,
83 GRF_I2C2_SDA << GRF_GPIO2A0_SEL_SHIFT);
84 rk_clrsetreg(&grf->gpio2a_iomux,
85 GRF_GPIO2A1_SEL_MASK,
86 GRF_I2C2_SCL << GRF_GPIO2A1_SEL_SHIFT);
87 break;
88 case PERIPH_ID_I2C3:
89 rk_clrsetreg(&grf->gpio4c_iomux,
90 GRF_GPIO4C0_SEL_MASK,
91 GRF_HDMII2C_SCL << GRF_GPIO4C0_SEL_SHIFT);
92 rk_clrsetreg(&grf->gpio4c_iomux,
93 GRF_GPIO4C1_SEL_MASK,
94 GRF_HDMII2C_SDA << GRF_GPIO4C1_SEL_SHIFT);
95 break;
96
97 case PERIPH_ID_I2C4:
98 rk_clrsetreg(&pmugrf->gpio1b_iomux,
99 PMUGRF_GPIO1B3_SEL_MASK,
100 PMUGRF_I2C4_SDA << PMUGRF_GPIO1B3_SEL_SHIFT);
101 rk_clrsetreg(&pmugrf->gpio1b_iomux,
102 PMUGRF_GPIO1B4_SEL_MASK,
103 PMUGRF_I2C4_SCL << PMUGRF_GPIO1B4_SEL_SHIFT);
104 break;
105
106 case PERIPH_ID_I2C7:
107 rk_clrsetreg(&grf->gpio2a_iomux,
108 GRF_GPIO2A7_SEL_MASK,
109 GRF_I2C7_SDA << GRF_GPIO2A7_SEL_SHIFT);
110 rk_clrsetreg(&grf->gpio2b_iomux,
111 GRF_GPIO2B0_SEL_MASK,
112 GRF_I2C7_SCL << GRF_GPIO2B0_SEL_SHIFT);
113 break;
114
115 case PERIPH_ID_I2C6:
116 rk_clrsetreg(&grf->gpio2b_iomux,
117 GRF_GPIO2B1_SEL_MASK,
118 GRF_I2C6_SDA << GRF_GPIO2B1_SEL_SHIFT);
119 rk_clrsetreg(&grf->gpio2b_iomux,
120 GRF_GPIO2B2_SEL_MASK,
121 GRF_I2C6_SDA << GRF_GPIO2B2_SEL_SHIFT);
122 break;
123
124 case PERIPH_ID_I2C8:
125 rk_clrsetreg(&pmugrf->gpio1c_iomux,
126 PMUGRF_GPIO1C4_SEL_MASK,
127 PMUGRF_I2C8PMU_SDA << PMUGRF_GPIO1C4_SEL_SHIFT);
128 rk_clrsetreg(&pmugrf->gpio1c_iomux,
129 PMUGRF_GPIO1C5_SEL_MASK,
130 PMUGRF_I2C8PMU_SCL << PMUGRF_GPIO1C5_SEL_SHIFT);
131 break;
132
133 case PERIPH_ID_I2C5:
134 default:
135 debug("i2c id = %d iomux error!\n", i2c_id);
136 break;
137 }
138 }
139
pinctrl_rk3399_lcdc_config(struct rk3399_grf_regs * grf,int lcd_id)140 static void pinctrl_rk3399_lcdc_config(struct rk3399_grf_regs *grf, int lcd_id)
141 {
142 switch (lcd_id) {
143 case PERIPH_ID_LCDC0:
144 break;
145 default:
146 debug("lcdc id = %d iomux error!\n", lcd_id);
147 break;
148 }
149 }
150
pinctrl_rk3399_spi_config(struct rk3399_grf_regs * grf,struct rk3399_pmugrf_regs * pmugrf,enum periph_id spi_id,int cs)151 static int pinctrl_rk3399_spi_config(struct rk3399_grf_regs *grf,
152 struct rk3399_pmugrf_regs *pmugrf,
153 enum periph_id spi_id, int cs)
154 {
155 switch (spi_id) {
156 case PERIPH_ID_SPI0:
157 switch (cs) {
158 case 0:
159 rk_clrsetreg(&grf->gpio3a_iomux,
160 GRF_GPIO3A7_SEL_MASK,
161 GRF_SPI0NORCODEC_CSN0
162 << GRF_GPIO3A7_SEL_SHIFT);
163 break;
164 case 1:
165 rk_clrsetreg(&grf->gpio3b_iomux,
166 GRF_GPIO3B0_SEL_MASK,
167 GRF_SPI0NORCODEC_CSN1
168 << GRF_GPIO3B0_SEL_SHIFT);
169 break;
170 default:
171 goto err;
172 }
173 rk_clrsetreg(&grf->gpio3a_iomux,
174 GRF_GPIO3A4_SEL_MASK | GRF_GPIO3A5_SEL_SHIFT
175 | GRF_GPIO3A6_SEL_SHIFT,
176 GRF_SPI0NORCODEC_RXD << GRF_GPIO3A4_SEL_SHIFT
177 | GRF_SPI0NORCODEC_RXD << GRF_GPIO3A5_SEL_SHIFT
178 | GRF_SPI0NORCODEC_RXD << GRF_GPIO3A6_SEL_SHIFT);
179 break;
180 case PERIPH_ID_SPI1:
181 if (cs != 0)
182 goto err;
183 rk_clrsetreg(&pmugrf->gpio1a_iomux,
184 PMUGRF_GPIO1A7_SEL_MASK,
185 PMUGRF_SPI1EC_RXD << PMUGRF_GPIO1A7_SEL_SHIFT);
186 rk_clrsetreg(&pmugrf->gpio1b_iomux,
187 PMUGRF_GPIO1B0_SEL_MASK | PMUGRF_GPIO1B1_SEL_MASK
188 | PMUGRF_GPIO1B2_SEL_MASK,
189 PMUGRF_SPI1EC_TXD << PMUGRF_GPIO1B0_SEL_SHIFT
190 | PMUGRF_SPI1EC_CLK << PMUGRF_GPIO1B1_SEL_SHIFT
191 | PMUGRF_SPI1EC_CSN0 << PMUGRF_GPIO1B2_SEL_SHIFT);
192 break;
193 case PERIPH_ID_SPI2:
194 if (cs != 0)
195 goto err;
196 rk_clrsetreg(&grf->gpio2b_iomux,
197 GRF_GPIO2B1_SEL_MASK | GRF_GPIO2B2_SEL_MASK
198 | GRF_GPIO2B3_SEL_MASK | GRF_GPIO2B4_SEL_MASK,
199 GRF_SPI2TPM_RXD << GRF_GPIO2B1_SEL_SHIFT
200 | GRF_SPI2TPM_TXD << GRF_GPIO2B2_SEL_SHIFT
201 | GRF_SPI2TPM_CLK << GRF_GPIO2B3_SEL_SHIFT
202 | GRF_SPI2TPM_CSN0 << GRF_GPIO2B4_SEL_SHIFT);
203 break;
204 case PERIPH_ID_SPI5:
205 if (cs != 0)
206 goto err;
207 rk_clrsetreg(&grf->gpio2c_iomux,
208 GRF_GPIO2C4_SEL_MASK | GRF_GPIO2C5_SEL_MASK
209 | GRF_GPIO2C6_SEL_MASK | GRF_GPIO2C7_SEL_MASK,
210 GRF_SPI5EXPPLUS_RXD << GRF_GPIO2C4_SEL_SHIFT
211 | GRF_SPI5EXPPLUS_TXD << GRF_GPIO2C5_SEL_SHIFT
212 | GRF_SPI5EXPPLUS_CLK << GRF_GPIO2C6_SEL_SHIFT
213 | GRF_SPI5EXPPLUS_CSN0 << GRF_GPIO2C7_SEL_SHIFT);
214 break;
215 default:
216 printf("%s: spi_id %d is not supported.\n", __func__, spi_id);
217 goto err;
218 }
219
220 return 0;
221 err:
222 debug("rkspi: periph%d cs=%d not supported", spi_id, cs);
223 return -ENOENT;
224 }
225
pinctrl_rk3399_uart_config(struct rk3399_grf_regs * grf,struct rk3399_pmugrf_regs * pmugrf,int uart_id)226 static void pinctrl_rk3399_uart_config(struct rk3399_grf_regs *grf,
227 struct rk3399_pmugrf_regs *pmugrf,
228 int uart_id)
229 {
230 switch (uart_id) {
231 case PERIPH_ID_UART2:
232 /* Using channel-C by default */
233 rk_clrsetreg(&grf->gpio4c_iomux,
234 GRF_GPIO4C3_SEL_MASK,
235 GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
236 rk_clrsetreg(&grf->gpio4c_iomux,
237 GRF_GPIO4C4_SEL_MASK,
238 GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
239 break;
240 case PERIPH_ID_UART0:
241 case PERIPH_ID_UART1:
242 case PERIPH_ID_UART3:
243 case PERIPH_ID_UART4:
244 default:
245 debug("uart id = %d iomux error!\n", uart_id);
246 break;
247 }
248 }
249
pinctrl_rk3399_sdmmc_config(struct rk3399_grf_regs * grf,int mmc_id)250 static void pinctrl_rk3399_sdmmc_config(struct rk3399_grf_regs *grf, int mmc_id)
251 {
252 switch (mmc_id) {
253 case PERIPH_ID_EMMC:
254 break;
255 case PERIPH_ID_SDCARD:
256 rk_clrsetreg(&grf->gpio4b_iomux,
257 GRF_GPIO4B0_SEL_MASK | GRF_GPIO4B1_SEL_MASK
258 | GRF_GPIO4B2_SEL_MASK | GRF_GPIO4B3_SEL_MASK
259 | GRF_GPIO4B4_SEL_MASK | GRF_GPIO4B5_SEL_MASK,
260 GRF_SDMMC_DATA0 << GRF_GPIO4B0_SEL_SHIFT
261 | GRF_SDMMC_DATA1 << GRF_GPIO4B1_SEL_SHIFT
262 | GRF_SDMMC_DATA2 << GRF_GPIO4B2_SEL_SHIFT
263 | GRF_SDMMC_DATA3 << GRF_GPIO4B3_SEL_SHIFT
264 | GRF_SDMMC_CLKOUT << GRF_GPIO4B4_SEL_SHIFT
265 | GRF_SDMMC_CMD << GRF_GPIO4B5_SEL_SHIFT);
266 break;
267 default:
268 debug("mmc id = %d iomux error!\n", mmc_id);
269 break;
270 }
271 }
272
273 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
pinctrl_rk3399_gmac_config(struct rk3399_grf_regs * grf,int mmc_id)274 static void pinctrl_rk3399_gmac_config(struct rk3399_grf_regs *grf, int mmc_id)
275 {
276 rk_clrsetreg(&grf->gpio3a_iomux,
277 GRF_GPIO3A0_SEL_MASK | GRF_GPIO3A1_SEL_MASK |
278 GRF_GPIO3A2_SEL_MASK | GRF_GPIO3A3_SEL_MASK |
279 GRF_GPIO3A4_SEL_MASK | GRF_GPIO3A5_SEL_MASK |
280 GRF_GPIO3A6_SEL_MASK | GRF_GPIO3A7_SEL_MASK,
281 GRF_MAC_TXD2 << GRF_GPIO3A0_SEL_SHIFT |
282 GRF_MAC_TXD3 << GRF_GPIO3A1_SEL_SHIFT |
283 GRF_MAC_RXD2 << GRF_GPIO3A2_SEL_SHIFT |
284 GRF_MAC_RXD3 << GRF_GPIO3A3_SEL_SHIFT |
285 GRF_MAC_TXD0 << GRF_GPIO3A4_SEL_SHIFT |
286 GRF_MAC_TXD1 << GRF_GPIO3A5_SEL_SHIFT |
287 GRF_MAC_RXD0 << GRF_GPIO3A6_SEL_SHIFT |
288 GRF_MAC_RXD1 << GRF_GPIO3A7_SEL_SHIFT);
289 rk_clrsetreg(&grf->gpio3b_iomux,
290 GRF_GPIO3B0_SEL_MASK | GRF_GPIO3B1_SEL_MASK |
291 GRF_GPIO3B3_SEL_MASK |
292 GRF_GPIO3B4_SEL_MASK | GRF_GPIO3B5_SEL_MASK |
293 GRF_GPIO3B6_SEL_MASK,
294 GRF_MAC_MDC << GRF_GPIO3B0_SEL_SHIFT |
295 GRF_MAC_RXDV << GRF_GPIO3B1_SEL_SHIFT |
296 GRF_MAC_CLK << GRF_GPIO3B3_SEL_SHIFT |
297 GRF_MAC_TXEN << GRF_GPIO3B4_SEL_SHIFT |
298 GRF_MAC_MDIO << GRF_GPIO3B5_SEL_SHIFT |
299 GRF_MAC_RXCLK << GRF_GPIO3B6_SEL_SHIFT);
300 rk_clrsetreg(&grf->gpio3c_iomux,
301 GRF_GPIO3C1_SEL_MASK,
302 GRF_MAC_TXCLK << GRF_GPIO3C1_SEL_SHIFT);
303
304 /* Set drive strength for GMAC tx io, value 3 means 13mA */
305 rk_clrsetreg(&grf->gpio3_e[0],
306 GRF_GPIO3A0_E_MASK | GRF_GPIO3A1_E_MASK |
307 GRF_GPIO3A4_E_MASK | GRF_GPIO3A5_E0_MASK,
308 3 << GRF_GPIO3A0_E_SHIFT |
309 3 << GRF_GPIO3A1_E_SHIFT |
310 3 << GRF_GPIO3A4_E_SHIFT |
311 1 << GRF_GPIO3A5_E0_SHIFT);
312 rk_clrsetreg(&grf->gpio3_e[1],
313 GRF_GPIO3A5_E12_MASK,
314 1 << GRF_GPIO3A5_E12_SHIFT);
315 rk_clrsetreg(&grf->gpio3_e[2],
316 GRF_GPIO3B4_E_MASK,
317 3 << GRF_GPIO3B4_E_SHIFT);
318 rk_clrsetreg(&grf->gpio3_e[4],
319 GRF_GPIO3C1_E_MASK,
320 3 << GRF_GPIO3C1_E_SHIFT);
321 }
322 #endif
323
324 #if !defined(CONFIG_SPL_BUILD)
pinctrl_rk3399_hdmi_config(struct rk3399_grf_regs * grf,int hdmi_id)325 static void pinctrl_rk3399_hdmi_config(struct rk3399_grf_regs *grf, int hdmi_id)
326 {
327 switch (hdmi_id) {
328 case PERIPH_ID_HDMI:
329 rk_clrsetreg(&grf->gpio4c_iomux,
330 GRF_GPIO4C0_SEL_MASK | GRF_GPIO4C1_SEL_MASK,
331 (GRF_HDMII2C_SCL << GRF_GPIO4C0_SEL_SHIFT) |
332 (GRF_HDMII2C_SDA << GRF_GPIO4C1_SEL_SHIFT));
333 break;
334 default:
335 debug("%s: hdmi_id = %d unsupported\n", __func__, hdmi_id);
336 break;
337 }
338 }
339 #endif
340
rk3399_pinctrl_request(struct udevice * dev,int func,int flags)341 static int rk3399_pinctrl_request(struct udevice *dev, int func, int flags)
342 {
343 struct rk3399_pinctrl_priv *priv = dev_get_priv(dev);
344
345 debug("%s: func=%x, flags=%x\n", __func__, func, flags);
346 switch (func) {
347 case PERIPH_ID_PWM0:
348 case PERIPH_ID_PWM1:
349 case PERIPH_ID_PWM2:
350 case PERIPH_ID_PWM3:
351 case PERIPH_ID_PWM4:
352 pinctrl_rk3399_pwm_config(priv->grf, priv->pmugrf, func);
353 break;
354 case PERIPH_ID_I2C0:
355 case PERIPH_ID_I2C1:
356 case PERIPH_ID_I2C2:
357 case PERIPH_ID_I2C3:
358 case PERIPH_ID_I2C4:
359 case PERIPH_ID_I2C5:
360 case PERIPH_ID_I2C6:
361 case PERIPH_ID_I2C7:
362 case PERIPH_ID_I2C8:
363 pinctrl_rk3399_i2c_config(priv->grf, priv->pmugrf, func);
364 break;
365 case PERIPH_ID_SPI0:
366 case PERIPH_ID_SPI1:
367 case PERIPH_ID_SPI2:
368 case PERIPH_ID_SPI3:
369 case PERIPH_ID_SPI4:
370 case PERIPH_ID_SPI5:
371 pinctrl_rk3399_spi_config(priv->grf, priv->pmugrf, func, flags);
372 break;
373 case PERIPH_ID_UART0:
374 case PERIPH_ID_UART1:
375 case PERIPH_ID_UART2:
376 case PERIPH_ID_UART3:
377 case PERIPH_ID_UART4:
378 pinctrl_rk3399_uart_config(priv->grf, priv->pmugrf, func);
379 break;
380 case PERIPH_ID_LCDC0:
381 case PERIPH_ID_LCDC1:
382 pinctrl_rk3399_lcdc_config(priv->grf, func);
383 break;
384 case PERIPH_ID_SDMMC0:
385 case PERIPH_ID_SDMMC1:
386 pinctrl_rk3399_sdmmc_config(priv->grf, func);
387 break;
388 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
389 case PERIPH_ID_GMAC:
390 pinctrl_rk3399_gmac_config(priv->grf, func);
391 break;
392 #endif
393 #if !defined(CONFIG_SPL_BUILD)
394 case PERIPH_ID_HDMI:
395 pinctrl_rk3399_hdmi_config(priv->grf, func);
396 break;
397 #endif
398 default:
399 return -EINVAL;
400 }
401
402 return 0;
403 }
404
rk3399_pinctrl_get_periph_id(struct udevice * dev,struct udevice * periph)405 static int rk3399_pinctrl_get_periph_id(struct udevice *dev,
406 struct udevice *periph)
407 {
408 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
409 u32 cell[3];
410 int ret;
411
412 ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
413 if (ret < 0)
414 return -EINVAL;
415
416 switch (cell[1]) {
417 case 68:
418 return PERIPH_ID_SPI0;
419 case 53:
420 return PERIPH_ID_SPI1;
421 case 52:
422 return PERIPH_ID_SPI2;
423 case 132:
424 return PERIPH_ID_SPI5;
425 case 57:
426 return PERIPH_ID_I2C0;
427 case 59: /* Note strange order */
428 return PERIPH_ID_I2C1;
429 case 35:
430 return PERIPH_ID_I2C2;
431 case 34:
432 return PERIPH_ID_I2C3;
433 case 56:
434 return PERIPH_ID_I2C4;
435 case 38:
436 return PERIPH_ID_I2C5;
437 case 37:
438 return PERIPH_ID_I2C6;
439 case 36:
440 return PERIPH_ID_I2C7;
441 case 58:
442 return PERIPH_ID_I2C8;
443 case 65:
444 return PERIPH_ID_SDMMC1;
445 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
446 case 12:
447 return PERIPH_ID_GMAC;
448 #endif
449 #if !defined(CONFIG_SPL_BUILD)
450 case 23:
451 return PERIPH_ID_HDMI;
452 #endif
453 }
454 #endif
455 return -ENOENT;
456 }
457
rk3399_pinctrl_set_state_simple(struct udevice * dev,struct udevice * periph)458 static int rk3399_pinctrl_set_state_simple(struct udevice *dev,
459 struct udevice *periph)
460 {
461 int func;
462
463 func = rk3399_pinctrl_get_periph_id(dev, periph);
464 if (func < 0)
465 return func;
466
467 return rk3399_pinctrl_request(dev, func, 0);
468 }
469
470 static struct pinctrl_ops rk3399_pinctrl_ops = {
471 .set_state_simple = rk3399_pinctrl_set_state_simple,
472 .request = rk3399_pinctrl_request,
473 .get_periph_id = rk3399_pinctrl_get_periph_id,
474 };
475
rk3399_pinctrl_probe(struct udevice * dev)476 static int rk3399_pinctrl_probe(struct udevice *dev)
477 {
478 struct rk3399_pinctrl_priv *priv = dev_get_priv(dev);
479 int ret = 0;
480
481 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
482 priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
483 debug("%s: grf=%p, pmugrf=%p\n", __func__, priv->grf, priv->pmugrf);
484
485 return ret;
486 }
487
488 static const struct udevice_id rk3399_pinctrl_ids[] = {
489 { .compatible = "rockchip,rk3399-pinctrl" },
490 { }
491 };
492
493 U_BOOT_DRIVER(pinctrl_rk3399) = {
494 .name = "rockchip_rk3399_pinctrl",
495 .id = UCLASS_PINCTRL,
496 .of_match = rk3399_pinctrl_ids,
497 .priv_auto_alloc_size = sizeof(struct rk3399_pinctrl_priv),
498 .ops = &rk3399_pinctrl_ops,
499 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
500 .bind = dm_scan_fdt_dev,
501 #endif
502 .probe = rk3399_pinctrl_probe,
503 };
504