1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2015 Broadcom Corporation. 4 */ 5 6 #include <config.h> 7 #include <common.h> 8 #include <asm/io.h> 9 #include <asm/arch/sysmap.h> 10 #include <asm/kona-common/clk.h> 11 12 #include "dwc2_udc_otg_priv.h" 13 #include "bcm_udc_otg.h" 14 otg_phy_init(struct dwc2_udc * dev)15void otg_phy_init(struct dwc2_udc *dev) 16 { 17 /* turn on the USB OTG clocks */ 18 clk_usb_otg_enable((void *)HSOTG_BASE_ADDR); 19 20 /* set Phy to driving mode */ 21 wfld_clear(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET, 22 HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK); 23 24 udelay(100); 25 26 /* clear Soft Disconnect */ 27 wfld_clear(HSOTG_BASE_ADDR + HSOTG_DCTL_OFFSET, 28 HSOTG_DCTL_SFTDISCON_MASK); 29 30 /* invoke Reset (active low) */ 31 wfld_clear(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET, 32 HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK); 33 34 /* Reset needs to be asserted for 2ms */ 35 udelay(2000); 36 37 /* release Reset */ 38 wfld_set(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET, 39 HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK, 40 HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK); 41 } 42 otg_phy_off(struct dwc2_udc * dev)43void otg_phy_off(struct dwc2_udc *dev) 44 { 45 /* Soft Disconnect */ 46 wfld_set(HSOTG_BASE_ADDR + HSOTG_DCTL_OFFSET, 47 HSOTG_DCTL_SFTDISCON_MASK, 48 HSOTG_DCTL_SFTDISCON_MASK); 49 50 /* set Phy to non-driving (reset) mode */ 51 wfld_set(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET, 52 HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK, 53 HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK); 54 } 55