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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
4  *
5  * Based on original Kirkwood support which is
6  * (C) Copyright 2009
7  * Marvell Semiconductor <www.marvell.com>
8  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
9  */
10 
11 #ifndef _CONFIG_EDMINIV2_H
12 #define _CONFIG_EDMINIV2_H
13 
14 /*
15  * SPL
16  */
17 
18 #define CONFIG_SPL_TEXT_BASE		0xffff0000
19 #define CONFIG_SPL_MAX_SIZE		0x0000fff0
20 #define CONFIG_SPL_STACK		0x00020000
21 #define CONFIG_SPL_BSS_START_ADDR	0x00020000
22 #define CONFIG_SPL_BSS_MAX_SIZE		0x0001ffff
23 #define CONFIG_SYS_SPL_MALLOC_START	0x00040000
24 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x0001ffff
25 #define CONFIG_SYS_UBOOT_BASE		0xfff90000
26 #define CONFIG_SYS_UBOOT_START		0x00800000
27 
28 /*
29  * High Level Configuration Options (easy to change)
30  */
31 
32 #define CONFIG_MARVELL		1
33 #define CONFIG_FEROCEON		1	/* CPU Core subversion */
34 #define CONFIG_88F5182		1	/* SOC Name */
35 
36 #include <asm/arch/orion5x.h>
37 /*
38  * CLKs configurations
39  */
40 
41 /*
42  * Board-specific values for Orion5x MPP low level init:
43  * - MPPs 12 to 15 are SATA LEDs (mode 5)
44  * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for
45  *   MPP16 to MPP19, mode 0 for others
46  */
47 
48 #define ORION5X_MPP0_7		0x00000003
49 #define ORION5X_MPP8_15		0x55550000
50 #define ORION5X_MPP16_23	0x00005555
51 
52 /*
53  * Board-specific values for Orion5x GPIO low level init:
54  * - GPIO3 is input (RTC interrupt)
55  * - GPIO16 is Power LED control (0 = on, 1 = off)
56  * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16)
57  * - GPIO18 is Power Button status (0 = Released, 1 = Pressed)
58  * - GPIO19 is SATA disk power toggle (toggles on 0-to-1)
59  * - GPIO22 is SATA disk power status ()
60  * - GPIO23 is supply status for SATA disk ()
61  * - GPIO24 is supply control for board (write 1 to power off)
62  * Last GPIO is 25, further bits are supposed to be 0.
63  * Enable mask has ones for INPUT, 0 for OUTPUT.
64  * Default is LED ON, board ON :)
65  */
66 
67 #define ORION5X_GPIO_OUT_ENABLE		0xfef4f0ca
68 #define ORION5X_GPIO_OUT_VALUE		0x00000000
69 #define ORION5X_GPIO_IN_POLARITY	0x000000d0
70 
71 /*
72  * NS16550 Configuration
73  */
74 
75 #define CONFIG_SYS_NS16550_SERIAL
76 #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
77 #define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_TCLK
78 #define CONFIG_SYS_NS16550_COM1		ORION5X_UART0_BASE
79 
80 /*
81  * Serial Port configuration
82  * The following definitions let you select what serial you want to use
83  * for your console driver.
84  */
85 
86 #define CONFIG_SYS_BAUDRATE_TABLE \
87 	{ 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 }
88 
89 /*
90  * FLASH configuration
91  */
92 
93 #define CONFIG_SYS_FLASH_CFI
94 #define CONFIG_FLASH_CFI_DRIVER
95 #define CONFIG_SYS_MAX_FLASH_BANKS	1  /* max num of flash banks       */
96 #define CONFIG_SYS_MAX_FLASH_SECT	11 /* max num of sects on one chip */
97 #define CONFIG_SYS_FLASH_BASE		0xfff80000
98 
99 /* auto boot */
100 
101 /*
102  * For booting Linux, the board info and command line data
103  * have to be in the first 8 MB of memory, since this is
104  * the maximum mapped by the Linux kernel during initialization.
105  */
106 #define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs  */
107 #define CONFIG_INITRD_TAG	1	/* enable INITRD tag */
108 #define CONFIG_SETUP_MEMORY_TAGS 1	/* enable memory tag */
109 
110 #define	CONFIG_SYS_CBSIZE	1024	/* Console I/O Buff Size */
111 /*
112  * Commands configuration
113  */
114 
115 /*
116  * Network
117  */
118 
119 #ifdef CONFIG_CMD_NET
120 #define CONFIG_MVGBE_PORTS	{1}		/* enable port 0 only */
121 #define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION	/* don't randomize MAC */
122 #define CONFIG_PHY_BASE_ADR	0x8
123 #define CONFIG_RESET_PHY_R	/* use reset_phy() to init mv8831116 PHY */
124 #define CONFIG_NETCONSOLE	/* include NetConsole support   */
125 #define	CONFIG_MII		/* expose smi ove miiphy interface */
126 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
127 #define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
128 #endif
129 
130 /*
131  * IDE
132  */
133 #ifdef CONFIG_IDE
134 #define __io
135 #define CONFIG_IDE_PREINIT
136 /* ED Mini V has an IDE-compatible SATA connector for port 1 */
137 #define CONFIG_MVSATA_IDE_USE_PORT1
138 /* Needs byte-swapping for ATA data register */
139 #define CONFIG_IDE_SWAP_IO
140 /* Data, registers and alternate blocks are at the same offset */
141 #define CONFIG_SYS_ATA_DATA_OFFSET	(0x0100)
142 #define CONFIG_SYS_ATA_REG_OFFSET	(0x0100)
143 #define CONFIG_SYS_ATA_ALT_OFFSET	(0x0100)
144 /* Each 8-bit ATA register is aligned to a 4-bytes address */
145 #define CONFIG_SYS_ATA_STRIDE		4
146 /* Controller supports 48-bits LBA addressing */
147 #define CONFIG_LBA48
148 /* A single bus, a single device */
149 #define CONFIG_SYS_IDE_MAXBUS		1
150 #define CONFIG_SYS_IDE_MAXDEVICE	1
151 /* ATA registers base is at SATA controller base */
152 #define CONFIG_SYS_ATA_BASE_ADDR	ORION5X_SATA_BASE
153 /* ATA bus 0 is orion5x port 1 on ED Mini V2 */
154 #define CONFIG_SYS_ATA_IDE0_OFFSET	ORION5X_SATA_PORT1_OFFSET
155 /* end of IDE defines */
156 #endif /* CMD_IDE */
157 
158 /*
159  * Common USB/EHCI configuration
160  */
161 #ifdef CONFIG_CMD_USB
162 #define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE
163 #endif /* CONFIG_CMD_USB */
164 
165 /*
166  * I2C related stuff
167  */
168 #ifdef CONFIG_CMD_I2C
169 #define CONFIG_SYS_I2C
170 #define CONFIG_SYS_I2C_MVTWSI
171 #define CONFIG_I2C_MVTWSI_BASE0		ORION5X_TWSI_BASE
172 #define CONFIG_SYS_I2C_SLAVE		0x0
173 #define CONFIG_SYS_I2C_SPEED		100000
174 #endif
175 
176 /*
177  *  Environment variables configurations
178  */
179 #define CONFIG_ENV_SECT_SIZE		0x2000	/* 16K */
180 #define CONFIG_ENV_SIZE			0x2000
181 #define CONFIG_ENV_OFFSET		0x4000	/* env starts here */
182 
183 /*
184  * Size of malloc() pool
185  */
186 #define CONFIG_SYS_MALLOC_LEN	(1024 * 256) /* 256kB for malloc() */
187 
188 /*
189  * Other required minimal configurations
190  */
191 #define CONFIG_ARCH_CPU_INIT		/* call arch_cpu_init() */
192 #define CONFIG_NR_DRAM_BANKS		1
193 
194 #define CONFIG_SYS_LOAD_ADDR		0x00800000
195 #define CONFIG_SYS_MEMTEST_START	0x00400000
196 #define CONFIG_SYS_MEMTEST_END		0x007fffff
197 #define CONFIG_SYS_RESET_ADDRESS	0xffff0000
198 
199 /* Enable command line editing */
200 
201 /* provide extensive help */
202 
203 /* additions for new relocation code, must be added to all boards */
204 #define CONFIG_SYS_SDRAM_BASE		0
205 #define CONFIG_SYS_INIT_SP_ADDR	\
206 	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
207 
208 #endif /* _CONFIG_EDMINIV2_H */
209