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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Configuation settings for the Hitachi Solution Engine 7750
4  *
5  * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6  */
7 
8 #ifndef __MS7750SE_H
9 #define __MS7750SE_H
10 
11 #define CONFIG_CPU_SH7750	1
12 /* #define CONFIG_CPU_SH7751	1 */
13 /* #define CONFIG_CPU_TYPE_R	1 */
14 #define __LITTLE_ENDIAN__	1
15 
16 #define CONFIG_DISPLAY_BOARDINFO
17 
18 /*
19  * Command line configuration.
20  */
21 #define CONFIG_CONS_SCIF1	1
22 
23 #define CONFIG_ENV_OVERWRITE	1
24 
25 /* SDRAM */
26 #define CONFIG_SYS_SDRAM_BASE		(0x8C000000)
27 #define CONFIG_SYS_SDRAM_SIZE		(64 * 1024 * 1024)
28 
29 #define CONFIG_SYS_PBSIZE		256
30 
31 #define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE)
32 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_TEXT_BASE - 0x100000)
33 
34 /* NOR Flash */
35 /* #define CONFIG_SYS_FLASH_BASE		(0xA1000000)*/
36 #define CONFIG_SYS_FLASH_BASE		(0xA0000000)
37 #define CONFIG_SYS_MAX_FLASH_BANKS	(1)	/* Max number of
38 					 * Flash memory banks
39 					 */
40 #define CONFIG_SYS_MAX_FLASH_SECT	142
41 #define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
42 
43 #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
44 #define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE)	/* Address of u-boot image in Flash */
45 #define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
46 #define CONFIG_SYS_MALLOC_LEN		(256 * 1024)		/* Size of DRAM reserved for malloc() use */
47 
48 #define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
49 #define CONFIG_SYS_RX_ETH_BUFFER	(8)
50 
51 #define CONFIG_SYS_FLASH_CFI
52 #define CONFIG_FLASH_CFI_DRIVER
53 #undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE
54 #undef  CONFIG_SYS_FLASH_QUIET_TEST
55 #define CONFIG_SYS_FLASH_EMPTY_INFO				/* print 'E' for empty sector on flinfo */
56 
57 #define CONFIG_ENV_SECT_SIZE	0x20000
58 #define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
59 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
60 #define CONFIG_SYS_FLASH_ERASE_TOUT	120000
61 #define CONFIG_SYS_FLASH_WRITE_TOUT	500
62 
63 /* Board Clock */
64 #define CONFIG_SYS_CLK_FREQ	33333333
65 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
66 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
67 #define CONFIG_SYS_TMU_CLK_DIV		4
68 
69 #endif /* __MS7750SE_H */
70