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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  *  Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
4  *                        Steven J. Hill <sjhill@realitydiluted.com>
5  *		          Thomas Gleixner <tglx@linutronix.de>
6  *
7  * Info:
8  *	Contains standard defines and IDs for NAND flash devices
9  *
10  * Changelog:
11  *	See git changelog.
12  */
13 #ifndef __LINUX_MTD_RAWNAND_H
14 #define __LINUX_MTD_RAWNAND_H
15 
16 #include <config.h>
17 
18 #include <linux/compat.h>
19 #include <linux/mtd/mtd.h>
20 #include <linux/mtd/flashchip.h>
21 #include <linux/mtd/bbm.h>
22 #include <asm/cache.h>
23 
24 struct mtd_info;
25 struct nand_chip;
26 struct nand_flash_dev;
27 struct device_node;
28 
29 /* Get the flash and manufacturer id and lookup if the type is supported. */
30 struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
31 					   struct nand_chip *chip,
32 					   int *maf_id, int *dev_id,
33 					   struct nand_flash_dev *type);
34 
35 /* Scan and identify a NAND device */
36 int nand_scan(struct mtd_info *mtd, int max_chips);
37 /*
38  * Separate phases of nand_scan(), allowing board driver to intervene
39  * and override command or ECC setup according to flash type.
40  */
41 int nand_scan_ident(struct mtd_info *mtd, int max_chips,
42 			   struct nand_flash_dev *table);
43 int nand_scan_tail(struct mtd_info *mtd);
44 
45 /* Free resources held by the NAND device */
46 void nand_release(struct mtd_info *mtd);
47 
48 /* Internal helper for board drivers which need to override command function */
49 void nand_wait_ready(struct mtd_info *mtd);
50 
51 /*
52  * This constant declares the max. oobsize / page, which
53  * is supported now. If you add a chip with bigger oobsize/page
54  * adjust this accordingly.
55  */
56 #define NAND_MAX_OOBSIZE       1664
57 #define NAND_MAX_PAGESIZE      16384
58 
59 /*
60  * Constants for hardware specific CLE/ALE/NCE function
61  *
62  * These are bits which can be or'ed to set/clear multiple
63  * bits in one go.
64  */
65 /* Select the chip by setting nCE to low */
66 #define NAND_NCE		0x01
67 /* Select the command latch by setting CLE to high */
68 #define NAND_CLE		0x02
69 /* Select the address latch by setting ALE to high */
70 #define NAND_ALE		0x04
71 
72 #define NAND_CTRL_CLE		(NAND_NCE | NAND_CLE)
73 #define NAND_CTRL_ALE		(NAND_NCE | NAND_ALE)
74 #define NAND_CTRL_CHANGE	0x80
75 
76 /*
77  * Standard NAND flash commands
78  */
79 #define NAND_CMD_READ0		0
80 #define NAND_CMD_READ1		1
81 #define NAND_CMD_RNDOUT		5
82 #define NAND_CMD_PAGEPROG	0x10
83 #define NAND_CMD_READOOB	0x50
84 #define NAND_CMD_ERASE1		0x60
85 #define NAND_CMD_STATUS		0x70
86 #define NAND_CMD_SEQIN		0x80
87 #define NAND_CMD_RNDIN		0x85
88 #define NAND_CMD_READID		0x90
89 #define NAND_CMD_ERASE2		0xd0
90 #define NAND_CMD_PARAM		0xec
91 #define NAND_CMD_GET_FEATURES	0xee
92 #define NAND_CMD_SET_FEATURES	0xef
93 #define NAND_CMD_RESET		0xff
94 
95 #define NAND_CMD_LOCK		0x2a
96 #define NAND_CMD_UNLOCK1	0x23
97 #define NAND_CMD_UNLOCK2	0x24
98 
99 /* Extended commands for large page devices */
100 #define NAND_CMD_READSTART	0x30
101 #define NAND_CMD_RNDOUTSTART	0xE0
102 #define NAND_CMD_CACHEDPROG	0x15
103 
104 /* Extended commands for AG-AND device */
105 /*
106  * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
107  *       there is no way to distinguish that from NAND_CMD_READ0
108  *       until the remaining sequence of commands has been completed
109  *       so add a high order bit and mask it off in the command.
110  */
111 #define NAND_CMD_DEPLETE1	0x100
112 #define NAND_CMD_DEPLETE2	0x38
113 #define NAND_CMD_STATUS_MULTI	0x71
114 #define NAND_CMD_STATUS_ERROR	0x72
115 /* multi-bank error status (banks 0-3) */
116 #define NAND_CMD_STATUS_ERROR0	0x73
117 #define NAND_CMD_STATUS_ERROR1	0x74
118 #define NAND_CMD_STATUS_ERROR2	0x75
119 #define NAND_CMD_STATUS_ERROR3	0x76
120 #define NAND_CMD_STATUS_RESET	0x7f
121 #define NAND_CMD_STATUS_CLEAR	0xff
122 
123 #define NAND_CMD_NONE		-1
124 
125 /* Status bits */
126 #define NAND_STATUS_FAIL	0x01
127 #define NAND_STATUS_FAIL_N1	0x02
128 #define NAND_STATUS_TRUE_READY	0x20
129 #define NAND_STATUS_READY	0x40
130 #define NAND_STATUS_WP		0x80
131 
132 #define NAND_DATA_IFACE_CHECK_ONLY	-1
133 
134 /*
135  * Constants for ECC_MODES
136  */
137 typedef enum {
138 	NAND_ECC_NONE,
139 	NAND_ECC_SOFT,
140 	NAND_ECC_HW,
141 	NAND_ECC_HW_SYNDROME,
142 	NAND_ECC_HW_OOB_FIRST,
143 	NAND_ECC_SOFT_BCH,
144 } nand_ecc_modes_t;
145 
146 /*
147  * Constants for Hardware ECC
148  */
149 /* Reset Hardware ECC for read */
150 #define NAND_ECC_READ		0
151 /* Reset Hardware ECC for write */
152 #define NAND_ECC_WRITE		1
153 /* Enable Hardware ECC before syndrome is read back from flash */
154 #define NAND_ECC_READSYN	2
155 
156 /*
157  * Enable generic NAND 'page erased' check. This check is only done when
158  * ecc.correct() returns -EBADMSG.
159  * Set this flag if your implementation does not fix bitflips in erased
160  * pages and you want to rely on the default implementation.
161  */
162 #define NAND_ECC_GENERIC_ERASED_CHECK	BIT(0)
163 #define NAND_ECC_MAXIMIZE		BIT(1)
164 /*
165  * If your controller already sends the required NAND commands when
166  * reading or writing a page, then the framework is not supposed to
167  * send READ0 and SEQIN/PAGEPROG respectively.
168  */
169 #define NAND_ECC_CUSTOM_PAGE_ACCESS	BIT(2)
170 
171 /* Bit mask for flags passed to do_nand_read_ecc */
172 #define NAND_GET_DEVICE		0x80
173 
174 
175 /*
176  * Option constants for bizarre disfunctionality and real
177  * features.
178  */
179 /* Buswidth is 16 bit */
180 #define NAND_BUSWIDTH_16	0x00000002
181 /* Device supports partial programming without padding */
182 #define NAND_NO_PADDING		0x00000004
183 /* Chip has cache program function */
184 #define NAND_CACHEPRG		0x00000008
185 /* Chip has copy back function */
186 #define NAND_COPYBACK		0x00000010
187 /*
188  * Chip requires ready check on read (for auto-incremented sequential read).
189  * True only for small page devices; large page devices do not support
190  * autoincrement.
191  */
192 #define NAND_NEED_READRDY	0x00000100
193 
194 /* Chip does not allow subpage writes */
195 #define NAND_NO_SUBPAGE_WRITE	0x00000200
196 
197 /* Device is one of 'new' xD cards that expose fake nand command set */
198 #define NAND_BROKEN_XD		0x00000400
199 
200 /* Device behaves just like nand, but is readonly */
201 #define NAND_ROM		0x00000800
202 
203 /* Device supports subpage reads */
204 #define NAND_SUBPAGE_READ	0x00001000
205 
206 /*
207  * Some MLC NANDs need data scrambling to limit bitflips caused by repeated
208  * patterns.
209  */
210 #define NAND_NEED_SCRAMBLING	0x00002000
211 
212 /* Device needs 3rd row address cycle */
213 #define NAND_ROW_ADDR_3		0x00004000
214 
215 /* Options valid for Samsung large page devices */
216 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
217 
218 /* Macros to identify the above */
219 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
220 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
221 #define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE)
222 
223 /* Non chip related options */
224 /* This option skips the bbt scan during initialization. */
225 #define NAND_SKIP_BBTSCAN	0x00010000
226 /*
227  * This option is defined if the board driver allocates its own buffers
228  * (e.g. because it needs them DMA-coherent).
229  */
230 #define NAND_OWN_BUFFERS	0x00020000
231 /* Chip may not exist, so silence any errors in scan */
232 #define NAND_SCAN_SILENT_NODEV	0x00040000
233 /*
234  * Autodetect nand buswidth with readid/onfi.
235  * This suppose the driver will configure the hardware in 8 bits mode
236  * when calling nand_scan_ident, and update its configuration
237  * before calling nand_scan_tail.
238  */
239 #define NAND_BUSWIDTH_AUTO      0x00080000
240 /*
241  * This option could be defined by controller drivers to protect against
242  * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
243  */
244 #define NAND_USE_BOUNCE_BUFFER	0x00100000
245 
246 /* Options set by nand scan */
247 /* bbt has already been read */
248 #define NAND_BBT_SCANNED	0x40000000
249 /* Nand scan has allocated controller struct */
250 #define NAND_CONTROLLER_ALLOC	0x80000000
251 
252 /* Cell info constants */
253 #define NAND_CI_CHIPNR_MSK	0x03
254 #define NAND_CI_CELLTYPE_MSK	0x0C
255 #define NAND_CI_CELLTYPE_SHIFT	2
256 
257 /* ONFI features */
258 #define ONFI_FEATURE_16_BIT_BUS		(1 << 0)
259 #define ONFI_FEATURE_EXT_PARAM_PAGE	(1 << 7)
260 
261 /* ONFI timing mode, used in both asynchronous and synchronous mode */
262 #define ONFI_TIMING_MODE_0		(1 << 0)
263 #define ONFI_TIMING_MODE_1		(1 << 1)
264 #define ONFI_TIMING_MODE_2		(1 << 2)
265 #define ONFI_TIMING_MODE_3		(1 << 3)
266 #define ONFI_TIMING_MODE_4		(1 << 4)
267 #define ONFI_TIMING_MODE_5		(1 << 5)
268 #define ONFI_TIMING_MODE_UNKNOWN	(1 << 6)
269 
270 /* ONFI feature address */
271 #define ONFI_FEATURE_ADDR_TIMING_MODE	0x1
272 
273 /* Vendor-specific feature address (Micron) */
274 #define ONFI_FEATURE_ADDR_READ_RETRY	0x89
275 
276 /* ONFI subfeature parameters length */
277 #define ONFI_SUBFEATURE_PARAM_LEN	4
278 
279 /* ONFI optional commands SET/GET FEATURES supported? */
280 #define ONFI_OPT_CMD_SET_GET_FEATURES	(1 << 2)
281 
282 struct nand_onfi_params {
283 	/* rev info and features block */
284 	/* 'O' 'N' 'F' 'I'  */
285 	u8 sig[4];
286 	__le16 revision;
287 	__le16 features;
288 	__le16 opt_cmd;
289 	u8 reserved0[2];
290 	__le16 ext_param_page_length; /* since ONFI 2.1 */
291 	u8 num_of_param_pages;        /* since ONFI 2.1 */
292 	u8 reserved1[17];
293 
294 	/* manufacturer information block */
295 	char manufacturer[12];
296 	char model[20];
297 	u8 jedec_id;
298 	__le16 date_code;
299 	u8 reserved2[13];
300 
301 	/* memory organization block */
302 	__le32 byte_per_page;
303 	__le16 spare_bytes_per_page;
304 	__le32 data_bytes_per_ppage;
305 	__le16 spare_bytes_per_ppage;
306 	__le32 pages_per_block;
307 	__le32 blocks_per_lun;
308 	u8 lun_count;
309 	u8 addr_cycles;
310 	u8 bits_per_cell;
311 	__le16 bb_per_lun;
312 	__le16 block_endurance;
313 	u8 guaranteed_good_blocks;
314 	__le16 guaranteed_block_endurance;
315 	u8 programs_per_page;
316 	u8 ppage_attr;
317 	u8 ecc_bits;
318 	u8 interleaved_bits;
319 	u8 interleaved_ops;
320 	u8 reserved3[13];
321 
322 	/* electrical parameter block */
323 	u8 io_pin_capacitance_max;
324 	__le16 async_timing_mode;
325 	__le16 program_cache_timing_mode;
326 	__le16 t_prog;
327 	__le16 t_bers;
328 	__le16 t_r;
329 	__le16 t_ccs;
330 	__le16 src_sync_timing_mode;
331 	u8 src_ssync_features;
332 	__le16 clk_pin_capacitance_typ;
333 	__le16 io_pin_capacitance_typ;
334 	__le16 input_pin_capacitance_typ;
335 	u8 input_pin_capacitance_max;
336 	u8 driver_strength_support;
337 	__le16 t_int_r;
338 	__le16 t_adl;
339 	u8 reserved4[8];
340 
341 	/* vendor */
342 	__le16 vendor_revision;
343 	u8 vendor[88];
344 
345 	__le16 crc;
346 } __packed;
347 
348 #define ONFI_CRC_BASE	0x4F4E
349 
350 /* Extended ECC information Block Definition (since ONFI 2.1) */
351 struct onfi_ext_ecc_info {
352 	u8 ecc_bits;
353 	u8 codeword_size;
354 	__le16 bb_per_lun;
355 	__le16 block_endurance;
356 	u8 reserved[2];
357 } __packed;
358 
359 #define ONFI_SECTION_TYPE_0	0	/* Unused section. */
360 #define ONFI_SECTION_TYPE_1	1	/* for additional sections. */
361 #define ONFI_SECTION_TYPE_2	2	/* for ECC information. */
362 struct onfi_ext_section {
363 	u8 type;
364 	u8 length;
365 } __packed;
366 
367 #define ONFI_EXT_SECTION_MAX 8
368 
369 /* Extended Parameter Page Definition (since ONFI 2.1) */
370 struct onfi_ext_param_page {
371 	__le16 crc;
372 	u8 sig[4];             /* 'E' 'P' 'P' 'S' */
373 	u8 reserved0[10];
374 	struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
375 
376 	/*
377 	 * The actual size of the Extended Parameter Page is in
378 	 * @ext_param_page_length of nand_onfi_params{}.
379 	 * The following are the variable length sections.
380 	 * So we do not add any fields below. Please see the ONFI spec.
381 	 */
382 } __packed;
383 
384 struct nand_onfi_vendor_micron {
385 	u8 two_plane_read;
386 	u8 read_cache;
387 	u8 read_unique_id;
388 	u8 dq_imped;
389 	u8 dq_imped_num_settings;
390 	u8 dq_imped_feat_addr;
391 	u8 rb_pulldown_strength;
392 	u8 rb_pulldown_strength_feat_addr;
393 	u8 rb_pulldown_strength_num_settings;
394 	u8 otp_mode;
395 	u8 otp_page_start;
396 	u8 otp_data_prot_addr;
397 	u8 otp_num_pages;
398 	u8 otp_feat_addr;
399 	u8 read_retry_options;
400 	u8 reserved[72];
401 	u8 param_revision;
402 } __packed;
403 
404 struct jedec_ecc_info {
405 	u8 ecc_bits;
406 	u8 codeword_size;
407 	__le16 bb_per_lun;
408 	__le16 block_endurance;
409 	u8 reserved[2];
410 } __packed;
411 
412 /* JEDEC features */
413 #define JEDEC_FEATURE_16_BIT_BUS	(1 << 0)
414 
415 struct nand_jedec_params {
416 	/* rev info and features block */
417 	/* 'J' 'E' 'S' 'D'  */
418 	u8 sig[4];
419 	__le16 revision;
420 	__le16 features;
421 	u8 opt_cmd[3];
422 	__le16 sec_cmd;
423 	u8 num_of_param_pages;
424 	u8 reserved0[18];
425 
426 	/* manufacturer information block */
427 	char manufacturer[12];
428 	char model[20];
429 	u8 jedec_id[6];
430 	u8 reserved1[10];
431 
432 	/* memory organization block */
433 	__le32 byte_per_page;
434 	__le16 spare_bytes_per_page;
435 	u8 reserved2[6];
436 	__le32 pages_per_block;
437 	__le32 blocks_per_lun;
438 	u8 lun_count;
439 	u8 addr_cycles;
440 	u8 bits_per_cell;
441 	u8 programs_per_page;
442 	u8 multi_plane_addr;
443 	u8 multi_plane_op_attr;
444 	u8 reserved3[38];
445 
446 	/* electrical parameter block */
447 	__le16 async_sdr_speed_grade;
448 	__le16 toggle_ddr_speed_grade;
449 	__le16 sync_ddr_speed_grade;
450 	u8 async_sdr_features;
451 	u8 toggle_ddr_features;
452 	u8 sync_ddr_features;
453 	__le16 t_prog;
454 	__le16 t_bers;
455 	__le16 t_r;
456 	__le16 t_r_multi_plane;
457 	__le16 t_ccs;
458 	__le16 io_pin_capacitance_typ;
459 	__le16 input_pin_capacitance_typ;
460 	__le16 clk_pin_capacitance_typ;
461 	u8 driver_strength_support;
462 	__le16 t_adl;
463 	u8 reserved4[36];
464 
465 	/* ECC and endurance block */
466 	u8 guaranteed_good_blocks;
467 	__le16 guaranteed_block_endurance;
468 	struct jedec_ecc_info ecc_info[4];
469 	u8 reserved5[29];
470 
471 	/* reserved */
472 	u8 reserved6[148];
473 
474 	/* vendor */
475 	__le16 vendor_rev_num;
476 	u8 reserved7[88];
477 
478 	/* CRC for Parameter Page */
479 	__le16 crc;
480 } __packed;
481 
482 /**
483  * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
484  * @lock:               protection lock
485  * @active:		the mtd device which holds the controller currently
486  * @wq:			wait queue to sleep on if a NAND operation is in
487  *			progress used instead of the per chip wait queue
488  *			when a hw controller is available.
489  */
490 struct nand_hw_control {
491 	spinlock_t lock;
492 	struct nand_chip *active;
493 };
494 
495 /**
496  * struct nand_ecc_step_info - ECC step information of ECC engine
497  * @stepsize: data bytes per ECC step
498  * @strengths: array of supported strengths
499  * @nstrengths: number of supported strengths
500  */
501 struct nand_ecc_step_info {
502 	int stepsize;
503 	const int *strengths;
504 	int nstrengths;
505 };
506 
507 /**
508  * struct nand_ecc_caps - capability of ECC engine
509  * @stepinfos: array of ECC step information
510  * @nstepinfos: number of ECC step information
511  * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step
512  */
513 struct nand_ecc_caps {
514 	const struct nand_ecc_step_info *stepinfos;
515 	int nstepinfos;
516 	int (*calc_ecc_bytes)(int step_size, int strength);
517 };
518 
519 /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */
520 #define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...)	\
521 static const int __name##_strengths[] = { __VA_ARGS__ };	\
522 static const struct nand_ecc_step_info __name##_stepinfo = {	\
523 	.stepsize = __step,					\
524 	.strengths = __name##_strengths,			\
525 	.nstrengths = ARRAY_SIZE(__name##_strengths),		\
526 };								\
527 static const struct nand_ecc_caps __name = {			\
528 	.stepinfos = &__name##_stepinfo,			\
529 	.nstepinfos = 1,					\
530 	.calc_ecc_bytes = __calc,				\
531 }
532 
533 /**
534  * struct nand_ecc_ctrl - Control structure for ECC
535  * @mode:	ECC mode
536  * @steps:	number of ECC steps per page
537  * @size:	data bytes per ECC step
538  * @bytes:	ECC bytes per step
539  * @strength:	max number of correctible bits per ECC step
540  * @total:	total number of ECC bytes per page
541  * @prepad:	padding information for syndrome based ECC generators
542  * @postpad:	padding information for syndrome based ECC generators
543  * @options:	ECC specific options (see NAND_ECC_XXX flags defined above)
544  * @layout:	ECC layout control struct pointer
545  * @priv:	pointer to private ECC control data
546  * @hwctl:	function to control hardware ECC generator. Must only
547  *		be provided if an hardware ECC is available
548  * @calculate:	function for ECC calculation or readback from ECC hardware
549  * @correct:	function for ECC correction, matching to ECC generator (sw/hw).
550  *		Should return a positive number representing the number of
551  *		corrected bitflips, -EBADMSG if the number of bitflips exceed
552  *		ECC strength, or any other error code if the error is not
553  *		directly related to correction.
554  *		If -EBADMSG is returned the input buffers should be left
555  *		untouched.
556  * @read_page_raw:	function to read a raw page without ECC. This function
557  *			should hide the specific layout used by the ECC
558  *			controller and always return contiguous in-band and
559  *			out-of-band data even if they're not stored
560  *			contiguously on the NAND chip (e.g.
561  *			NAND_ECC_HW_SYNDROME interleaves in-band and
562  *			out-of-band data).
563  * @write_page_raw:	function to write a raw page without ECC. This function
564  *			should hide the specific layout used by the ECC
565  *			controller and consider the passed data as contiguous
566  *			in-band and out-of-band data. ECC controller is
567  *			responsible for doing the appropriate transformations
568  *			to adapt to its specific layout (e.g.
569  *			NAND_ECC_HW_SYNDROME interleaves in-band and
570  *			out-of-band data).
571  * @read_page:	function to read a page according to the ECC generator
572  *		requirements; returns maximum number of bitflips corrected in
573  *		any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
574  * @read_subpage:	function to read parts of the page covered by ECC;
575  *			returns same as read_page()
576  * @write_subpage:	function to write parts of the page covered by ECC.
577  * @write_page:	function to write a page according to the ECC generator
578  *		requirements.
579  * @write_oob_raw:	function to write chip OOB data without ECC
580  * @read_oob_raw:	function to read chip OOB data without ECC
581  * @read_oob:	function to read chip OOB data
582  * @write_oob:	function to write chip OOB data
583  */
584 struct nand_ecc_ctrl {
585 	nand_ecc_modes_t mode;
586 	int steps;
587 	int size;
588 	int bytes;
589 	int total;
590 	int strength;
591 	int prepad;
592 	int postpad;
593 	unsigned int options;
594 	struct nand_ecclayout	*layout;
595 	void *priv;
596 	void (*hwctl)(struct mtd_info *mtd, int mode);
597 	int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
598 			uint8_t *ecc_code);
599 	int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
600 			uint8_t *calc_ecc);
601 	int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
602 			uint8_t *buf, int oob_required, int page);
603 	int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
604 			const uint8_t *buf, int oob_required, int page);
605 	int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
606 			uint8_t *buf, int oob_required, int page);
607 	int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
608 			uint32_t offs, uint32_t len, uint8_t *buf, int page);
609 	int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
610 			uint32_t offset, uint32_t data_len,
611 			const uint8_t *data_buf, int oob_required, int page);
612 	int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
613 			const uint8_t *buf, int oob_required, int page);
614 	int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
615 			int page);
616 	int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
617 			int page);
618 	int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
619 	int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
620 			int page);
621 };
622 
nand_standard_page_accessors(struct nand_ecc_ctrl * ecc)623 static inline int nand_standard_page_accessors(struct nand_ecc_ctrl *ecc)
624 {
625 	return !(ecc->options & NAND_ECC_CUSTOM_PAGE_ACCESS);
626 }
627 
628 /**
629  * struct nand_buffers - buffer structure for read/write
630  * @ecccalc:	buffer pointer for calculated ECC, size is oobsize.
631  * @ecccode:	buffer pointer for ECC read from flash, size is oobsize.
632  * @databuf:	buffer pointer for data, size is (page size + oobsize).
633  *
634  * Do not change the order of buffers. databuf and oobrbuf must be in
635  * consecutive order.
636  */
637 struct nand_buffers {
638 	uint8_t	ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
639 	uint8_t	ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
640 	uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE,
641 			      ARCH_DMA_MINALIGN)];
642 };
643 
644 /**
645  * struct nand_sdr_timings - SDR NAND chip timings
646  *
647  * This struct defines the timing requirements of a SDR NAND chip.
648  * These information can be found in every NAND datasheets and the timings
649  * meaning are described in the ONFI specifications:
650  * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
651  * Parameters)
652  *
653  * All these timings are expressed in picoseconds.
654  *
655  * @tBERS_max: Block erase time
656  * @tCCS_min: Change column setup time
657  * @tPROG_max: Page program time
658  * @tR_max: Page read time
659  * @tALH_min: ALE hold time
660  * @tADL_min: ALE to data loading time
661  * @tALS_min: ALE setup time
662  * @tAR_min: ALE to RE# delay
663  * @tCEA_max: CE# access time
664  * @tCEH_min: CE# high hold time
665  * @tCH_min:  CE# hold time
666  * @tCHZ_max: CE# high to output hi-Z
667  * @tCLH_min: CLE hold time
668  * @tCLR_min: CLE to RE# delay
669  * @tCLS_min: CLE setup time
670  * @tCOH_min: CE# high to output hold
671  * @tCS_min: CE# setup time
672  * @tDH_min: Data hold time
673  * @tDS_min: Data setup time
674  * @tFEAT_max: Busy time for Set Features and Get Features
675  * @tIR_min: Output hi-Z to RE# low
676  * @tITC_max: Interface and Timing Mode Change time
677  * @tRC_min: RE# cycle time
678  * @tREA_max: RE# access time
679  * @tREH_min: RE# high hold time
680  * @tRHOH_min: RE# high to output hold
681  * @tRHW_min: RE# high to WE# low
682  * @tRHZ_max: RE# high to output hi-Z
683  * @tRLOH_min: RE# low to output hold
684  * @tRP_min: RE# pulse width
685  * @tRR_min: Ready to RE# low (data only)
686  * @tRST_max: Device reset time, measured from the falling edge of R/B# to the
687  *	      rising edge of R/B#.
688  * @tWB_max: WE# high to SR[6] low
689  * @tWC_min: WE# cycle time
690  * @tWH_min: WE# high hold time
691  * @tWHR_min: WE# high to RE# low
692  * @tWP_min: WE# pulse width
693  * @tWW_min: WP# transition to WE# low
694  */
695 struct nand_sdr_timings {
696 	u64 tBERS_max;
697 	u32 tCCS_min;
698 	u64 tPROG_max;
699 	u64 tR_max;
700 	u32 tALH_min;
701 	u32 tADL_min;
702 	u32 tALS_min;
703 	u32 tAR_min;
704 	u32 tCEA_max;
705 	u32 tCEH_min;
706 	u32 tCH_min;
707 	u32 tCHZ_max;
708 	u32 tCLH_min;
709 	u32 tCLR_min;
710 	u32 tCLS_min;
711 	u32 tCOH_min;
712 	u32 tCS_min;
713 	u32 tDH_min;
714 	u32 tDS_min;
715 	u32 tFEAT_max;
716 	u32 tIR_min;
717 	u32 tITC_max;
718 	u32 tRC_min;
719 	u32 tREA_max;
720 	u32 tREH_min;
721 	u32 tRHOH_min;
722 	u32 tRHW_min;
723 	u32 tRHZ_max;
724 	u32 tRLOH_min;
725 	u32 tRP_min;
726 	u32 tRR_min;
727 	u64 tRST_max;
728 	u32 tWB_max;
729 	u32 tWC_min;
730 	u32 tWH_min;
731 	u32 tWHR_min;
732 	u32 tWP_min;
733 	u32 tWW_min;
734 };
735 
736 /**
737  * enum nand_data_interface_type - NAND interface timing type
738  * @NAND_SDR_IFACE:	Single Data Rate interface
739  */
740 enum nand_data_interface_type {
741 	NAND_SDR_IFACE,
742 };
743 
744 /**
745  * struct nand_data_interface - NAND interface timing
746  * @type:	type of the timing
747  * @timings:	The timing, type according to @type
748  */
749 struct nand_data_interface {
750 	enum nand_data_interface_type type;
751 	union {
752 		struct nand_sdr_timings sdr;
753 	} timings;
754 };
755 
756 /**
757  * nand_get_sdr_timings - get SDR timing from data interface
758  * @conf:	The data interface
759  */
760 static inline const struct nand_sdr_timings *
nand_get_sdr_timings(const struct nand_data_interface * conf)761 nand_get_sdr_timings(const struct nand_data_interface *conf)
762 {
763 	if (conf->type != NAND_SDR_IFACE)
764 		return ERR_PTR(-EINVAL);
765 
766 	return &conf->timings.sdr;
767 }
768 
769 /**
770  * struct nand_chip - NAND Private Flash Chip Data
771  * @mtd:		MTD device registered to the MTD framework
772  * @IO_ADDR_R:		[BOARDSPECIFIC] address to read the 8 I/O lines of the
773  *			flash device
774  * @IO_ADDR_W:		[BOARDSPECIFIC] address to write the 8 I/O lines of the
775  *			flash device.
776  * @flash_node:		[BOARDSPECIFIC] device node describing this instance
777  * @read_byte:		[REPLACEABLE] read one byte from the chip
778  * @read_word:		[REPLACEABLE] read one word from the chip
779  * @write_byte:		[REPLACEABLE] write a single byte to the chip on the
780  *			low 8 I/O lines
781  * @write_buf:		[REPLACEABLE] write data from the buffer to the chip
782  * @read_buf:		[REPLACEABLE] read data from the chip into the buffer
783  * @select_chip:	[REPLACEABLE] select chip nr
784  * @block_bad:		[REPLACEABLE] check if a block is bad, using OOB markers
785  * @block_markbad:	[REPLACEABLE] mark a block bad
786  * @cmd_ctrl:		[BOARDSPECIFIC] hardwarespecific function for controlling
787  *			ALE/CLE/nCE. Also used to write command and address
788  * @dev_ready:		[BOARDSPECIFIC] hardwarespecific function for accessing
789  *			device ready/busy line. If set to NULL no access to
790  *			ready/busy is available and the ready/busy information
791  *			is read from the chip status register.
792  * @cmdfunc:		[REPLACEABLE] hardwarespecific function for writing
793  *			commands to the chip.
794  * @waitfunc:		[REPLACEABLE] hardwarespecific function for wait on
795  *			ready.
796  * @setup_read_retry:	[FLASHSPECIFIC] flash (vendor) specific function for
797  *			setting the read-retry mode. Mostly needed for MLC NAND.
798  * @ecc:		[BOARDSPECIFIC] ECC control structure
799  * @buffers:		buffer structure for read/write
800  * @buf_align:		minimum buffer alignment required by a platform
801  * @hwcontrol:		platform-specific hardware control structure
802  * @erase:		[REPLACEABLE] erase function
803  * @scan_bbt:		[REPLACEABLE] function to scan bad block table
804  * @chip_delay:		[BOARDSPECIFIC] chip dependent delay for transferring
805  *			data from array to read regs (tR).
806  * @state:		[INTERN] the current state of the NAND device
807  * @oob_poi:		"poison value buffer," used for laying out OOB data
808  *			before writing
809  * @page_shift:		[INTERN] number of address bits in a page (column
810  *			address bits).
811  * @phys_erase_shift:	[INTERN] number of address bits in a physical eraseblock
812  * @bbt_erase_shift:	[INTERN] number of address bits in a bbt entry
813  * @chip_shift:		[INTERN] number of address bits in one chip
814  * @options:		[BOARDSPECIFIC] various chip options. They can partly
815  *			be set to inform nand_scan about special functionality.
816  *			See the defines for further explanation.
817  * @bbt_options:	[INTERN] bad block specific options. All options used
818  *			here must come from bbm.h. By default, these options
819  *			will be copied to the appropriate nand_bbt_descr's.
820  * @badblockpos:	[INTERN] position of the bad block marker in the oob
821  *			area.
822  * @badblockbits:	[INTERN] minimum number of set bits in a good block's
823  *			bad block marker position; i.e., BBM == 11110111b is
824  *			not bad when badblockbits == 7
825  * @bits_per_cell:	[INTERN] number of bits per cell. i.e., 1 means SLC.
826  * @ecc_strength_ds:	[INTERN] ECC correctability from the datasheet.
827  *			Minimum amount of bit errors per @ecc_step_ds guaranteed
828  *			to be correctable. If unknown, set to zero.
829  * @ecc_step_ds:	[INTERN] ECC step required by the @ecc_strength_ds,
830  *                      also from the datasheet. It is the recommended ECC step
831  *			size, if known; if unknown, set to zero.
832  * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
833  *			      set to the actually used ONFI mode if the chip is
834  *			      ONFI compliant or deduced from the datasheet if
835  *			      the NAND chip is not ONFI compliant.
836  * @numchips:		[INTERN] number of physical chips
837  * @chipsize:		[INTERN] the size of one chip for multichip arrays
838  * @pagemask:		[INTERN] page number mask = number of (pages / chip) - 1
839  * @pagebuf:		[INTERN] holds the pagenumber which is currently in
840  *			data_buf.
841  * @pagebuf_bitflips:	[INTERN] holds the bitflip count for the page which is
842  *			currently in data_buf.
843  * @subpagesize:	[INTERN] holds the subpagesize
844  * @onfi_version:	[INTERN] holds the chip ONFI version (BCD encoded),
845  *			non 0 if ONFI supported.
846  * @jedec_version:	[INTERN] holds the chip JEDEC version (BCD encoded),
847  *			non 0 if JEDEC supported.
848  * @onfi_params:	[INTERN] holds the ONFI page parameter when ONFI is
849  *			supported, 0 otherwise.
850  * @jedec_params:	[INTERN] holds the JEDEC parameter page when JEDEC is
851  *			supported, 0 otherwise.
852  * @read_retries:	[INTERN] the number of read retry modes supported
853  * @onfi_set_features:	[REPLACEABLE] set the features for ONFI nand
854  * @onfi_get_features:	[REPLACEABLE] get the features for ONFI nand
855  * @setup_data_interface: [OPTIONAL] setup the data interface and timing. If
856  *			  chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this
857  *			  means the configuration should not be applied but
858  *			  only checked.
859  * @bbt:		[INTERN] bad block table pointer
860  * @bbt_td:		[REPLACEABLE] bad block table descriptor for flash
861  *			lookup.
862  * @bbt_md:		[REPLACEABLE] bad block table mirror descriptor
863  * @badblock_pattern:	[REPLACEABLE] bad block scan pattern used for initial
864  *			bad block scan.
865  * @controller:		[REPLACEABLE] a pointer to a hardware controller
866  *			structure which is shared among multiple independent
867  *			devices.
868  * @priv:		[OPTIONAL] pointer to private chip data
869  * @write_page:		[REPLACEABLE] High-level page write function
870  */
871 
872 struct nand_chip {
873 	struct mtd_info mtd;
874 	void __iomem *IO_ADDR_R;
875 	void __iomem *IO_ADDR_W;
876 
877 	int flash_node;
878 
879 	uint8_t (*read_byte)(struct mtd_info *mtd);
880 	u16 (*read_word)(struct mtd_info *mtd);
881 	void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
882 	void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
883 	void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
884 	void (*select_chip)(struct mtd_info *mtd, int chip);
885 	int (*block_bad)(struct mtd_info *mtd, loff_t ofs);
886 	int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
887 	void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
888 	int (*dev_ready)(struct mtd_info *mtd);
889 	void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
890 			int page_addr);
891 	int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
892 	int (*erase)(struct mtd_info *mtd, int page);
893 	int (*scan_bbt)(struct mtd_info *mtd);
894 	int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
895 			uint32_t offset, int data_len, const uint8_t *buf,
896 			int oob_required, int page, int raw);
897 	int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
898 			int feature_addr, uint8_t *subfeature_para);
899 	int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
900 			int feature_addr, uint8_t *subfeature_para);
901 	int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
902 	int (*setup_data_interface)(struct mtd_info *mtd, int chipnr,
903 				    const struct nand_data_interface *conf);
904 
905 
906 	int chip_delay;
907 	unsigned int options;
908 	unsigned int bbt_options;
909 
910 	int page_shift;
911 	int phys_erase_shift;
912 	int bbt_erase_shift;
913 	int chip_shift;
914 	int numchips;
915 	uint64_t chipsize;
916 	int pagemask;
917 	int pagebuf;
918 	unsigned int pagebuf_bitflips;
919 	int subpagesize;
920 	uint8_t bits_per_cell;
921 	uint16_t ecc_strength_ds;
922 	uint16_t ecc_step_ds;
923 	int onfi_timing_mode_default;
924 	int badblockpos;
925 	int badblockbits;
926 
927 	int onfi_version;
928 	int jedec_version;
929 	struct nand_onfi_params	onfi_params;
930 	struct nand_jedec_params jedec_params;
931 
932 	struct nand_data_interface *data_interface;
933 
934 	int read_retries;
935 
936 	flstate_t state;
937 
938 	uint8_t *oob_poi;
939 	struct nand_hw_control *controller;
940 	struct nand_ecclayout *ecclayout;
941 
942 	struct nand_ecc_ctrl ecc;
943 	struct nand_buffers *buffers;
944 	unsigned long buf_align;
945 	struct nand_hw_control hwcontrol;
946 
947 	uint8_t *bbt;
948 	struct nand_bbt_descr *bbt_td;
949 	struct nand_bbt_descr *bbt_md;
950 
951 	struct nand_bbt_descr *badblock_pattern;
952 
953 	void *priv;
954 };
955 
mtd_to_nand(struct mtd_info * mtd)956 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
957 {
958 	return container_of(mtd, struct nand_chip, mtd);
959 }
960 
nand_to_mtd(struct nand_chip * chip)961 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
962 {
963 	return &chip->mtd;
964 }
965 
nand_get_controller_data(struct nand_chip * chip)966 static inline void *nand_get_controller_data(struct nand_chip *chip)
967 {
968 	return chip->priv;
969 }
970 
nand_set_controller_data(struct nand_chip * chip,void * priv)971 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
972 {
973 	chip->priv = priv;
974 }
975 
976 /*
977  * NAND Flash Manufacturer ID Codes
978  */
979 #define NAND_MFR_TOSHIBA	0x98
980 #define NAND_MFR_SAMSUNG	0xec
981 #define NAND_MFR_FUJITSU	0x04
982 #define NAND_MFR_NATIONAL	0x8f
983 #define NAND_MFR_RENESAS	0x07
984 #define NAND_MFR_STMICRO	0x20
985 #define NAND_MFR_HYNIX		0xad
986 #define NAND_MFR_MICRON		0x2c
987 #define NAND_MFR_AMD		0x01
988 #define NAND_MFR_MACRONIX	0xc2
989 #define NAND_MFR_EON		0x92
990 #define NAND_MFR_SANDISK	0x45
991 #define NAND_MFR_INTEL		0x89
992 #define NAND_MFR_ATO		0x9b
993 
994 /* The maximum expected count of bytes in the NAND ID sequence */
995 #define NAND_MAX_ID_LEN 8
996 
997 /*
998  * A helper for defining older NAND chips where the second ID byte fully
999  * defined the chip, including the geometry (chip size, eraseblock size, page
1000  * size). All these chips have 512 bytes NAND page size.
1001  */
1002 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts)          \
1003 	{ .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
1004 	  .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
1005 
1006 /*
1007  * A helper for defining newer chips which report their page size and
1008  * eraseblock size via the extended ID bytes.
1009  *
1010  * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
1011  * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
1012  * device ID now only represented a particular total chip size (and voltage,
1013  * buswidth), and the page size, eraseblock size, and OOB size could vary while
1014  * using the same device ID.
1015  */
1016 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts)                      \
1017 	{ .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
1018 	  .options = (opts) }
1019 
1020 #define NAND_ECC_INFO(_strength, _step)	\
1021 			{ .strength_ds = (_strength), .step_ds = (_step) }
1022 #define NAND_ECC_STRENGTH(type)		((type)->ecc.strength_ds)
1023 #define NAND_ECC_STEP(type)		((type)->ecc.step_ds)
1024 
1025 /**
1026  * struct nand_flash_dev - NAND Flash Device ID Structure
1027  * @name: a human-readable name of the NAND chip
1028  * @dev_id: the device ID (the second byte of the full chip ID array)
1029  * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
1030  *          memory address as @id[0])
1031  * @dev_id: device ID part of the full chip ID array (refers the same memory
1032  *          address as @id[1])
1033  * @id: full device ID array
1034  * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
1035  *            well as the eraseblock size) is determined from the extended NAND
1036  *            chip ID array)
1037  * @chipsize: total chip size in MiB
1038  * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
1039  * @options: stores various chip bit options
1040  * @id_len: The valid length of the @id.
1041  * @oobsize: OOB size
1042  * @ecc: ECC correctability and step information from the datasheet.
1043  * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
1044  *                   @ecc_strength_ds in nand_chip{}.
1045  * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
1046  *               @ecc_step_ds in nand_chip{}, also from the datasheet.
1047  *               For example, the "4bit ECC for each 512Byte" can be set with
1048  *               NAND_ECC_INFO(4, 512).
1049  * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
1050  *			      reset. Should be deduced from timings described
1051  *			      in the datasheet.
1052  *
1053  */
1054 struct nand_flash_dev {
1055 	char *name;
1056 	union {
1057 		struct {
1058 			uint8_t mfr_id;
1059 			uint8_t dev_id;
1060 		};
1061 		uint8_t id[NAND_MAX_ID_LEN];
1062 	};
1063 	unsigned int pagesize;
1064 	unsigned int chipsize;
1065 	unsigned int erasesize;
1066 	unsigned int options;
1067 	uint16_t id_len;
1068 	uint16_t oobsize;
1069 	struct {
1070 		uint16_t strength_ds;
1071 		uint16_t step_ds;
1072 	} ecc;
1073 	int onfi_timing_mode_default;
1074 };
1075 
1076 /**
1077  * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
1078  * @name:	Manufacturer name
1079  * @id:		manufacturer ID code of device.
1080 */
1081 struct nand_manufacturers {
1082 	int id;
1083 	char *name;
1084 };
1085 
1086 extern struct nand_flash_dev nand_flash_ids[];
1087 extern struct nand_manufacturers nand_manuf_ids[];
1088 
1089 int nand_default_bbt(struct mtd_info *mtd);
1090 int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
1091 int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
1092 int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
1093 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
1094 			   int allowbbt);
1095 int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
1096 			size_t *retlen, uint8_t *buf);
1097 
1098 /*
1099 * Constants for oob configuration
1100 */
1101 #define NAND_SMALL_BADBLOCK_POS		5
1102 #define NAND_LARGE_BADBLOCK_POS		0
1103 
1104 /**
1105  * struct platform_nand_chip - chip level device structure
1106  * @nr_chips:		max. number of chips to scan for
1107  * @chip_offset:	chip number offset
1108  * @nr_partitions:	number of partitions pointed to by partitions (or zero)
1109  * @partitions:		mtd partition list
1110  * @chip_delay:		R/B delay value in us
1111  * @options:		Option flags, e.g. 16bit buswidth
1112  * @bbt_options:	BBT option flags, e.g. NAND_BBT_USE_FLASH
1113  * @part_probe_types:	NULL-terminated array of probe types
1114  */
1115 struct platform_nand_chip {
1116 	int nr_chips;
1117 	int chip_offset;
1118 	int nr_partitions;
1119 	struct mtd_partition *partitions;
1120 	int chip_delay;
1121 	unsigned int options;
1122 	unsigned int bbt_options;
1123 	const char **part_probe_types;
1124 };
1125 
1126 /* Keep gcc happy */
1127 struct platform_device;
1128 
1129 /**
1130  * struct platform_nand_ctrl - controller level device structure
1131  * @probe:		platform specific function to probe/setup hardware
1132  * @remove:		platform specific function to remove/teardown hardware
1133  * @hwcontrol:		platform specific hardware control structure
1134  * @dev_ready:		platform specific function to read ready/busy pin
1135  * @select_chip:	platform specific chip select function
1136  * @cmd_ctrl:		platform specific function for controlling
1137  *			ALE/CLE/nCE. Also used to write command and address
1138  * @write_buf:		platform specific function for write buffer
1139  * @read_buf:		platform specific function for read buffer
1140  * @read_byte:		platform specific function to read one byte from chip
1141  * @priv:		private data to transport driver specific settings
1142  *
1143  * All fields are optional and depend on the hardware driver requirements
1144  */
1145 struct platform_nand_ctrl {
1146 	int (*probe)(struct platform_device *pdev);
1147 	void (*remove)(struct platform_device *pdev);
1148 	void (*hwcontrol)(struct mtd_info *mtd, int cmd);
1149 	int (*dev_ready)(struct mtd_info *mtd);
1150 	void (*select_chip)(struct mtd_info *mtd, int chip);
1151 	void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
1152 	void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
1153 	void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
1154 	unsigned char (*read_byte)(struct mtd_info *mtd);
1155 	void *priv;
1156 };
1157 
1158 /**
1159  * struct platform_nand_data - container structure for platform-specific data
1160  * @chip:		chip level chip structure
1161  * @ctrl:		controller level device structure
1162  */
1163 struct platform_nand_data {
1164 	struct platform_nand_chip chip;
1165 	struct platform_nand_ctrl ctrl;
1166 };
1167 
1168 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
1169 /* return the supported features. */
onfi_feature(struct nand_chip * chip)1170 static inline int onfi_feature(struct nand_chip *chip)
1171 {
1172 	return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;
1173 }
1174 
1175 /* return the supported asynchronous timing mode. */
onfi_get_async_timing_mode(struct nand_chip * chip)1176 static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
1177 {
1178 	if (!chip->onfi_version)
1179 		return ONFI_TIMING_MODE_UNKNOWN;
1180 	return le16_to_cpu(chip->onfi_params.async_timing_mode);
1181 }
1182 
1183 /* return the supported synchronous timing mode. */
onfi_get_sync_timing_mode(struct nand_chip * chip)1184 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
1185 {
1186 	if (!chip->onfi_version)
1187 		return ONFI_TIMING_MODE_UNKNOWN;
1188 	return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
1189 }
1190 #else
onfi_feature(struct nand_chip * chip)1191 static inline int onfi_feature(struct nand_chip *chip)
1192 {
1193 	return 0;
1194 }
1195 
onfi_get_async_timing_mode(struct nand_chip * chip)1196 static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
1197 {
1198 	return ONFI_TIMING_MODE_UNKNOWN;
1199 }
1200 
onfi_get_sync_timing_mode(struct nand_chip * chip)1201 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
1202 {
1203 	return ONFI_TIMING_MODE_UNKNOWN;
1204 }
1205 #endif
1206 
1207 int onfi_init_data_interface(struct nand_chip *chip,
1208 			     struct nand_data_interface *iface,
1209 			     enum nand_data_interface_type type,
1210 			     int timing_mode);
1211 
1212 /*
1213  * Check if it is a SLC nand.
1214  * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
1215  * We do not distinguish the MLC and TLC now.
1216  */
nand_is_slc(struct nand_chip * chip)1217 static inline bool nand_is_slc(struct nand_chip *chip)
1218 {
1219 	return chip->bits_per_cell == 1;
1220 }
1221 
1222 /**
1223  * Check if the opcode's address should be sent only on the lower 8 bits
1224  * @command: opcode to check
1225  */
nand_opcode_8bits(unsigned int command)1226 static inline int nand_opcode_8bits(unsigned int command)
1227 {
1228 	switch (command) {
1229 	case NAND_CMD_READID:
1230 	case NAND_CMD_PARAM:
1231 	case NAND_CMD_GET_FEATURES:
1232 	case NAND_CMD_SET_FEATURES:
1233 		return 1;
1234 	default:
1235 		break;
1236 	}
1237 	return 0;
1238 }
1239 
1240 /* return the supported JEDEC features. */
jedec_feature(struct nand_chip * chip)1241 static inline int jedec_feature(struct nand_chip *chip)
1242 {
1243 	return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)
1244 		: 0;
1245 }
1246 
1247 /* Standard NAND functions from nand_base.c */
1248 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len);
1249 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len);
1250 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len);
1251 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len);
1252 uint8_t nand_read_byte(struct mtd_info *mtd);
1253 
1254 /* get timing characteristics from ONFI timing mode. */
1255 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
1256 /* get data interface from ONFI timing mode 0, used after reset. */
1257 const struct nand_data_interface *nand_get_default_data_interface(void);
1258 
1259 int nand_check_erased_ecc_chunk(void *data, int datalen,
1260 				void *ecc, int ecclen,
1261 				void *extraoob, int extraooblen,
1262 				int threshold);
1263 
1264 int nand_check_ecc_caps(struct nand_chip *chip,
1265 			const struct nand_ecc_caps *caps, int oobavail);
1266 
1267 int nand_match_ecc_req(struct nand_chip *chip,
1268 		       const struct nand_ecc_caps *caps,  int oobavail);
1269 
1270 int nand_maximize_ecc(struct nand_chip *chip,
1271 		      const struct nand_ecc_caps *caps, int oobavail);
1272 
1273 /* Reset and initialize a NAND device */
1274 int nand_reset(struct nand_chip *chip, int chipnr);
1275 #endif /* __LINUX_MTD_RAWNAND_H */
1276