1 // Copyright 2014 the V8 project authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 #ifndef V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_ 6 #define V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_ 7 8 namespace v8 { 9 namespace internal { 10 namespace compiler { 11 12 // IA32-specific opcodes that specify which assembly sequence to emit. 13 // Most opcodes specify a single instruction. 14 #define TARGET_ARCH_OPCODE_LIST(V) \ 15 V(IA32Add) \ 16 V(IA32And) \ 17 V(IA32Cmp) \ 18 V(IA32Cmp16) \ 19 V(IA32Cmp8) \ 20 V(IA32Test) \ 21 V(IA32Test16) \ 22 V(IA32Test8) \ 23 V(IA32Or) \ 24 V(IA32Xor) \ 25 V(IA32Sub) \ 26 V(IA32Imul) \ 27 V(IA32ImulHigh) \ 28 V(IA32UmulHigh) \ 29 V(IA32Idiv) \ 30 V(IA32Udiv) \ 31 V(IA32Not) \ 32 V(IA32Neg) \ 33 V(IA32Shl) \ 34 V(IA32Shr) \ 35 V(IA32Sar) \ 36 V(IA32AddPair) \ 37 V(IA32SubPair) \ 38 V(IA32MulPair) \ 39 V(IA32ShlPair) \ 40 V(IA32ShrPair) \ 41 V(IA32SarPair) \ 42 V(IA32Ror) \ 43 V(IA32Lzcnt) \ 44 V(IA32Tzcnt) \ 45 V(IA32Popcnt) \ 46 V(IA32Bswap) \ 47 V(LFence) \ 48 V(SSEFloat32Cmp) \ 49 V(SSEFloat32Add) \ 50 V(SSEFloat32Sub) \ 51 V(SSEFloat32Mul) \ 52 V(SSEFloat32Div) \ 53 V(SSEFloat32Abs) \ 54 V(SSEFloat32Neg) \ 55 V(SSEFloat32Sqrt) \ 56 V(SSEFloat32Round) \ 57 V(SSEFloat64Cmp) \ 58 V(SSEFloat64Add) \ 59 V(SSEFloat64Sub) \ 60 V(SSEFloat64Mul) \ 61 V(SSEFloat64Div) \ 62 V(SSEFloat64Mod) \ 63 V(SSEFloat32Max) \ 64 V(SSEFloat64Max) \ 65 V(SSEFloat32Min) \ 66 V(SSEFloat64Min) \ 67 V(SSEFloat64Abs) \ 68 V(SSEFloat64Neg) \ 69 V(SSEFloat64Sqrt) \ 70 V(SSEFloat64Round) \ 71 V(SSEFloat32ToFloat64) \ 72 V(SSEFloat64ToFloat32) \ 73 V(SSEFloat32ToInt32) \ 74 V(SSEFloat32ToUint32) \ 75 V(SSEFloat64ToInt32) \ 76 V(SSEFloat64ToUint32) \ 77 V(SSEInt32ToFloat32) \ 78 V(SSEUint32ToFloat32) \ 79 V(SSEInt32ToFloat64) \ 80 V(SSEUint32ToFloat64) \ 81 V(SSEFloat64ExtractLowWord32) \ 82 V(SSEFloat64ExtractHighWord32) \ 83 V(SSEFloat64InsertLowWord32) \ 84 V(SSEFloat64InsertHighWord32) \ 85 V(SSEFloat64LoadLowWord32) \ 86 V(SSEFloat64SilenceNaN) \ 87 V(AVXFloat32Add) \ 88 V(AVXFloat32Sub) \ 89 V(AVXFloat32Mul) \ 90 V(AVXFloat32Div) \ 91 V(AVXFloat64Add) \ 92 V(AVXFloat64Sub) \ 93 V(AVXFloat64Mul) \ 94 V(AVXFloat64Div) \ 95 V(AVXFloat64Abs) \ 96 V(AVXFloat64Neg) \ 97 V(AVXFloat32Abs) \ 98 V(AVXFloat32Neg) \ 99 V(IA32Movsxbl) \ 100 V(IA32Movzxbl) \ 101 V(IA32Movb) \ 102 V(IA32Movsxwl) \ 103 V(IA32Movzxwl) \ 104 V(IA32Movw) \ 105 V(IA32Movl) \ 106 V(IA32Movss) \ 107 V(IA32Movsd) \ 108 V(IA32Movdqu) \ 109 V(IA32BitcastFI) \ 110 V(IA32BitcastIF) \ 111 V(IA32Lea) \ 112 V(IA32Push) \ 113 V(IA32PushFloat32) \ 114 V(IA32PushFloat64) \ 115 V(IA32PushSimd128) \ 116 V(IA32Poke) \ 117 V(IA32Peek) \ 118 V(IA32StackCheck) \ 119 V(SSEF32x4Splat) \ 120 V(AVXF32x4Splat) \ 121 V(SSEF32x4ExtractLane) \ 122 V(AVXF32x4ExtractLane) \ 123 V(SSEF32x4ReplaceLane) \ 124 V(AVXF32x4ReplaceLane) \ 125 V(IA32F32x4SConvertI32x4) \ 126 V(SSEF32x4UConvertI32x4) \ 127 V(AVXF32x4UConvertI32x4) \ 128 V(SSEF32x4Abs) \ 129 V(AVXF32x4Abs) \ 130 V(SSEF32x4Neg) \ 131 V(AVXF32x4Neg) \ 132 V(IA32F32x4RecipApprox) \ 133 V(IA32F32x4RecipSqrtApprox) \ 134 V(SSEF32x4Add) \ 135 V(AVXF32x4Add) \ 136 V(SSEF32x4AddHoriz) \ 137 V(AVXF32x4AddHoriz) \ 138 V(SSEF32x4Sub) \ 139 V(AVXF32x4Sub) \ 140 V(SSEF32x4Mul) \ 141 V(AVXF32x4Mul) \ 142 V(SSEF32x4Min) \ 143 V(AVXF32x4Min) \ 144 V(SSEF32x4Max) \ 145 V(AVXF32x4Max) \ 146 V(SSEF32x4Eq) \ 147 V(AVXF32x4Eq) \ 148 V(SSEF32x4Ne) \ 149 V(AVXF32x4Ne) \ 150 V(SSEF32x4Lt) \ 151 V(AVXF32x4Lt) \ 152 V(SSEF32x4Le) \ 153 V(AVXF32x4Le) \ 154 V(IA32I32x4Splat) \ 155 V(IA32I32x4ExtractLane) \ 156 V(SSEI32x4ReplaceLane) \ 157 V(AVXI32x4ReplaceLane) \ 158 V(SSEI32x4SConvertF32x4) \ 159 V(AVXI32x4SConvertF32x4) \ 160 V(IA32I32x4SConvertI16x8Low) \ 161 V(IA32I32x4SConvertI16x8High) \ 162 V(IA32I32x4Neg) \ 163 V(SSEI32x4Shl) \ 164 V(AVXI32x4Shl) \ 165 V(SSEI32x4ShrS) \ 166 V(AVXI32x4ShrS) \ 167 V(SSEI32x4Add) \ 168 V(AVXI32x4Add) \ 169 V(SSEI32x4AddHoriz) \ 170 V(AVXI32x4AddHoriz) \ 171 V(SSEI32x4Sub) \ 172 V(AVXI32x4Sub) \ 173 V(SSEI32x4Mul) \ 174 V(AVXI32x4Mul) \ 175 V(SSEI32x4MinS) \ 176 V(AVXI32x4MinS) \ 177 V(SSEI32x4MaxS) \ 178 V(AVXI32x4MaxS) \ 179 V(SSEI32x4Eq) \ 180 V(AVXI32x4Eq) \ 181 V(SSEI32x4Ne) \ 182 V(AVXI32x4Ne) \ 183 V(SSEI32x4GtS) \ 184 V(AVXI32x4GtS) \ 185 V(SSEI32x4GeS) \ 186 V(AVXI32x4GeS) \ 187 V(SSEI32x4UConvertF32x4) \ 188 V(AVXI32x4UConvertF32x4) \ 189 V(IA32I32x4UConvertI16x8Low) \ 190 V(IA32I32x4UConvertI16x8High) \ 191 V(SSEI32x4ShrU) \ 192 V(AVXI32x4ShrU) \ 193 V(SSEI32x4MinU) \ 194 V(AVXI32x4MinU) \ 195 V(SSEI32x4MaxU) \ 196 V(AVXI32x4MaxU) \ 197 V(SSEI32x4GtU) \ 198 V(AVXI32x4GtU) \ 199 V(SSEI32x4GeU) \ 200 V(AVXI32x4GeU) \ 201 V(IA32I16x8Splat) \ 202 V(IA32I16x8ExtractLane) \ 203 V(SSEI16x8ReplaceLane) \ 204 V(AVXI16x8ReplaceLane) \ 205 V(IA32I16x8SConvertI8x16Low) \ 206 V(IA32I16x8SConvertI8x16High) \ 207 V(IA32I16x8Neg) \ 208 V(SSEI16x8Shl) \ 209 V(AVXI16x8Shl) \ 210 V(SSEI16x8ShrS) \ 211 V(AVXI16x8ShrS) \ 212 V(SSEI16x8SConvertI32x4) \ 213 V(AVXI16x8SConvertI32x4) \ 214 V(SSEI16x8Add) \ 215 V(AVXI16x8Add) \ 216 V(SSEI16x8AddSaturateS) \ 217 V(AVXI16x8AddSaturateS) \ 218 V(SSEI16x8AddHoriz) \ 219 V(AVXI16x8AddHoriz) \ 220 V(SSEI16x8Sub) \ 221 V(AVXI16x8Sub) \ 222 V(SSEI16x8SubSaturateS) \ 223 V(AVXI16x8SubSaturateS) \ 224 V(SSEI16x8Mul) \ 225 V(AVXI16x8Mul) \ 226 V(SSEI16x8MinS) \ 227 V(AVXI16x8MinS) \ 228 V(SSEI16x8MaxS) \ 229 V(AVXI16x8MaxS) \ 230 V(SSEI16x8Eq) \ 231 V(AVXI16x8Eq) \ 232 V(SSEI16x8Ne) \ 233 V(AVXI16x8Ne) \ 234 V(SSEI16x8GtS) \ 235 V(AVXI16x8GtS) \ 236 V(SSEI16x8GeS) \ 237 V(AVXI16x8GeS) \ 238 V(IA32I16x8UConvertI8x16Low) \ 239 V(IA32I16x8UConvertI8x16High) \ 240 V(SSEI16x8ShrU) \ 241 V(AVXI16x8ShrU) \ 242 V(SSEI16x8UConvertI32x4) \ 243 V(AVXI16x8UConvertI32x4) \ 244 V(SSEI16x8AddSaturateU) \ 245 V(AVXI16x8AddSaturateU) \ 246 V(SSEI16x8SubSaturateU) \ 247 V(AVXI16x8SubSaturateU) \ 248 V(SSEI16x8MinU) \ 249 V(AVXI16x8MinU) \ 250 V(SSEI16x8MaxU) \ 251 V(AVXI16x8MaxU) \ 252 V(SSEI16x8GtU) \ 253 V(AVXI16x8GtU) \ 254 V(SSEI16x8GeU) \ 255 V(AVXI16x8GeU) \ 256 V(IA32I8x16Splat) \ 257 V(IA32I8x16ExtractLane) \ 258 V(SSEI8x16ReplaceLane) \ 259 V(AVXI8x16ReplaceLane) \ 260 V(SSEI8x16SConvertI16x8) \ 261 V(AVXI8x16SConvertI16x8) \ 262 V(IA32I8x16Neg) \ 263 V(SSEI8x16Shl) \ 264 V(AVXI8x16Shl) \ 265 V(IA32I8x16ShrS) \ 266 V(SSEI8x16Add) \ 267 V(AVXI8x16Add) \ 268 V(SSEI8x16AddSaturateS) \ 269 V(AVXI8x16AddSaturateS) \ 270 V(SSEI8x16Sub) \ 271 V(AVXI8x16Sub) \ 272 V(SSEI8x16SubSaturateS) \ 273 V(AVXI8x16SubSaturateS) \ 274 V(SSEI8x16Mul) \ 275 V(AVXI8x16Mul) \ 276 V(SSEI8x16MinS) \ 277 V(AVXI8x16MinS) \ 278 V(SSEI8x16MaxS) \ 279 V(AVXI8x16MaxS) \ 280 V(SSEI8x16Eq) \ 281 V(AVXI8x16Eq) \ 282 V(SSEI8x16Ne) \ 283 V(AVXI8x16Ne) \ 284 V(SSEI8x16GtS) \ 285 V(AVXI8x16GtS) \ 286 V(SSEI8x16GeS) \ 287 V(AVXI8x16GeS) \ 288 V(SSEI8x16UConvertI16x8) \ 289 V(AVXI8x16UConvertI16x8) \ 290 V(SSEI8x16AddSaturateU) \ 291 V(AVXI8x16AddSaturateU) \ 292 V(SSEI8x16SubSaturateU) \ 293 V(AVXI8x16SubSaturateU) \ 294 V(IA32I8x16ShrU) \ 295 V(SSEI8x16MinU) \ 296 V(AVXI8x16MinU) \ 297 V(SSEI8x16MaxU) \ 298 V(AVXI8x16MaxU) \ 299 V(SSEI8x16GtU) \ 300 V(AVXI8x16GtU) \ 301 V(SSEI8x16GeU) \ 302 V(AVXI8x16GeU) \ 303 V(IA32S128Zero) \ 304 V(SSES128Not) \ 305 V(AVXS128Not) \ 306 V(SSES128And) \ 307 V(AVXS128And) \ 308 V(SSES128Or) \ 309 V(AVXS128Or) \ 310 V(SSES128Xor) \ 311 V(AVXS128Xor) \ 312 V(SSES128Select) \ 313 V(AVXS128Select) \ 314 V(IA32S8x16Shuffle) \ 315 V(IA32S32x4Swizzle) \ 316 V(IA32S32x4Shuffle) \ 317 V(IA32S16x8Blend) \ 318 V(IA32S16x8HalfShuffle1) \ 319 V(IA32S16x8HalfShuffle2) \ 320 V(IA32S8x16Alignr) \ 321 V(IA32S16x8Dup) \ 322 V(IA32S8x16Dup) \ 323 V(SSES16x8UnzipHigh) \ 324 V(AVXS16x8UnzipHigh) \ 325 V(SSES16x8UnzipLow) \ 326 V(AVXS16x8UnzipLow) \ 327 V(SSES8x16UnzipHigh) \ 328 V(AVXS8x16UnzipHigh) \ 329 V(SSES8x16UnzipLow) \ 330 V(AVXS8x16UnzipLow) \ 331 V(IA32S64x2UnpackHigh) \ 332 V(IA32S32x4UnpackHigh) \ 333 V(IA32S16x8UnpackHigh) \ 334 V(IA32S8x16UnpackHigh) \ 335 V(IA32S64x2UnpackLow) \ 336 V(IA32S32x4UnpackLow) \ 337 V(IA32S16x8UnpackLow) \ 338 V(IA32S8x16UnpackLow) \ 339 V(SSES8x16TransposeLow) \ 340 V(AVXS8x16TransposeLow) \ 341 V(SSES8x16TransposeHigh) \ 342 V(AVXS8x16TransposeHigh) \ 343 V(SSES8x8Reverse) \ 344 V(AVXS8x8Reverse) \ 345 V(SSES8x4Reverse) \ 346 V(AVXS8x4Reverse) \ 347 V(SSES8x2Reverse) \ 348 V(AVXS8x2Reverse) \ 349 V(IA32S1x4AnyTrue) \ 350 V(IA32S1x4AllTrue) \ 351 V(IA32S1x8AnyTrue) \ 352 V(IA32S1x8AllTrue) \ 353 V(IA32S1x16AnyTrue) \ 354 V(IA32S1x16AllTrue) \ 355 V(IA32Word32AtomicPairLoad) \ 356 V(IA32Word32AtomicPairStore) \ 357 V(IA32Word32AtomicPairAdd) \ 358 V(IA32Word32AtomicPairSub) \ 359 V(IA32Word32AtomicPairAnd) \ 360 V(IA32Word32AtomicPairOr) \ 361 V(IA32Word32AtomicPairXor) \ 362 V(IA32Word32AtomicPairExchange) \ 363 V(IA32Word32AtomicPairCompareExchange) \ 364 V(IA32Word64AtomicNarrowAddUint8) \ 365 V(IA32Word64AtomicNarrowAddUint16) \ 366 V(IA32Word64AtomicNarrowAddUint32) \ 367 V(IA32Word64AtomicNarrowSubUint8) \ 368 V(IA32Word64AtomicNarrowSubUint16) \ 369 V(IA32Word64AtomicNarrowSubUint32) \ 370 V(IA32Word64AtomicNarrowAndUint8) \ 371 V(IA32Word64AtomicNarrowAndUint16) \ 372 V(IA32Word64AtomicNarrowAndUint32) \ 373 V(IA32Word64AtomicNarrowOrUint8) \ 374 V(IA32Word64AtomicNarrowOrUint16) \ 375 V(IA32Word64AtomicNarrowOrUint32) \ 376 V(IA32Word64AtomicNarrowXorUint8) \ 377 V(IA32Word64AtomicNarrowXorUint16) \ 378 V(IA32Word64AtomicNarrowXorUint32) \ 379 V(IA32Word64AtomicNarrowExchangeUint8) \ 380 V(IA32Word64AtomicNarrowExchangeUint16) \ 381 V(IA32Word64AtomicNarrowExchangeUint32) \ 382 V(IA32Word64AtomicNarrowCompareExchangeUint8) \ 383 V(IA32Word64AtomicNarrowCompareExchangeUint16) \ 384 V(IA32Word64AtomicNarrowCompareExchangeUint32) 385 386 // Addressing modes represent the "shape" of inputs to an instruction. 387 // Many instructions support multiple addressing modes. Addressing modes 388 // are encoded into the InstructionCode of the instruction and tell the 389 // code generator after register allocation which assembler method to call. 390 // 391 // We use the following local notation for addressing modes: 392 // 393 // M = memory operand 394 // R = base register 395 // N = index register * N for N in {1, 2, 4, 8} 396 // I = immediate displacement (int32_t) 397 398 #define TARGET_ADDRESSING_MODE_LIST(V) \ 399 V(MR) /* [%r1 ] */ \ 400 V(MRI) /* [%r1 + K] */ \ 401 V(MR1) /* [%r1 + %r2*1 ] */ \ 402 V(MR2) /* [%r1 + %r2*2 ] */ \ 403 V(MR4) /* [%r1 + %r2*4 ] */ \ 404 V(MR8) /* [%r1 + %r2*8 ] */ \ 405 V(MR1I) /* [%r1 + %r2*1 + K] */ \ 406 V(MR2I) /* [%r1 + %r2*2 + K] */ \ 407 V(MR4I) /* [%r1 + %r2*3 + K] */ \ 408 V(MR8I) /* [%r1 + %r2*4 + K] */ \ 409 V(M1) /* [ %r2*1 ] */ \ 410 V(M2) /* [ %r2*2 ] */ \ 411 V(M4) /* [ %r2*4 ] */ \ 412 V(M8) /* [ %r2*8 ] */ \ 413 V(M1I) /* [ %r2*1 + K] */ \ 414 V(M2I) /* [ %r2*2 + K] */ \ 415 V(M4I) /* [ %r2*4 + K] */ \ 416 V(M8I) /* [ %r2*8 + K] */ \ 417 V(MI) /* [ K] */ 418 419 } // namespace compiler 420 } // namespace internal 421 } // namespace v8 422 423 #endif // V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_ 424