1 // Copyright 2016, VIXL authors
2 // All rights reserved.
3 //
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are met:
6 //
7 // * Redistributions of source code must retain the above copyright notice,
8 // this list of conditions and the following disclaimer.
9 // * Redistributions in binary form must reproduce the above copyright notice,
10 // this list of conditions and the following disclaimer in the documentation
11 // and/or other materials provided with the distribution.
12 // * Neither the name of ARM Limited nor the names of its contributors may be
13 // used to endorse or promote products derived from this software without
14 // specific prior written permission.
15 //
16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
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21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
27
28 // -----------------------------------------------------------------------------
29 // This file is auto generated from the
30 // test/aarch32/config/template-assembler-aarch32.cc.in template file using
31 // tools/generate_tests.py.
32 //
33 // PLEASE DO NOT EDIT.
34 // -----------------------------------------------------------------------------
35
36
37 #include "test-runner.h"
38
39 #include "test-utils.h"
40 #include "test-utils-aarch32.h"
41
42 #include "aarch32/assembler-aarch32.h"
43 #include "aarch32/macro-assembler-aarch32.h"
44
45 #define BUF_SIZE (4096)
46
47 namespace vixl {
48 namespace aarch32 {
49
50 // List of instruction mnemonics.
51 #define FOREACH_INSTRUCTION(M) M(muls)
52
53
54 // The following definitions are defined again in each generated test, therefore
55 // we need to place them in an anomymous namespace. It expresses that they are
56 // local to this file only, and the compiler is not allowed to share these types
57 // across test files during template instantiation. Specifically, `Operands` has
58 // various layouts across generated tests so it absolutely cannot be shared.
59
60 #ifdef VIXL_INCLUDE_TARGET_T32
61 namespace {
62
63 // Values to be passed to the assembler to produce the instruction under test.
64 struct Operands {
65 Condition cond;
66 Register rd;
67 Register rn;
68 Register rm;
69 };
70
71 // This structure contains all data needed to test one specific
72 // instruction.
73 struct TestData {
74 // The `operands` field represents what to pass to the assembler to
75 // produce the instruction.
76 Operands operands;
77 // True if we need to generate an IT instruction for this test to be valid.
78 bool in_it_block;
79 // The condition to give the IT instruction, this will be set to "al" by
80 // default.
81 Condition it_condition;
82 // Description of the operands, used for error reporting.
83 const char* operands_description;
84 // Unique identifier, used for generating traces.
85 const char* identifier;
86 };
87
88 struct TestResult {
89 size_t size;
90 const byte* encoding;
91 };
92
93 // Each element of this array produce one instruction encoding.
94 const TestData kTests[] =
95 {{{al, r0, r0, r0}, false, al, "al r0 r0 r0", "al_r0_r0_r0"},
96 {{al, r0, r1, r0}, false, al, "al r0 r1 r0", "al_r0_r1_r0"},
97 {{al, r0, r2, r0}, false, al, "al r0 r2 r0", "al_r0_r2_r0"},
98 {{al, r0, r3, r0}, false, al, "al r0 r3 r0", "al_r0_r3_r0"},
99 {{al, r0, r4, r0}, false, al, "al r0 r4 r0", "al_r0_r4_r0"},
100 {{al, r0, r5, r0}, false, al, "al r0 r5 r0", "al_r0_r5_r0"},
101 {{al, r0, r6, r0}, false, al, "al r0 r6 r0", "al_r0_r6_r0"},
102 {{al, r0, r7, r0}, false, al, "al r0 r7 r0", "al_r0_r7_r0"},
103 {{al, r1, r0, r1}, false, al, "al r1 r0 r1", "al_r1_r0_r1"},
104 {{al, r1, r1, r1}, false, al, "al r1 r1 r1", "al_r1_r1_r1"},
105 {{al, r1, r2, r1}, false, al, "al r1 r2 r1", "al_r1_r2_r1"},
106 {{al, r1, r3, r1}, false, al, "al r1 r3 r1", "al_r1_r3_r1"},
107 {{al, r1, r4, r1}, false, al, "al r1 r4 r1", "al_r1_r4_r1"},
108 {{al, r1, r5, r1}, false, al, "al r1 r5 r1", "al_r1_r5_r1"},
109 {{al, r1, r6, r1}, false, al, "al r1 r6 r1", "al_r1_r6_r1"},
110 {{al, r1, r7, r1}, false, al, "al r1 r7 r1", "al_r1_r7_r1"},
111 {{al, r2, r0, r2}, false, al, "al r2 r0 r2", "al_r2_r0_r2"},
112 {{al, r2, r1, r2}, false, al, "al r2 r1 r2", "al_r2_r1_r2"},
113 {{al, r2, r2, r2}, false, al, "al r2 r2 r2", "al_r2_r2_r2"},
114 {{al, r2, r3, r2}, false, al, "al r2 r3 r2", "al_r2_r3_r2"},
115 {{al, r2, r4, r2}, false, al, "al r2 r4 r2", "al_r2_r4_r2"},
116 {{al, r2, r5, r2}, false, al, "al r2 r5 r2", "al_r2_r5_r2"},
117 {{al, r2, r6, r2}, false, al, "al r2 r6 r2", "al_r2_r6_r2"},
118 {{al, r2, r7, r2}, false, al, "al r2 r7 r2", "al_r2_r7_r2"},
119 {{al, r3, r0, r3}, false, al, "al r3 r0 r3", "al_r3_r0_r3"},
120 {{al, r3, r1, r3}, false, al, "al r3 r1 r3", "al_r3_r1_r3"},
121 {{al, r3, r2, r3}, false, al, "al r3 r2 r3", "al_r3_r2_r3"},
122 {{al, r3, r3, r3}, false, al, "al r3 r3 r3", "al_r3_r3_r3"},
123 {{al, r3, r4, r3}, false, al, "al r3 r4 r3", "al_r3_r4_r3"},
124 {{al, r3, r5, r3}, false, al, "al r3 r5 r3", "al_r3_r5_r3"},
125 {{al, r3, r6, r3}, false, al, "al r3 r6 r3", "al_r3_r6_r3"},
126 {{al, r3, r7, r3}, false, al, "al r3 r7 r3", "al_r3_r7_r3"},
127 {{al, r4, r0, r4}, false, al, "al r4 r0 r4", "al_r4_r0_r4"},
128 {{al, r4, r1, r4}, false, al, "al r4 r1 r4", "al_r4_r1_r4"},
129 {{al, r4, r2, r4}, false, al, "al r4 r2 r4", "al_r4_r2_r4"},
130 {{al, r4, r3, r4}, false, al, "al r4 r3 r4", "al_r4_r3_r4"},
131 {{al, r4, r4, r4}, false, al, "al r4 r4 r4", "al_r4_r4_r4"},
132 {{al, r4, r5, r4}, false, al, "al r4 r5 r4", "al_r4_r5_r4"},
133 {{al, r4, r6, r4}, false, al, "al r4 r6 r4", "al_r4_r6_r4"},
134 {{al, r4, r7, r4}, false, al, "al r4 r7 r4", "al_r4_r7_r4"},
135 {{al, r5, r0, r5}, false, al, "al r5 r0 r5", "al_r5_r0_r5"},
136 {{al, r5, r1, r5}, false, al, "al r5 r1 r5", "al_r5_r1_r5"},
137 {{al, r5, r2, r5}, false, al, "al r5 r2 r5", "al_r5_r2_r5"},
138 {{al, r5, r3, r5}, false, al, "al r5 r3 r5", "al_r5_r3_r5"},
139 {{al, r5, r4, r5}, false, al, "al r5 r4 r5", "al_r5_r4_r5"},
140 {{al, r5, r5, r5}, false, al, "al r5 r5 r5", "al_r5_r5_r5"},
141 {{al, r5, r6, r5}, false, al, "al r5 r6 r5", "al_r5_r6_r5"},
142 {{al, r5, r7, r5}, false, al, "al r5 r7 r5", "al_r5_r7_r5"},
143 {{al, r6, r0, r6}, false, al, "al r6 r0 r6", "al_r6_r0_r6"},
144 {{al, r6, r1, r6}, false, al, "al r6 r1 r6", "al_r6_r1_r6"},
145 {{al, r6, r2, r6}, false, al, "al r6 r2 r6", "al_r6_r2_r6"},
146 {{al, r6, r3, r6}, false, al, "al r6 r3 r6", "al_r6_r3_r6"},
147 {{al, r6, r4, r6}, false, al, "al r6 r4 r6", "al_r6_r4_r6"},
148 {{al, r6, r5, r6}, false, al, "al r6 r5 r6", "al_r6_r5_r6"},
149 {{al, r6, r6, r6}, false, al, "al r6 r6 r6", "al_r6_r6_r6"},
150 {{al, r6, r7, r6}, false, al, "al r6 r7 r6", "al_r6_r7_r6"},
151 {{al, r7, r0, r7}, false, al, "al r7 r0 r7", "al_r7_r0_r7"},
152 {{al, r7, r1, r7}, false, al, "al r7 r1 r7", "al_r7_r1_r7"},
153 {{al, r7, r2, r7}, false, al, "al r7 r2 r7", "al_r7_r2_r7"},
154 {{al, r7, r3, r7}, false, al, "al r7 r3 r7", "al_r7_r3_r7"},
155 {{al, r7, r4, r7}, false, al, "al r7 r4 r7", "al_r7_r4_r7"},
156 {{al, r7, r5, r7}, false, al, "al r7 r5 r7", "al_r7_r5_r7"},
157 {{al, r7, r6, r7}, false, al, "al r7 r6 r7", "al_r7_r6_r7"},
158 {{al, r7, r7, r7}, false, al, "al r7 r7 r7", "al_r7_r7_r7"}};
159
160 // These headers each contain an array of `TestResult` with the reference output
161 // values. The reference arrays are names `kReference{mnemonic}`.
162 #include "aarch32/traces/assembler-cond-rdlow-rnlow-rmlow-muls-t32.h"
163
164
165 // The maximum number of errors to report in detail for each test.
166 const unsigned kErrorReportLimit = 8;
167
168 typedef void (MacroAssembler::*Fn)(Condition cond,
169 Register rd,
170 Register rn,
171 Register rm);
172
TestHelper(Fn instruction,const char * mnemonic,const TestResult reference[])173 void TestHelper(Fn instruction,
174 const char* mnemonic,
175 const TestResult reference[]) {
176 unsigned total_error_count = 0;
177 MacroAssembler masm(BUF_SIZE);
178
179 masm.UseT32();
180
181 for (unsigned i = 0; i < ARRAY_SIZE(kTests); i++) {
182 // Values to pass to the macro-assembler.
183 Condition cond = kTests[i].operands.cond;
184 Register rd = kTests[i].operands.rd;
185 Register rn = kTests[i].operands.rn;
186 Register rm = kTests[i].operands.rm;
187
188 int32_t start = masm.GetCursorOffset();
189 {
190 // We never generate more that 4 bytes, as IT instructions are only
191 // allowed for narrow encodings.
192 ExactAssemblyScope scope(&masm, 4, ExactAssemblyScope::kMaximumSize);
193 if (kTests[i].in_it_block) {
194 masm.it(kTests[i].it_condition);
195 }
196 (masm.*instruction)(cond, rd, rn, rm);
197 }
198 int32_t end = masm.GetCursorOffset();
199
200 const byte* result_ptr =
201 masm.GetBuffer()->GetOffsetAddress<const byte*>(start);
202 VIXL_ASSERT(start < end);
203 uint32_t result_size = end - start;
204
205 if (Test::generate_test_trace()) {
206 // Print the result bytes.
207 printf("const byte kInstruction_%s_%s[] = {\n",
208 mnemonic,
209 kTests[i].identifier);
210 for (uint32_t j = 0; j < result_size; j++) {
211 if (j == 0) {
212 printf(" 0x%02" PRIx8, result_ptr[j]);
213 } else {
214 printf(", 0x%02" PRIx8, result_ptr[j]);
215 }
216 }
217 // This comment is meant to be used by external tools to validate
218 // the encoding. We can parse the comment to figure out what
219 // instruction this corresponds to.
220 if (kTests[i].in_it_block) {
221 printf(" // It %s; %s %s\n};\n",
222 kTests[i].it_condition.GetName(),
223 mnemonic,
224 kTests[i].operands_description);
225 } else {
226 printf(" // %s %s\n};\n", mnemonic, kTests[i].operands_description);
227 }
228 } else {
229 // Check we've emitted the exact same encoding as present in the
230 // trace file. Only print up to `kErrorReportLimit` errors.
231 if (((result_size != reference[i].size) ||
232 (memcmp(result_ptr, reference[i].encoding, reference[i].size) !=
233 0)) &&
234 (++total_error_count <= kErrorReportLimit)) {
235 printf("Error when testing \"%s\" with operands \"%s\":\n",
236 mnemonic,
237 kTests[i].operands_description);
238 printf(" Expected: ");
239 for (uint32_t j = 0; j < reference[i].size; j++) {
240 if (j == 0) {
241 printf("0x%02" PRIx8, reference[i].encoding[j]);
242 } else {
243 printf(", 0x%02" PRIx8, reference[i].encoding[j]);
244 }
245 }
246 printf("\n");
247 printf(" Found: ");
248 for (uint32_t j = 0; j < result_size; j++) {
249 if (j == 0) {
250 printf("0x%02" PRIx8, result_ptr[j]);
251 } else {
252 printf(", 0x%02" PRIx8, result_ptr[j]);
253 }
254 }
255 printf("\n");
256 }
257 }
258 }
259
260 masm.FinalizeCode();
261
262 if (Test::generate_test_trace()) {
263 // Finalize the trace file by writing the final `TestResult` array
264 // which links all generated instruction encodings.
265 printf("const TestResult kReference%s[] = {\n", mnemonic);
266 for (unsigned i = 0; i < ARRAY_SIZE(kTests); i++) {
267 printf(" {\n");
268 printf(" ARRAY_SIZE(kInstruction_%s_%s),\n",
269 mnemonic,
270 kTests[i].identifier);
271 printf(" kInstruction_%s_%s,\n", mnemonic, kTests[i].identifier);
272 printf(" },\n");
273 }
274 printf("};\n");
275 } else {
276 if (total_error_count > kErrorReportLimit) {
277 printf("%u other errors follow.\n",
278 total_error_count - kErrorReportLimit);
279 }
280 // Crash if the test failed.
281 VIXL_CHECK(total_error_count == 0);
282 }
283 }
284
285 // Instantiate tests for each instruction in the list.
286 #define TEST(mnemonic) \
287 void Test_##mnemonic() { \
288 TestHelper(&MacroAssembler::mnemonic, #mnemonic, kReference##mnemonic); \
289 } \
290 Test test_##mnemonic("AARCH32_ASSEMBLER_COND_RDLOW_RNLOW_RMLOW_" #mnemonic \
291 "_T32", \
292 &Test_##mnemonic);
293 FOREACH_INSTRUCTION(TEST)
294 #undef TEST
295
296 } // namespace
297 #endif
298
299 } // namespace aarch32
300 } // namespace vixl
301