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1 #ifndef _UAPI_MSM_MDP_H_
2 #define _UAPI_MSM_MDP_H_
3 
4 #include <linux/types.h>
5 #include <linux/fb.h>
6 
7 #define MSMFB_IOCTL_MAGIC 'm'
8 #define MSMFB_GRP_DISP          _IOW(MSMFB_IOCTL_MAGIC, 1, unsigned int)
9 #define MSMFB_BLIT              _IOW(MSMFB_IOCTL_MAGIC, 2, unsigned int)
10 #define MSMFB_SUSPEND_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 128, unsigned int)
11 #define MSMFB_RESUME_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 129, unsigned int)
12 #define MSMFB_CURSOR _IOW(MSMFB_IOCTL_MAGIC, 130, struct fb_cursor)
13 #define MSMFB_SET_LUT _IOW(MSMFB_IOCTL_MAGIC, 131, struct fb_cmap)
14 #define MSMFB_HISTOGRAM _IOWR(MSMFB_IOCTL_MAGIC, 132, struct mdp_histogram_data)
15 /* new ioctls's for set/get ccs matrix */
16 #define MSMFB_GET_CCS_MATRIX  _IOWR(MSMFB_IOCTL_MAGIC, 133, struct mdp_ccs)
17 #define MSMFB_SET_CCS_MATRIX  _IOW(MSMFB_IOCTL_MAGIC, 134, struct mdp_ccs)
18 #define MSMFB_OVERLAY_SET       _IOWR(MSMFB_IOCTL_MAGIC, 135, \
19 						struct mdp_overlay)
20 #define MSMFB_OVERLAY_UNSET     _IOW(MSMFB_IOCTL_MAGIC, 136, unsigned int)
21 
22 #define MSMFB_OVERLAY_PLAY      _IOW(MSMFB_IOCTL_MAGIC, 137, \
23 						struct msmfb_overlay_data)
24 #define MSMFB_OVERLAY_QUEUE	MSMFB_OVERLAY_PLAY
25 
26 #define MSMFB_GET_PAGE_PROTECTION _IOR(MSMFB_IOCTL_MAGIC, 138, \
27 					struct mdp_page_protection)
28 #define MSMFB_SET_PAGE_PROTECTION _IOW(MSMFB_IOCTL_MAGIC, 139, \
29 					struct mdp_page_protection)
30 #define MSMFB_OVERLAY_GET      _IOR(MSMFB_IOCTL_MAGIC, 140, \
31 						struct mdp_overlay)
32 #define MSMFB_OVERLAY_PLAY_ENABLE     _IOW(MSMFB_IOCTL_MAGIC, 141, unsigned int)
33 #define MSMFB_OVERLAY_BLT       _IOWR(MSMFB_IOCTL_MAGIC, 142, \
34 						struct msmfb_overlay_blt)
35 #define MSMFB_OVERLAY_BLT_OFFSET     _IOW(MSMFB_IOCTL_MAGIC, 143, unsigned int)
36 #define MSMFB_HISTOGRAM_START	_IOR(MSMFB_IOCTL_MAGIC, 144, \
37 						struct mdp_histogram_start_req)
38 #define MSMFB_HISTOGRAM_STOP	_IOR(MSMFB_IOCTL_MAGIC, 145, unsigned int)
39 #define MSMFB_NOTIFY_UPDATE	_IOWR(MSMFB_IOCTL_MAGIC, 146, unsigned int)
40 
41 #define MSMFB_OVERLAY_3D       _IOWR(MSMFB_IOCTL_MAGIC, 147, \
42 						struct msmfb_overlay_3d)
43 
44 #define MSMFB_MIXER_INFO       _IOWR(MSMFB_IOCTL_MAGIC, 148, \
45 						struct msmfb_mixer_info_req)
46 #define MSMFB_OVERLAY_PLAY_WAIT _IOWR(MSMFB_IOCTL_MAGIC, 149, \
47 						struct msmfb_overlay_data)
48 #define MSMFB_WRITEBACK_INIT _IO(MSMFB_IOCTL_MAGIC, 150)
49 #define MSMFB_WRITEBACK_START _IO(MSMFB_IOCTL_MAGIC, 151)
50 #define MSMFB_WRITEBACK_STOP _IO(MSMFB_IOCTL_MAGIC, 152)
51 #define MSMFB_WRITEBACK_QUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 153, \
52 						struct msmfb_data)
53 #define MSMFB_WRITEBACK_DEQUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 154, \
54 						struct msmfb_data)
55 #define MSMFB_WRITEBACK_TERMINATE _IO(MSMFB_IOCTL_MAGIC, 155)
56 #define MSMFB_MDP_PP _IOWR(MSMFB_IOCTL_MAGIC, 156, struct msmfb_mdp_pp)
57 #define MSMFB_OVERLAY_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 160, unsigned int)
58 #define MSMFB_VSYNC_CTRL  _IOW(MSMFB_IOCTL_MAGIC, 161, unsigned int)
59 #define MSMFB_BUFFER_SYNC  _IOW(MSMFB_IOCTL_MAGIC, 162, struct mdp_buf_sync)
60 #define MSMFB_OVERLAY_COMMIT      _IO(MSMFB_IOCTL_MAGIC, 163)
61 #define MSMFB_DISPLAY_COMMIT      _IOW(MSMFB_IOCTL_MAGIC, 164, \
62 						struct mdp_display_commit)
63 #define MSMFB_METADATA_SET  _IOW(MSMFB_IOCTL_MAGIC, 165, struct msmfb_metadata)
64 #define MSMFB_METADATA_GET  _IOW(MSMFB_IOCTL_MAGIC, 166, struct msmfb_metadata)
65 #define MSMFB_WRITEBACK_SET_MIRRORING_HINT _IOW(MSMFB_IOCTL_MAGIC, 167, \
66 						unsigned int)
67 #define MSMFB_ASYNC_BLIT              _IOW(MSMFB_IOCTL_MAGIC, 168, unsigned int)
68 #define MSMFB_OVERLAY_PREPARE		_IOWR(MSMFB_IOCTL_MAGIC, 169, \
69 						struct mdp_overlay_list)
70 #define MSMFB_LPM_ENABLE	_IOWR(MSMFB_IOCTL_MAGIC, 170, unsigned int)
71 #define MSMFB_MDP_PP_GET_FEATURE_VERSION _IOWR(MSMFB_IOCTL_MAGIC, 171, \
72 					      struct mdp_pp_feature_version)
73 #define MSMFB_SET_PERSISTENCE_MODE	_IOWR(MSMFB_IOCTL_MAGIC, 172, unsigned int)
74 
75 #define FB_TYPE_3D_PANEL 0x10101010
76 #define MDP_IMGTYPE2_START 0x10000
77 #define MSMFB_DRIVER_VERSION	0xF9E8D701
78 /* Maximum number of formats supported by MDP*/
79 #define MDP_IMGTYPE_END 0x100
80 
81 /* HW Revisions for different MDSS targets */
82 #define MDSS_GET_MAJOR(rev)		((rev) >> 28)
83 #define MDSS_GET_MINOR(rev)		(((rev) >> 16) & 0xFFF)
84 #define MDSS_GET_STEP(rev)		((rev) & 0xFFFF)
85 #define MDSS_GET_MAJOR_MINOR(rev)	((rev) >> 16)
86 
87 #define IS_MDSS_MAJOR_MINOR_SAME(rev1, rev2)	\
88 	(MDSS_GET_MAJOR_MINOR((rev1)) == MDSS_GET_MAJOR_MINOR((rev2)))
89 
90 #define MDSS_MDP_REV(major, minor, step)	\
91 	((((major) & 0x000F) << 28) |		\
92 	 (((minor) & 0x0FFF) << 16) |		\
93 	 ((step)   & 0xFFFF))
94 
95 #define MDSS_MDP_HW_REV_100	MDSS_MDP_REV(1, 0, 0) /* 8974 v1.0 */
96 #define MDSS_MDP_HW_REV_101	MDSS_MDP_REV(1, 1, 0) /* 8x26 v1.0 */
97 #define MDSS_MDP_HW_REV_101_1	MDSS_MDP_REV(1, 1, 1) /* 8x26 v2.0, 8926 v1.0 */
98 #define MDSS_MDP_HW_REV_101_2	MDSS_MDP_REV(1, 1, 2) /* 8926 v2.0 */
99 #define MDSS_MDP_HW_REV_102	MDSS_MDP_REV(1, 2, 0) /* 8974 v2.0 */
100 #define MDSS_MDP_HW_REV_102_1	MDSS_MDP_REV(1, 2, 1) /* 8974 v3.0 (Pro) */
101 #define MDSS_MDP_HW_REV_103	MDSS_MDP_REV(1, 3, 0) /* 8084 v1.0 */
102 #define MDSS_MDP_HW_REV_103_1	MDSS_MDP_REV(1, 3, 1) /* 8084 v1.1 */
103 #define MDSS_MDP_HW_REV_105	MDSS_MDP_REV(1, 5, 0) /* 8994 v1.0 */
104 #define MDSS_MDP_HW_REV_106	MDSS_MDP_REV(1, 6, 0) /* 8916 v1.0 */
105 #define MDSS_MDP_HW_REV_107	MDSS_MDP_REV(1, 7, 0) /* 8996 v1 */
106 #define MDSS_MDP_HW_REV_107_1	MDSS_MDP_REV(1, 7, 1) /* 8996 v2 */
107 #define MDSS_MDP_HW_REV_107_2	MDSS_MDP_REV(1, 7, 2) /* 8996 v3 */
108 #define MDSS_MDP_HW_REV_108	MDSS_MDP_REV(1, 8, 0) /* 8939 v1.0 */
109 #define MDSS_MDP_HW_REV_109	MDSS_MDP_REV(1, 9, 0) /* 8994 v2.0 */
110 #define MDSS_MDP_HW_REV_110	MDSS_MDP_REV(1, 10, 0) /* 8992 v1.0 */
111 #define MDSS_MDP_HW_REV_200	MDSS_MDP_REV(2, 0, 0) /* 8092 v1.0 */
112 #define MDSS_MDP_HW_REV_112	MDSS_MDP_REV(1, 12, 0) /* 8952 v1.0 */
113 #define MDSS_MDP_HW_REV_114	MDSS_MDP_REV(1, 14, 0) /* 8937 v1.0 */
114 #define MDSS_MDP_HW_REV_115	MDSS_MDP_REV(1, 15, 0) /* msm8917 */
115 #define MDSS_MDP_HW_REV_116	MDSS_MDP_REV(1, 16, 0) /* msm8953 */
116 #define MDSS_MDP_HW_REV_300	MDSS_MDP_REV(3, 0, 0)  /* msmcobalt */
117 #define MDSS_MDP_HW_REV_301	MDSS_MDP_REV(3, 0, 1)  /* msmcobalt v1.0 */
118 
119 enum {
120 	NOTIFY_UPDATE_INIT,
121 	NOTIFY_UPDATE_DEINIT,
122 	NOTIFY_UPDATE_START,
123 	NOTIFY_UPDATE_STOP,
124 	NOTIFY_UPDATE_POWER_OFF,
125 };
126 
127 enum {
128 	NOTIFY_TYPE_NO_UPDATE,
129 	NOTIFY_TYPE_SUSPEND,
130 	NOTIFY_TYPE_UPDATE,
131 	NOTIFY_TYPE_BL_UPDATE,
132 	NOTIFY_TYPE_BL_AD_ATTEN_UPDATE,
133 };
134 
135 enum {
136 	MDP_RGB_565,      /* RGB 565 planer */
137 	MDP_XRGB_8888,    /* RGB 888 padded */
138 	MDP_Y_CBCR_H2V2,  /* Y and CbCr, pseudo planer w/ Cb is in MSB */
139 	MDP_Y_CBCR_H2V2_ADRENO,
140 	MDP_ARGB_8888,    /* ARGB 888 */
141 	MDP_RGB_888,      /* RGB 888 planer */
142 	MDP_Y_CRCB_H2V2,  /* Y and CrCb, pseudo planer w/ Cr is in MSB */
143 	MDP_YCRYCB_H2V1,  /* YCrYCb interleave */
144 	MDP_CBYCRY_H2V1,  /* CbYCrY interleave */
145 	MDP_Y_CRCB_H2V1,  /* Y and CrCb, pseduo planer w/ Cr is in MSB */
146 	MDP_Y_CBCR_H2V1,   /* Y and CrCb, pseduo planer w/ Cr is in MSB */
147 	MDP_Y_CRCB_H1V2,
148 	MDP_Y_CBCR_H1V2,
149 	MDP_RGBA_8888,    /* ARGB 888 */
150 	MDP_BGRA_8888,	  /* ABGR 888 */
151 	MDP_RGBX_8888,	  /* RGBX 888 */
152 	MDP_Y_CRCB_H2V2_TILE,  /* Y and CrCb, pseudo planer tile */
153 	MDP_Y_CBCR_H2V2_TILE,  /* Y and CbCr, pseudo planer tile */
154 	MDP_Y_CR_CB_H2V2,  /* Y, Cr and Cb, planar */
155 	MDP_Y_CR_CB_GH2V2,  /* Y, Cr and Cb, planar aligned to Android YV12 */
156 	MDP_Y_CB_CR_H2V2,  /* Y, Cb and Cr, planar */
157 	MDP_Y_CRCB_H1V1,  /* Y and CrCb, pseduo planer w/ Cr is in MSB */
158 	MDP_Y_CBCR_H1V1,  /* Y and CbCr, pseduo planer w/ Cb is in MSB */
159 	MDP_YCRCB_H1V1,   /* YCrCb interleave */
160 	MDP_YCBCR_H1V1,   /* YCbCr interleave */
161 	MDP_BGR_565,      /* BGR 565 planer */
162 	MDP_BGR_888,      /* BGR 888 */
163 	MDP_Y_CBCR_H2V2_VENUS,
164 	MDP_BGRX_8888,   /* BGRX 8888 */
165 	MDP_RGBA_8888_TILE,	  /* RGBA 8888 in tile format */
166 	MDP_ARGB_8888_TILE,	  /* ARGB 8888 in tile format */
167 	MDP_ABGR_8888_TILE,	  /* ABGR 8888 in tile format */
168 	MDP_BGRA_8888_TILE,	  /* BGRA 8888 in tile format */
169 	MDP_RGBX_8888_TILE,	  /* RGBX 8888 in tile format */
170 	MDP_XRGB_8888_TILE,	  /* XRGB 8888 in tile format */
171 	MDP_XBGR_8888_TILE,	  /* XBGR 8888 in tile format */
172 	MDP_BGRX_8888_TILE,	  /* BGRX 8888 in tile format */
173 	MDP_YCBYCR_H2V1,  /* YCbYCr interleave */
174 	MDP_RGB_565_TILE,	  /* RGB 565 in tile format */
175 	MDP_BGR_565_TILE,	  /* BGR 565 in tile format */
176 	MDP_ARGB_1555,	/*ARGB 1555*/
177 	MDP_RGBA_5551,	/*RGBA 5551*/
178 	MDP_ARGB_4444,	/*ARGB 4444*/
179 	MDP_RGBA_4444,	/*RGBA 4444*/
180 	MDP_RGB_565_UBWC,
181 	MDP_RGBA_8888_UBWC,
182 	MDP_Y_CBCR_H2V2_UBWC,
183 	MDP_RGBX_8888_UBWC,
184 	MDP_Y_CRCB_H2V2_VENUS,
185 	MDP_IMGTYPE_LIMIT,
186 	MDP_RGB_BORDERFILL,	/* border fill pipe */
187 	MDP_XRGB_1555,
188 	MDP_RGBX_5551,
189 	MDP_XRGB_4444,
190 	MDP_RGBX_4444,
191 	MDP_ABGR_1555,
192 	MDP_BGRA_5551,
193 	MDP_XBGR_1555,
194 	MDP_BGRX_5551,
195 	MDP_ABGR_4444,
196 	MDP_BGRA_4444,
197 	MDP_XBGR_4444,
198 	MDP_BGRX_4444,
199 	MDP_ABGR_8888,
200 	MDP_XBGR_8888,
201 	MDP_RGBA_1010102,
202 	MDP_ARGB_2101010,
203 	MDP_RGBX_1010102,
204 	MDP_XRGB_2101010,
205 	MDP_BGRA_1010102,
206 	MDP_ABGR_2101010,
207 	MDP_BGRX_1010102,
208 	MDP_XBGR_2101010,
209 	MDP_RGBA_1010102_UBWC,
210 	MDP_RGBX_1010102_UBWC,
211 	MDP_Y_CBCR_H2V2_P010,
212 	MDP_Y_CBCR_H2V2_TP10_UBWC,
213 	MDP_CRYCBY_H2V1,  /* CrYCbY interleave */
214 	MDP_IMGTYPE_LIMIT1 = MDP_IMGTYPE_END,
215 	MDP_FB_FORMAT = MDP_IMGTYPE2_START,    /* framebuffer format */
216 	MDP_IMGTYPE_LIMIT2 /* Non valid image type after this enum */
217 };
218 
219 #define MDP_CRYCBY_H2V1 MDP_CRYCBY_H2V1
220 
221 enum {
222 	PMEM_IMG,
223 	FB_IMG,
224 };
225 
226 enum {
227 	HSIC_HUE = 0,
228 	HSIC_SAT,
229 	HSIC_INT,
230 	HSIC_CON,
231 	NUM_HSIC_PARAM,
232 };
233 
234 enum mdss_mdp_max_bw_mode {
235 	MDSS_MAX_BW_LIMIT_DEFAULT = 0x1,
236 	MDSS_MAX_BW_LIMIT_CAMERA = 0x2,
237 	MDSS_MAX_BW_LIMIT_HFLIP = 0x4,
238 	MDSS_MAX_BW_LIMIT_VFLIP = 0x8,
239 };
240 
241 #define MDSS_MDP_ROT_ONLY		0x80
242 #define MDSS_MDP_RIGHT_MIXER		0x100
243 #define MDSS_MDP_DUAL_PIPE		0x200
244 
245 /* mdp_blit_req flag values */
246 #define MDP_ROT_NOP 0
247 #define MDP_FLIP_LR 0x1
248 #define MDP_FLIP_UD 0x2
249 #define MDP_ROT_90 0x4
250 #define MDP_ROT_180 (MDP_FLIP_UD|MDP_FLIP_LR)
251 #define MDP_ROT_270 (MDP_ROT_90|MDP_FLIP_UD|MDP_FLIP_LR)
252 #define MDP_DITHER 0x8
253 #define MDP_BLUR 0x10
254 #define MDP_BLEND_FG_PREMULT 0x20000
255 #define MDP_IS_FG 0x40000
256 #define MDP_SOLID_FILL 0x00000020
257 #define MDP_VPU_PIPE 0x00000040
258 #define MDP_DEINTERLACE 0x80000000
259 #define MDP_SHARPENING  0x40000000
260 #define MDP_NO_DMA_BARRIER_START	0x20000000
261 #define MDP_NO_DMA_BARRIER_END		0x10000000
262 #define MDP_NO_BLIT			0x08000000
263 #define MDP_BLIT_WITH_DMA_BARRIERS	0x000
264 #define MDP_BLIT_WITH_NO_DMA_BARRIERS    \
265 	(MDP_NO_DMA_BARRIER_START | MDP_NO_DMA_BARRIER_END)
266 #define MDP_BLIT_SRC_GEM                0x04000000
267 #define MDP_BLIT_DST_GEM                0x02000000
268 #define MDP_BLIT_NON_CACHED		0x01000000
269 #define MDP_OV_PIPE_SHARE		0x00800000
270 #define MDP_DEINTERLACE_ODD		0x00400000
271 #define MDP_OV_PLAY_NOWAIT		0x00200000
272 #define MDP_SOURCE_ROTATED_90		0x00100000
273 #define MDP_OVERLAY_PP_CFG_EN		0x00080000
274 #define MDP_BACKEND_COMPOSITION		0x00040000
275 #define MDP_BORDERFILL_SUPPORTED	0x00010000
276 #define MDP_SECURE_OVERLAY_SESSION      0x00008000
277 #define MDP_SECURE_DISPLAY_OVERLAY_SESSION	0x00002000
278 #define MDP_OV_PIPE_FORCE_DMA		0x00004000
279 #define MDP_MEMORY_ID_TYPE_FB		0x00001000
280 #define MDP_BWC_EN			0x00000400
281 #define MDP_DECIMATION_EN		0x00000800
282 #define MDP_SMP_FORCE_ALLOC		0x00200000
283 #define MDP_TRANSP_NOP 0xffffffff
284 #define MDP_ALPHA_NOP 0xff
285 
286 #define MDP_FB_PAGE_PROTECTION_NONCACHED         (0)
287 #define MDP_FB_PAGE_PROTECTION_WRITECOMBINE      (1)
288 #define MDP_FB_PAGE_PROTECTION_WRITETHROUGHCACHE (2)
289 #define MDP_FB_PAGE_PROTECTION_WRITEBACKCACHE    (3)
290 #define MDP_FB_PAGE_PROTECTION_WRITEBACKWACACHE  (4)
291 /* Sentinel: Don't use! */
292 #define MDP_FB_PAGE_PROTECTION_INVALID           (5)
293 /* Count of the number of MDP_FB_PAGE_PROTECTION_... values. */
294 #define MDP_NUM_FB_PAGE_PROTECTION_VALUES        (5)
295 
296 struct mdp_rect {
297 	uint32_t x;
298 	uint32_t y;
299 	uint32_t w;
300 	uint32_t h;
301 };
302 
303 struct mdp_img {
304 	uint32_t width;
305 	uint32_t height;
306 	uint32_t format;
307 	uint32_t offset;
308 	int memory_id;		/* the file descriptor */
309 	uint32_t priv;
310 };
311 
312 struct mult_factor {
313 	uint32_t numer;
314 	uint32_t denom;
315 };
316 
317 /*
318  * {3x3} + {3} ccs matrix
319  */
320 
321 #define MDP_CCS_RGB2YUV 	0
322 #define MDP_CCS_YUV2RGB 	1
323 
324 #define MDP_CCS_SIZE	9
325 #define MDP_BV_SIZE	3
326 
327 struct mdp_ccs {
328 	int direction;			/* MDP_CCS_RGB2YUV or YUV2RGB */
329 	uint16_t ccs[MDP_CCS_SIZE];	/* 3x3 color coefficients */
330 	uint16_t bv[MDP_BV_SIZE];	/* 1x3 bias vector */
331 };
332 
333 struct mdp_csc {
334 	int id;
335 	uint32_t csc_mv[9];
336 	uint32_t csc_pre_bv[3];
337 	uint32_t csc_post_bv[3];
338 	uint32_t csc_pre_lv[6];
339 	uint32_t csc_post_lv[6];
340 };
341 
342 /* The version of the mdp_blit_req structure so that
343  * user applications can selectively decide which functionality
344  * to include
345  */
346 
347 #define MDP_BLIT_REQ_VERSION 3
348 
349 struct color {
350 	uint32_t r;
351 	uint32_t g;
352 	uint32_t b;
353 	uint32_t alpha;
354 };
355 
356 struct mdp_blit_req {
357 	struct mdp_img src;
358 	struct mdp_img dst;
359 	struct mdp_rect src_rect;
360 	struct mdp_rect dst_rect;
361 	struct color const_color;
362 	uint32_t alpha;
363 	uint32_t transp_mask;
364 	uint32_t flags;
365 	int sharpening_strength;  /* -127 <--> 127, default 64 */
366 	uint8_t color_space;
367 	uint32_t fps;
368 };
369 
370 struct mdp_blit_req_list {
371 	uint32_t count;
372 	struct mdp_blit_req req[];
373 };
374 
375 #define MSMFB_DATA_VERSION 2
376 
377 struct msmfb_data {
378 	uint32_t offset;
379 	int memory_id;
380 	int id;
381 	uint32_t flags;
382 	uint32_t priv;
383 	uint32_t iova;
384 };
385 
386 #define MSMFB_NEW_REQUEST -1
387 
388 struct msmfb_overlay_data {
389 	uint32_t id;
390 	struct msmfb_data data;
391 	uint32_t version_key;
392 	struct msmfb_data plane1_data;
393 	struct msmfb_data plane2_data;
394 	struct msmfb_data dst_data;
395 };
396 
397 struct msmfb_img {
398 	uint32_t width;
399 	uint32_t height;
400 	uint32_t format;
401 };
402 
403 #define MSMFB_WRITEBACK_DEQUEUE_BLOCKING 0x1
404 struct msmfb_writeback_data {
405 	struct msmfb_data buf_info;
406 	struct msmfb_img img;
407 };
408 
409 #define MDP_PP_OPS_ENABLE 0x1
410 #define MDP_PP_OPS_READ 0x2
411 #define MDP_PP_OPS_WRITE 0x4
412 #define MDP_PP_OPS_DISABLE 0x8
413 #define MDP_PP_IGC_FLAG_ROM0	0x10
414 #define MDP_PP_IGC_FLAG_ROM1	0x20
415 
416 
417 #define MDSS_PP_DSPP_CFG	0x000
418 #define MDSS_PP_SSPP_CFG	0x100
419 #define MDSS_PP_LM_CFG	0x200
420 #define MDSS_PP_WB_CFG	0x300
421 
422 #define MDSS_PP_ARG_MASK	0x3C00
423 #define MDSS_PP_ARG_NUM		4
424 #define MDSS_PP_ARG_SHIFT	10
425 #define MDSS_PP_LOCATION_MASK	0x0300
426 #define MDSS_PP_LOGICAL_MASK	0x00FF
427 
428 #define MDSS_PP_ADD_ARG(var, arg) ((var) | (0x1 << (MDSS_PP_ARG_SHIFT + (arg))))
429 #define PP_ARG(x, var) ((var) & (0x1 << (MDSS_PP_ARG_SHIFT + (x))))
430 #define PP_LOCAT(var) ((var) & MDSS_PP_LOCATION_MASK)
431 #define PP_BLOCK(var) ((var) & MDSS_PP_LOGICAL_MASK)
432 
433 
434 struct mdp_qseed_cfg {
435 	uint32_t table_num;
436 	uint32_t ops;
437 	uint32_t len;
438 	uint32_t *data;
439 };
440 
441 struct mdp_sharp_cfg {
442 	uint32_t flags;
443 	uint32_t strength;
444 	uint32_t edge_thr;
445 	uint32_t smooth_thr;
446 	uint32_t noise_thr;
447 };
448 
449 struct mdp_qseed_cfg_data {
450 	uint32_t block;
451 	struct mdp_qseed_cfg qseed_data;
452 };
453 
454 #define MDP_OVERLAY_PP_CSC_CFG         0x1
455 #define MDP_OVERLAY_PP_QSEED_CFG       0x2
456 #define MDP_OVERLAY_PP_PA_CFG          0x4
457 #define MDP_OVERLAY_PP_IGC_CFG         0x8
458 #define MDP_OVERLAY_PP_SHARP_CFG       0x10
459 #define MDP_OVERLAY_PP_HIST_CFG        0x20
460 #define MDP_OVERLAY_PP_HIST_LUT_CFG    0x40
461 #define MDP_OVERLAY_PP_PA_V2_CFG       0x80
462 #define MDP_OVERLAY_PP_PCC_CFG	       0x100
463 
464 #define MDP_CSC_FLAG_ENABLE	0x1
465 #define MDP_CSC_FLAG_YUV_IN	0x2
466 #define MDP_CSC_FLAG_YUV_OUT	0x4
467 
468 #define MDP_CSC_MATRIX_COEFF_SIZE	9
469 #define MDP_CSC_CLAMP_SIZE		6
470 #define MDP_CSC_BIAS_SIZE		3
471 
472 struct mdp_csc_cfg {
473 	/* flags for enable CSC, toggling RGB,YUV input/output */
474 	uint32_t flags;
475 	uint32_t csc_mv[MDP_CSC_MATRIX_COEFF_SIZE];
476 	uint32_t csc_pre_bv[MDP_CSC_BIAS_SIZE];
477 	uint32_t csc_post_bv[MDP_CSC_BIAS_SIZE];
478 	uint32_t csc_pre_lv[MDP_CSC_CLAMP_SIZE];
479 	uint32_t csc_post_lv[MDP_CSC_CLAMP_SIZE];
480 };
481 
482 struct mdp_csc_cfg_data {
483 	uint32_t block;
484 	struct mdp_csc_cfg csc_data;
485 };
486 
487 struct mdp_pa_cfg {
488 	uint32_t flags;
489 	uint32_t hue_adj;
490 	uint32_t sat_adj;
491 	uint32_t val_adj;
492 	uint32_t cont_adj;
493 };
494 
495 struct mdp_pa_mem_col_cfg {
496 	uint32_t color_adjust_p0;
497 	uint32_t color_adjust_p1;
498 	uint32_t hue_region;
499 	uint32_t sat_region;
500 	uint32_t val_region;
501 };
502 
503 #define MDP_SIX_ZONE_LUT_SIZE		384
504 
505 /* PA Write/Read extension flags */
506 #define MDP_PP_PA_HUE_ENABLE		0x10
507 #define MDP_PP_PA_SAT_ENABLE		0x20
508 #define MDP_PP_PA_VAL_ENABLE		0x40
509 #define MDP_PP_PA_CONT_ENABLE		0x80
510 #define MDP_PP_PA_SIX_ZONE_ENABLE	0x100
511 #define MDP_PP_PA_SKIN_ENABLE		0x200
512 #define MDP_PP_PA_SKY_ENABLE		0x400
513 #define MDP_PP_PA_FOL_ENABLE		0x800
514 
515 /* PA masks */
516 /* Masks used in PA v1_7 only */
517 #define MDP_PP_PA_MEM_PROT_HUE_EN	0x1
518 #define MDP_PP_PA_MEM_PROT_SAT_EN	0x2
519 #define MDP_PP_PA_MEM_PROT_VAL_EN	0x4
520 #define MDP_PP_PA_MEM_PROT_CONT_EN	0x8
521 #define MDP_PP_PA_MEM_PROT_SIX_EN	0x10
522 #define MDP_PP_PA_MEM_PROT_BLEND_EN	0x20
523 /* Masks used in all PAv2 versions */
524 #define MDP_PP_PA_HUE_MASK		0x1000
525 #define MDP_PP_PA_SAT_MASK		0x2000
526 #define MDP_PP_PA_VAL_MASK		0x4000
527 #define MDP_PP_PA_CONT_MASK		0x8000
528 #define MDP_PP_PA_SIX_ZONE_HUE_MASK	0x10000
529 #define MDP_PP_PA_SIX_ZONE_SAT_MASK	0x20000
530 #define MDP_PP_PA_SIX_ZONE_VAL_MASK	0x40000
531 #define MDP_PP_PA_MEM_COL_SKIN_MASK	0x80000
532 #define MDP_PP_PA_MEM_COL_SKY_MASK	0x100000
533 #define MDP_PP_PA_MEM_COL_FOL_MASK	0x200000
534 #define MDP_PP_PA_MEM_PROTECT_EN	0x400000
535 #define MDP_PP_PA_SAT_ZERO_EXP_EN	0x800000
536 
537 /* Flags for setting PA saturation and value hold */
538 #define MDP_PP_PA_LEFT_HOLD		0x1
539 #define MDP_PP_PA_RIGHT_HOLD		0x2
540 
541 struct mdp_pa_v2_data {
542 	/* Mask bits for PA features */
543 	uint32_t flags;
544 	uint32_t global_hue_adj;
545 	uint32_t global_sat_adj;
546 	uint32_t global_val_adj;
547 	uint32_t global_cont_adj;
548 	struct mdp_pa_mem_col_cfg skin_cfg;
549 	struct mdp_pa_mem_col_cfg sky_cfg;
550 	struct mdp_pa_mem_col_cfg fol_cfg;
551 	uint32_t six_zone_len;
552 	uint32_t six_zone_thresh;
553 	uint32_t *six_zone_curve_p0;
554 	uint32_t *six_zone_curve_p1;
555 };
556 
557 struct mdp_pa_mem_col_data_v1_7 {
558 	uint32_t color_adjust_p0;
559 	uint32_t color_adjust_p1;
560 	uint32_t color_adjust_p2;
561 	uint32_t blend_gain;
562 	uint8_t sat_hold;
563 	uint8_t val_hold;
564 	uint32_t hue_region;
565 	uint32_t sat_region;
566 	uint32_t val_region;
567 };
568 
569 struct mdp_pa_data_v1_7 {
570 	uint32_t mode;
571 	uint32_t global_hue_adj;
572 	uint32_t global_sat_adj;
573 	uint32_t global_val_adj;
574 	uint32_t global_cont_adj;
575 	struct mdp_pa_mem_col_data_v1_7 skin_cfg;
576 	struct mdp_pa_mem_col_data_v1_7 sky_cfg;
577 	struct mdp_pa_mem_col_data_v1_7 fol_cfg;
578 	uint32_t six_zone_thresh;
579 	uint32_t six_zone_adj_p0;
580 	uint32_t six_zone_adj_p1;
581 	uint8_t six_zone_sat_hold;
582 	uint8_t six_zone_val_hold;
583 	uint32_t six_zone_len;
584 	uint32_t *six_zone_curve_p0;
585 	uint32_t *six_zone_curve_p1;
586 };
587 
588 
589 struct mdp_pa_v2_cfg_data {
590 	uint32_t version;
591 	uint32_t block;
592 	uint32_t flags;
593 	struct mdp_pa_v2_data pa_v2_data;
594 	void *cfg_payload;
595 };
596 
597 
598 enum {
599 	mdp_igc_rec601 = 1,
600 	mdp_igc_rec709,
601 	mdp_igc_srgb,
602 	mdp_igc_custom,
603 	mdp_igc_rec_max,
604 };
605 
606 struct mdp_igc_lut_data {
607 	uint32_t block;
608 	uint32_t version;
609 	uint32_t len, ops;
610 	uint32_t *c0_c1_data;
611 	uint32_t *c2_data;
612 	void *cfg_payload;
613 };
614 
615 struct mdp_igc_lut_data_v1_7 {
616 	uint32_t table_fmt;
617 	uint32_t len;
618 	uint32_t *c0_c1_data;
619 	uint32_t *c2_data;
620 };
621 
622 struct mdp_histogram_cfg {
623 	uint32_t ops;
624 	uint32_t block;
625 	uint8_t frame_cnt;
626 	uint8_t bit_mask;
627 	uint16_t num_bins;
628 };
629 
630 struct mdp_hist_lut_data_v1_7 {
631 	uint32_t len;
632 	uint32_t *data;
633 };
634 
635 struct mdp_hist_lut_data {
636 	uint32_t block;
637 	uint32_t version;
638 	uint32_t hist_lut_first;
639 	uint32_t ops;
640 	uint32_t len;
641 	uint32_t *data;
642 	void *cfg_payload;
643 };
644 
645 struct mdp_pcc_coeff {
646 	uint32_t c, r, g, b, rr, gg, bb, rg, gb, rb, rgb_0, rgb_1;
647 };
648 
649 struct mdp_pcc_coeff_v1_7 {
650 	uint32_t c, r, g, b, rg, gb, rb, rgb;
651 };
652 
653 struct mdp_pcc_data_v1_7 {
654 	struct mdp_pcc_coeff_v1_7 r, g, b;
655 };
656 
657 struct mdp_pcc_cfg_data {
658 	uint32_t version;
659 	uint32_t block;
660 	uint32_t ops;
661 	struct mdp_pcc_coeff r, g, b;
662 	void *cfg_payload;
663 };
664 
665 enum {
666 	mdp_lut_igc,
667 	mdp_lut_pgc,
668 	mdp_lut_hist,
669 	mdp_lut_rgb,
670 	mdp_lut_max,
671 };
672 struct mdp_overlay_pp_params {
673 	uint32_t config_ops;
674 	struct mdp_csc_cfg csc_cfg;
675 	struct mdp_qseed_cfg qseed_cfg[2];
676 	struct mdp_pa_cfg pa_cfg;
677 	struct mdp_pa_v2_data pa_v2_cfg;
678 	struct mdp_igc_lut_data igc_cfg;
679 	struct mdp_sharp_cfg sharp_cfg;
680 	struct mdp_histogram_cfg hist_cfg;
681 	struct mdp_hist_lut_data hist_lut_cfg;
682 	/* PAv2 cfg data for PA 2.x versions */
683 	struct mdp_pa_v2_cfg_data pa_v2_cfg_data;
684 	struct mdp_pcc_cfg_data pcc_cfg_data;
685 };
686 
687 /**
688  * enum mdss_mdp_blend_op - Different blend operations set by userspace
689  *
690  * @BLEND_OP_NOT_DEFINED:    No blend operation defined for the layer.
691  * @BLEND_OP_OPAQUE:         Apply a constant blend operation. The layer
692  *                           would appear opaque in case fg plane alpha is
693  *                           0xff.
694  * @BLEND_OP_PREMULTIPLIED:  Apply source over blend rule. Layer already has
695  *                           alpha pre-multiplication done. If fg plane alpha
696  *                           is less than 0xff, apply modulation as well. This
697  *                           operation is intended on layers having alpha
698  *                           channel.
699  * @BLEND_OP_COVERAGE:       Apply source over blend rule. Layer is not alpha
700  *                           pre-multiplied. Apply pre-multiplication. If fg
701  *                           plane alpha is less than 0xff, apply modulation as
702  *                           well.
703  * @BLEND_OP_MAX:            Used to track maximum blend operation possible by
704  *                           mdp.
705  */
706 enum mdss_mdp_blend_op {
707 	BLEND_OP_NOT_DEFINED = 0,
708 	BLEND_OP_OPAQUE,
709 	BLEND_OP_PREMULTIPLIED,
710 	BLEND_OP_COVERAGE,
711 	BLEND_OP_MAX,
712 };
713 
714 #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci))
715 #define MAX_PLANES	4
716 struct mdp_scale_data {
717 	uint8_t enable_pxl_ext;
718 
719 	int init_phase_x[MAX_PLANES];
720 	int phase_step_x[MAX_PLANES];
721 	int init_phase_y[MAX_PLANES];
722 	int phase_step_y[MAX_PLANES];
723 
724 	int num_ext_pxls_left[MAX_PLANES];
725 	int num_ext_pxls_right[MAX_PLANES];
726 	int num_ext_pxls_top[MAX_PLANES];
727 	int num_ext_pxls_btm[MAX_PLANES];
728 
729 	int left_ftch[MAX_PLANES];
730 	int left_rpt[MAX_PLANES];
731 	int right_ftch[MAX_PLANES];
732 	int right_rpt[MAX_PLANES];
733 
734 	int top_rpt[MAX_PLANES];
735 	int btm_rpt[MAX_PLANES];
736 	int top_ftch[MAX_PLANES];
737 	int btm_ftch[MAX_PLANES];
738 
739 	uint32_t roi_w[MAX_PLANES];
740 };
741 
742 /**
743  * enum mdp_overlay_pipe_type - Different pipe type set by userspace
744  *
745  * @PIPE_TYPE_AUTO:    Not specified, pipe will be selected according to flags.
746  * @PIPE_TYPE_VIG:     VIG pipe.
747  * @PIPE_TYPE_RGB:     RGB pipe.
748  * @PIPE_TYPE_DMA:     DMA pipe.
749  * @PIPE_TYPE_CURSOR:  CURSOR pipe.
750  * @PIPE_TYPE_MAX:     Used to track maximum number of pipe type.
751  */
752 enum mdp_overlay_pipe_type {
753 	PIPE_TYPE_AUTO = 0,
754 	PIPE_TYPE_VIG,
755 	PIPE_TYPE_RGB,
756 	PIPE_TYPE_DMA,
757 	PIPE_TYPE_CURSOR,
758 	PIPE_TYPE_MAX,
759 };
760 
761 /**
762  * struct mdp_overlay - overlay surface structure
763  * @src:	Source image information (width, height, format).
764  * @src_rect:	Source crop rectangle, portion of image that will be fetched.
765  *		This should always be within boundaries of source image.
766  * @dst_rect:	Destination rectangle, the position and size of image on screen.
767  *		This should always be within panel boundaries.
768  * @z_order:	Blending stage to occupy in display, if multiple layers are
769  *		present, highest z_order usually means the top most visible
770  *		layer. The range acceptable is from 0-3 to support blending
771  *		up to 4 layers.
772  * @is_fg:	This flag is used to disable blending of any layers with z_order
773  *		less than this overlay. It means that any layers with z_order
774  *		less than this layer will not be blended and will be replaced
775  *		by the background border color.
776  * @alpha:	Used to set plane opacity. The range can be from 0-255, where
777  *		0 means completely transparent and 255 means fully opaque.
778  * @transp_mask: Color used as color key for transparency. Any pixel in fetched
779  *		image matching this color will be transparent when blending.
780  *		The color should be in same format as the source image format.
781  * @flags:	This is used to customize operation of overlay. See MDP flags
782  *		for more information.
783  * @pipe_type:  Used to specify the type of overlay pipe.
784  * @user_data:	DEPRECATED* Used to store user application specific information.
785  * @bg_color:	Solid color used to fill the overlay surface when no source
786  *		buffer is provided.
787  * @horz_deci:	Horizontal decimation value, this indicates the amount of pixels
788  *		dropped for each pixel that is fetched from a line. The value
789  *		given should be power of two of decimation amount.
790  *		0: no decimation
791  *		1: decimate by 2 (drop 1 pixel for each pixel fetched)
792  *		2: decimate by 4 (drop 3 pixels for each pixel fetched)
793  *		3: decimate by 8 (drop 7 pixels for each pixel fetched)
794  *		4: decimate by 16 (drop 15 pixels for each pixel fetched)
795  * @vert_deci:	Vertical decimation value, this indicates the amount of lines
796  *		dropped for each line that is fetched from overlay. The value
797  *		given should be power of two of decimation amount.
798  *		0: no decimation
799  *		1: decimation by 2 (drop 1 line for each line fetched)
800  *		2: decimation by 4 (drop 3 lines for each line fetched)
801  *		3: decimation by 8 (drop 7 lines for each line fetched)
802  *		4: decimation by 16 (drop 15 lines for each line fetched)
803  * @overlay_pp_cfg: Overlay post processing configuration, for more information
804  *		see struct mdp_overlay_pp_params.
805  * @priority:	Priority is returned by the driver when overlay is set for the
806  *		first time. It indicates the priority of the underlying pipe
807  *		serving the overlay. This priority can be used by user-space
808  *		in source split when pipes are re-used and shuffled around to
809  *		reduce fallbacks.
810  */
811 struct mdp_overlay {
812 	struct msmfb_img src;
813 	struct mdp_rect src_rect;
814 	struct mdp_rect dst_rect;
815 	uint32_t z_order;	/* stage number */
816 	uint32_t is_fg;		/* control alpha & transp */
817 	uint32_t alpha;
818 	uint32_t blend_op;
819 	uint32_t transp_mask;
820 	uint32_t flags;
821 	uint32_t pipe_type;
822 	uint32_t id;
823 	uint8_t priority;
824 	uint32_t user_data[6];
825 	uint32_t bg_color;
826 	uint8_t horz_deci;
827 	uint8_t vert_deci;
828 	struct mdp_overlay_pp_params overlay_pp_cfg;
829 	struct mdp_scale_data scale;
830 	uint8_t color_space;
831 	uint32_t frame_rate;
832 };
833 
834 struct msmfb_overlay_3d {
835 	uint32_t is_3d;
836 	uint32_t width;
837 	uint32_t height;
838 };
839 
840 
841 struct msmfb_overlay_blt {
842 	uint32_t enable;
843 	uint32_t offset;
844 	uint32_t width;
845 	uint32_t height;
846 	uint32_t bpp;
847 };
848 
849 struct mdp_histogram {
850 	uint32_t frame_cnt;
851 	uint32_t bin_cnt;
852 	uint32_t *r;
853 	uint32_t *g;
854 	uint32_t *b;
855 };
856 
857 #define MISR_CRC_BATCH_SIZE 32
858 enum {
859 	DISPLAY_MISR_EDP,
860 	DISPLAY_MISR_DSI0,
861 	DISPLAY_MISR_DSI1,
862 	DISPLAY_MISR_HDMI,
863 	DISPLAY_MISR_LCDC,
864 	DISPLAY_MISR_MDP,
865 	DISPLAY_MISR_ATV,
866 	DISPLAY_MISR_DSI_CMD,
867 	DISPLAY_MISR_MAX
868 };
869 
870 enum {
871 	MISR_OP_NONE,
872 	MISR_OP_SFM,
873 	MISR_OP_MFM,
874 	MISR_OP_BM,
875 	MISR_OP_MAX
876 };
877 
878 struct mdp_misr {
879 	uint32_t block_id;
880 	uint32_t frame_count;
881 	uint32_t crc_op_mode;
882 	uint32_t crc_value[MISR_CRC_BATCH_SIZE];
883 };
884 
885 /*
886 
887 	mdp_block_type defines the identifiers for pipes in MDP 4.3 and up
888 
889 	MDP_BLOCK_RESERVED is provided for backward compatibility and is
890 	deprecated. It corresponds to DMA_P. So MDP_BLOCK_DMA_P should be used
891 	instead.
892 
893 	MDP_LOGICAL_BLOCK_DISP_0 identifies the display pipe which fb0 uses,
894 	same for others.
895 
896 */
897 
898 enum {
899 	MDP_BLOCK_RESERVED = 0,
900 	MDP_BLOCK_OVERLAY_0,
901 	MDP_BLOCK_OVERLAY_1,
902 	MDP_BLOCK_VG_1,
903 	MDP_BLOCK_VG_2,
904 	MDP_BLOCK_RGB_1,
905 	MDP_BLOCK_RGB_2,
906 	MDP_BLOCK_DMA_P,
907 	MDP_BLOCK_DMA_S,
908 	MDP_BLOCK_DMA_E,
909 	MDP_BLOCK_OVERLAY_2,
910 	MDP_LOGICAL_BLOCK_DISP_0 = 0x10,
911 	MDP_LOGICAL_BLOCK_DISP_1,
912 	MDP_LOGICAL_BLOCK_DISP_2,
913 	MDP_BLOCK_MAX,
914 };
915 
916 /*
917  * mdp_histogram_start_req is used to provide the parameters for
918  * histogram start request
919  */
920 
921 struct mdp_histogram_start_req {
922 	uint32_t block;
923 	uint8_t frame_cnt;
924 	uint8_t bit_mask;
925 	uint16_t num_bins;
926 };
927 
928 /*
929  * mdp_histogram_data is used to return the histogram data, once
930  * the histogram is done/stopped/cance
931  */
932 
933 struct mdp_histogram_data {
934 	uint32_t block;
935 	uint32_t bin_cnt;
936 	uint32_t *c0;
937 	uint32_t *c1;
938 	uint32_t *c2;
939 	uint32_t *extra_info;
940 };
941 
942 
943 #define GC_LUT_ENTRIES_V1_7	512
944 
945 struct mdp_ar_gc_lut_data {
946 	uint32_t x_start;
947 	uint32_t slope;
948 	uint32_t offset;
949 };
950 
951 #define MDP_PP_PGC_ROUNDING_ENABLE 0x10
952 struct mdp_pgc_lut_data {
953 	uint32_t version;
954 	uint32_t block;
955 	uint32_t flags;
956 	uint8_t num_r_stages;
957 	uint8_t num_g_stages;
958 	uint8_t num_b_stages;
959 	struct mdp_ar_gc_lut_data *r_data;
960 	struct mdp_ar_gc_lut_data *g_data;
961 	struct mdp_ar_gc_lut_data *b_data;
962 	void *cfg_payload;
963 };
964 
965 #define PGC_LUT_ENTRIES 1024
966 struct mdp_pgc_lut_data_v1_7 {
967 	uint32_t  len;
968 	uint32_t  *c0_data;
969 	uint32_t  *c1_data;
970 	uint32_t  *c2_data;
971 };
972 
973 /*
974  * mdp_rgb_lut_data is used to provide parameters for configuring the
975  * generic RGB lut in case of gamma correction or other LUT updation usecases
976  */
977 struct mdp_rgb_lut_data {
978 	uint32_t flags;
979 	uint32_t lut_type;
980 	struct fb_cmap cmap;
981 };
982 
983 enum {
984 	mdp_rgb_lut_gc,
985 	mdp_rgb_lut_hist,
986 };
987 
988 struct mdp_lut_cfg_data {
989 	uint32_t lut_type;
990 	union {
991 		struct mdp_igc_lut_data igc_lut_data;
992 		struct mdp_pgc_lut_data pgc_lut_data;
993 		struct mdp_hist_lut_data hist_lut_data;
994 		struct mdp_rgb_lut_data rgb_lut_data;
995 	} data;
996 };
997 
998 struct mdp_bl_scale_data {
999 	uint32_t min_lvl;
1000 	uint32_t scale;
1001 };
1002 
1003 struct mdp_pa_cfg_data {
1004 	uint32_t block;
1005 	struct mdp_pa_cfg pa_data;
1006 };
1007 
1008 #define MDP_DITHER_DATA_V1_7_SZ 16
1009 
1010 struct mdp_dither_data_v1_7 {
1011 	uint32_t g_y_depth;
1012 	uint32_t r_cr_depth;
1013 	uint32_t b_cb_depth;
1014 	uint32_t len;
1015 	uint32_t data[MDP_DITHER_DATA_V1_7_SZ];
1016 	uint32_t temporal_en;
1017 };
1018 
1019 struct mdp_dither_cfg_data {
1020 	uint32_t version;
1021 	uint32_t block;
1022 	uint32_t flags;
1023 	uint32_t mode;
1024 	uint32_t g_y_depth;
1025 	uint32_t r_cr_depth;
1026 	uint32_t b_cb_depth;
1027 	void *cfg_payload;
1028 };
1029 
1030 #define MDP_GAMUT_TABLE_NUM		8
1031 #define MDP_GAMUT_TABLE_NUM_V1_7	4
1032 #define MDP_GAMUT_SCALE_OFF_TABLE_NUM	3
1033 #define MDP_GAMUT_TABLE_V1_7_SZ 1229
1034 #define MDP_GAMUT_SCALE_OFF_SZ 16
1035 #define MDP_GAMUT_TABLE_V1_7_COARSE_SZ 32
1036 
1037 struct mdp_gamut_cfg_data {
1038 	uint32_t block;
1039 	uint32_t flags;
1040 	uint32_t version;
1041 	/* v1 version specific params */
1042 	uint32_t gamut_first;
1043 	uint32_t tbl_size[MDP_GAMUT_TABLE_NUM];
1044 	uint16_t *r_tbl[MDP_GAMUT_TABLE_NUM];
1045 	uint16_t *g_tbl[MDP_GAMUT_TABLE_NUM];
1046 	uint16_t *b_tbl[MDP_GAMUT_TABLE_NUM];
1047 	/* params for newer versions of gamut */
1048 	void *cfg_payload;
1049 };
1050 
1051 enum {
1052 	mdp_gamut_fine_mode = 0x1,
1053 	mdp_gamut_coarse_mode,
1054 };
1055 
1056 struct mdp_gamut_data_v1_7 {
1057 	uint32_t mode;
1058 	uint32_t map_en;
1059 	uint32_t tbl_size[MDP_GAMUT_TABLE_NUM_V1_7];
1060 	uint32_t *c0_data[MDP_GAMUT_TABLE_NUM_V1_7];
1061 	uint32_t *c1_c2_data[MDP_GAMUT_TABLE_NUM_V1_7];
1062 	uint32_t  tbl_scale_off_sz[MDP_GAMUT_SCALE_OFF_TABLE_NUM];
1063 	uint32_t  *scale_off_data[MDP_GAMUT_SCALE_OFF_TABLE_NUM];
1064 };
1065 
1066 struct mdp_calib_config_data {
1067 	uint32_t ops;
1068 	uint32_t addr;
1069 	uint32_t data;
1070 };
1071 
1072 struct mdp_calib_config_buffer {
1073 	uint32_t ops;
1074 	uint32_t size;
1075 	uint32_t *buffer;
1076 };
1077 
1078 struct mdp_calib_dcm_state {
1079 	uint32_t ops;
1080 	uint32_t dcm_state;
1081 };
1082 
1083 enum {
1084 	DCM_UNINIT,
1085 	DCM_UNBLANK,
1086 	DCM_ENTER,
1087 	DCM_EXIT,
1088 	DCM_BLANK,
1089 	DTM_ENTER,
1090 	DTM_EXIT,
1091 };
1092 
1093 #define MDSS_PP_SPLIT_LEFT_ONLY		0x10000000
1094 #define MDSS_PP_SPLIT_RIGHT_ONLY	0x20000000
1095 #define MDSS_PP_SPLIT_MASK		0x30000000
1096 
1097 #define MDSS_MAX_BL_BRIGHTNESS 255
1098 #define AD_BL_LIN_LEN 256
1099 #define AD_BL_ATT_LUT_LEN 33
1100 
1101 #define MDSS_AD_MODE_AUTO_BL	0x0
1102 #define MDSS_AD_MODE_AUTO_STR	0x1
1103 #define MDSS_AD_MODE_TARG_STR	0x3
1104 #define MDSS_AD_MODE_MAN_STR	0x7
1105 #define MDSS_AD_MODE_CALIB	0xF
1106 
1107 #define MDP_PP_AD_INIT	0x10
1108 #define MDP_PP_AD_CFG	0x20
1109 
1110 struct mdss_ad_init {
1111 	uint32_t asym_lut[33];
1112 	uint32_t color_corr_lut[33];
1113 	uint8_t i_control[2];
1114 	uint16_t black_lvl;
1115 	uint16_t white_lvl;
1116 	uint8_t var;
1117 	uint8_t limit_ampl;
1118 	uint8_t i_dither;
1119 	uint8_t slope_max;
1120 	uint8_t slope_min;
1121 	uint8_t dither_ctl;
1122 	uint8_t format;
1123 	uint8_t auto_size;
1124 	uint16_t frame_w;
1125 	uint16_t frame_h;
1126 	uint8_t logo_v;
1127 	uint8_t logo_h;
1128 	uint32_t alpha;
1129 	uint32_t alpha_base;
1130 	uint32_t al_thresh;
1131 	uint32_t bl_lin_len;
1132 	uint32_t bl_att_len;
1133 	uint32_t *bl_lin;
1134 	uint32_t *bl_lin_inv;
1135 	uint32_t *bl_att_lut;
1136 };
1137 
1138 #define MDSS_AD_BL_CTRL_MODE_EN 1
1139 #define MDSS_AD_BL_CTRL_MODE_DIS 0
1140 struct mdss_ad_cfg {
1141 	uint32_t mode;
1142 	uint32_t al_calib_lut[33];
1143 	uint16_t backlight_min;
1144 	uint16_t backlight_max;
1145 	uint16_t backlight_scale;
1146 	uint16_t amb_light_min;
1147 	uint16_t filter[2];
1148 	uint16_t calib[4];
1149 	uint8_t strength_limit;
1150 	uint8_t t_filter_recursion;
1151 	uint16_t stab_itr;
1152 	uint32_t bl_ctrl_mode;
1153 };
1154 
1155 /* ops uses standard MDP_PP_* flags */
1156 struct mdss_ad_init_cfg {
1157 	uint32_t ops;
1158 	union {
1159 		struct mdss_ad_init init;
1160 		struct mdss_ad_cfg cfg;
1161 	} params;
1162 };
1163 
1164 /* mode uses MDSS_AD_MODE_* flags */
1165 struct mdss_ad_input {
1166 	uint32_t mode;
1167 	union {
1168 		uint32_t amb_light;
1169 		uint32_t strength;
1170 		uint32_t calib_bl;
1171 	} in;
1172 	uint32_t output;
1173 };
1174 
1175 #define MDSS_CALIB_MODE_BL	0x1
1176 struct mdss_calib_cfg {
1177 	uint32_t ops;
1178 	uint32_t calib_mask;
1179 };
1180 
1181 enum {
1182 	mdp_op_pcc_cfg,
1183 	mdp_op_csc_cfg,
1184 	mdp_op_lut_cfg,
1185 	mdp_op_qseed_cfg,
1186 	mdp_bl_scale_cfg,
1187 	mdp_op_pa_cfg,
1188 	mdp_op_pa_v2_cfg,
1189 	mdp_op_dither_cfg,
1190 	mdp_op_gamut_cfg,
1191 	mdp_op_calib_cfg,
1192 	mdp_op_ad_cfg,
1193 	mdp_op_ad_input,
1194 	mdp_op_calib_mode,
1195 	mdp_op_calib_buffer,
1196 	mdp_op_calib_dcm_state,
1197 	mdp_op_max,
1198 };
1199 
1200 enum {
1201 	WB_FORMAT_NV12,
1202 	WB_FORMAT_RGB_565,
1203 	WB_FORMAT_RGB_888,
1204 	WB_FORMAT_xRGB_8888,
1205 	WB_FORMAT_ARGB_8888,
1206 	WB_FORMAT_BGRA_8888,
1207 	WB_FORMAT_BGRX_8888,
1208 	WB_FORMAT_ARGB_8888_INPUT_ALPHA /* Need to support */
1209 };
1210 
1211 struct msmfb_mdp_pp {
1212 	uint32_t op;
1213 	union {
1214 		struct mdp_pcc_cfg_data pcc_cfg_data;
1215 		struct mdp_csc_cfg_data csc_cfg_data;
1216 		struct mdp_lut_cfg_data lut_cfg_data;
1217 		struct mdp_qseed_cfg_data qseed_cfg_data;
1218 		struct mdp_bl_scale_data bl_scale_data;
1219 		struct mdp_pa_cfg_data pa_cfg_data;
1220 		struct mdp_pa_v2_cfg_data pa_v2_cfg_data;
1221 		struct mdp_dither_cfg_data dither_cfg_data;
1222 		struct mdp_gamut_cfg_data gamut_cfg_data;
1223 		struct mdp_calib_config_data calib_cfg;
1224 		struct mdss_ad_init_cfg ad_init_cfg;
1225 		struct mdss_calib_cfg mdss_calib_cfg;
1226 		struct mdss_ad_input ad_input;
1227 		struct mdp_calib_config_buffer calib_buffer;
1228 		struct mdp_calib_dcm_state calib_dcm;
1229 	} data;
1230 };
1231 
1232 #define FB_METADATA_VIDEO_INFO_CODE_SUPPORT 1
1233 enum {
1234 	metadata_op_none,
1235 	metadata_op_base_blend,
1236 	metadata_op_frame_rate,
1237 	metadata_op_vic,
1238 	metadata_op_wb_format,
1239 	metadata_op_wb_secure,
1240 	metadata_op_get_caps,
1241 	metadata_op_crc,
1242 	metadata_op_get_ion_fd,
1243 	metadata_op_max
1244 };
1245 
1246 struct mdp_blend_cfg {
1247 	uint32_t is_premultiplied;
1248 };
1249 
1250 struct mdp_mixer_cfg {
1251 	uint32_t writeback_format;
1252 	uint32_t alpha;
1253 };
1254 
1255 struct mdss_hw_caps {
1256 	uint32_t mdp_rev;
1257 	uint8_t rgb_pipes;
1258 	uint8_t vig_pipes;
1259 	uint8_t dma_pipes;
1260 	uint8_t max_smp_cnt;
1261 	uint8_t smp_per_pipe;
1262 	uint32_t features;
1263 };
1264 
1265 struct msmfb_metadata {
1266 	uint32_t op;
1267 	uint32_t flags;
1268 	union {
1269 		struct mdp_misr misr_request;
1270 		struct mdp_blend_cfg blend_cfg;
1271 		struct mdp_mixer_cfg mixer_cfg;
1272 		uint32_t panel_frame_rate;
1273 		uint32_t video_info_code;
1274 		struct mdss_hw_caps caps;
1275 		uint8_t secure_en;
1276 		int fbmem_ionfd;
1277 	} data;
1278 };
1279 
1280 #define MDP_MAX_FENCE_FD	32
1281 #define MDP_BUF_SYNC_FLAG_WAIT	1
1282 #define MDP_BUF_SYNC_FLAG_RETIRE_FENCE	0x10
1283 
1284 struct mdp_buf_sync {
1285 	uint32_t flags;
1286 	uint32_t acq_fen_fd_cnt;
1287 	uint32_t session_id;
1288 	int *acq_fen_fd;
1289 	int *rel_fen_fd;
1290 	int *retire_fen_fd;
1291 };
1292 
1293 struct mdp_async_blit_req_list {
1294 	struct mdp_buf_sync sync;
1295 	uint32_t count;
1296 	struct mdp_blit_req req[];
1297 };
1298 
1299 #define MDP_DISPLAY_COMMIT_OVERLAY	1
1300 
1301 struct mdp_display_commit {
1302 	uint32_t flags;
1303 	uint32_t wait_for_finish;
1304 	struct fb_var_screeninfo var;
1305 	/*
1306 	 * user needs to follow guidelines as per below rules
1307 	 * 1. source split is enabled: l_roi = roi and r_roi = 0
1308 	 * 2. source split is disabled:
1309 	 *	2.1 split display: l_roi = l_roi and r_roi = r_roi
1310 	 *	2.2 non split display: l_roi = roi and r_roi = 0
1311 	 */
1312 	struct mdp_rect l_roi;
1313 	struct mdp_rect r_roi;
1314 };
1315 
1316 /**
1317  * struct mdp_overlay_list - argument for ioctl MSMFB_OVERLAY_PREPARE
1318  * @num_overlays:	Number of overlay layers as part of the frame.
1319  * @overlay_list:	Pointer to a list of overlay structures identifying
1320  *			the layers as part of the frame
1321  * @flags:		Flags can be used to extend behavior.
1322  * @processed_overlays:	Output parameter indicating how many pipes were
1323  *			successful. If there are no errors this number should
1324  *			match num_overlays. Otherwise it will indicate the last
1325  *			successful index for overlay that couldn't be set.
1326  */
1327 struct mdp_overlay_list {
1328 	uint32_t num_overlays;
1329 	struct mdp_overlay **overlay_list;
1330 	uint32_t flags;
1331 	uint32_t processed_overlays;
1332 };
1333 
1334 struct mdp_page_protection {
1335 	uint32_t page_protection;
1336 };
1337 
1338 
1339 struct mdp_mixer_info {
1340 	int pndx;
1341 	int pnum;
1342 	int ptype;
1343 	int mixer_num;
1344 	int z_order;
1345 };
1346 
1347 #define MAX_PIPE_PER_MIXER  7
1348 
1349 struct msmfb_mixer_info_req {
1350 	int mixer_num;
1351 	int cnt;
1352 	struct mdp_mixer_info info[MAX_PIPE_PER_MIXER];
1353 };
1354 
1355 enum {
1356 	DISPLAY_SUBSYSTEM_ID,
1357 	ROTATOR_SUBSYSTEM_ID,
1358 };
1359 
1360 enum {
1361 	MDP_IOMMU_DOMAIN_CP,
1362 	MDP_IOMMU_DOMAIN_NS,
1363 };
1364 
1365 enum {
1366 	MDP_WRITEBACK_MIRROR_OFF,
1367 	MDP_WRITEBACK_MIRROR_ON,
1368 	MDP_WRITEBACK_MIRROR_PAUSE,
1369 	MDP_WRITEBACK_MIRROR_RESUME,
1370 };
1371 
1372 enum mdp_color_space {
1373 	MDP_CSC_ITU_R_601,
1374 	MDP_CSC_ITU_R_601_FR,
1375 	MDP_CSC_ITU_R_709,
1376 };
1377 
1378 enum {
1379 	mdp_igc_v1_7 = 1,
1380 	mdp_igc_vmax,
1381 	mdp_hist_lut_v1_7,
1382 	mdp_hist_lut_vmax,
1383 	mdp_pgc_v1_7,
1384 	mdp_pgc_vmax,
1385 	mdp_dither_v1_7,
1386 	mdp_dither_vmax,
1387 	mdp_gamut_v1_7,
1388 	mdp_gamut_vmax,
1389 	mdp_pa_v1_7,
1390 	mdp_pa_vmax,
1391 	mdp_pcc_v1_7,
1392 	mdp_pcc_vmax,
1393 	mdp_pp_legacy,
1394 };
1395 
1396 /* PP Features */
1397 enum {
1398 	IGC = 1,
1399 	PCC,
1400 	GC,
1401 	PA,
1402 	GAMUT,
1403 	DITHER,
1404 	QSEED,
1405 	HIST_LUT,
1406 	HIST,
1407 	PP_FEATURE_MAX,
1408 };
1409 
1410 struct mdp_pp_feature_version {
1411 	uint32_t pp_feature;
1412 	uint32_t version_info;
1413 };
1414 #endif /*_UAPI_MSM_MDP_H_*/
1415