56 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)  in cm_setup_context()  argument
64 	security_state = GET_SECURITY_STATE(ep->h.attr);  in cm_setup_context()
99 		assert(((ep->spsr >> SPSR_E_SHIFT) & SPSR_E_MASK) ==  in cm_setup_context()
100 			(EP_GET_EE(ep->h.attr) >> EP_EE_SHIFT));  in cm_setup_context()
102 		sctlr = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0U;  in cm_setup_context()
111 	if (GET_M32(ep->spsr) == MODE32_hyp)  in cm_setup_context()
120 	write_ctx_reg(reg_ctx, CTX_LR, ep->pc);  in cm_setup_context()
121 	write_ctx_reg(reg_ctx, CTX_SPSR, ep->spsr);  in cm_setup_context()
127 	memcpy((void *)reg_ctx, (void *)&ep->args, sizeof(aapcs32_params_t));  in cm_setup_context()
150 			      const entry_point_info_t *ep)  in cm_init_context_by_index()  argument
153 	ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr));  in cm_init_context_by_index()
154 	cm_setup_context(ctx, ep);  in cm_init_context_by_index()
162 void cm_init_my_context(const entry_point_info_t *ep)  in cm_init_my_context()  argument
165 	ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr));  in cm_init_my_context()
166 	cm_setup_context(ctx, ep);  in cm_init_my_context()