1 /*
2 * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <stdbool.h>
9 #include <string.h>
10
11 #include <platform_def.h>
12
13 #include <arch.h>
14 #include <arch_helpers.h>
15 #include <common/bl_common.h>
16 #include <context.h>
17 #include <lib/el3_runtime/context_mgmt.h>
18 #include <lib/extensions/amu.h>
19 #include <lib/utils.h>
20 #include <plat/common/platform.h>
21 #include <smccc_helpers.h>
22
23 /*******************************************************************************
24 * Context management library initialisation routine. This library is used by
25 * runtime services to share pointers to 'cpu_context' structures for the secure
26 * and non-secure states. Management of the structures and their associated
27 * memory is not done by the context management library e.g. the PSCI service
28 * manages the cpu context used for entry from and exit to the non-secure state.
29 * The Secure payload manages the context(s) corresponding to the secure state.
30 * It also uses this library to get access to the non-secure
31 * state cpu context pointers.
32 ******************************************************************************/
cm_init(void)33 void cm_init(void)
34 {
35 /*
36 * The context management library has only global data to initialize, but
37 * that will be done when the BSS is zeroed out
38 */
39 }
40
41 /*******************************************************************************
42 * The following function initializes the cpu_context 'ctx' for
43 * first use, and sets the initial entrypoint state as specified by the
44 * entry_point_info structure.
45 *
46 * The security state to initialize is determined by the SECURE attribute
47 * of the entry_point_info.
48 *
49 * The EE and ST attributes are used to configure the endianness and secure
50 * timer availability for the new execution context.
51 *
52 * To prepare the register state for entry call cm_prepare_el3_exit() and
53 * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to
54 * cm_e1_sysreg_context_restore().
55 ******************************************************************************/
cm_setup_context(cpu_context_t * ctx,const entry_point_info_t * ep)56 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
57 {
58 unsigned int security_state;
59 uint32_t scr, sctlr;
60 regs_t *reg_ctx;
61
62 assert(ctx != NULL);
63
64 security_state = GET_SECURITY_STATE(ep->h.attr);
65
66 /* Clear any residual register values from the context */
67 zeromem(ctx, sizeof(*ctx));
68
69 reg_ctx = get_regs_ctx(ctx);
70
71 /*
72 * Base the context SCR on the current value, adjust for entry point
73 * specific requirements
74 */
75 scr = read_scr();
76 scr &= ~(SCR_NS_BIT | SCR_HCE_BIT);
77
78 if (security_state != SECURE)
79 scr |= SCR_NS_BIT;
80
81 if (security_state != SECURE) {
82 /*
83 * Set up SCTLR for the Non-secure context.
84 *
85 * SCTLR.EE: Endianness is taken from the entrypoint attributes.
86 *
87 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as
88 * required by PSCI specification)
89 *
90 * Set remaining SCTLR fields to their architecturally defined
91 * values. Some fields reset to an IMPLEMENTATION DEFINED value:
92 *
93 * SCTLR.TE: Set to zero so that exceptions to an Exception
94 * Level executing at PL1 are taken to A32 state.
95 *
96 * SCTLR.V: Set to zero to select the normal exception vectors
97 * with base address held in VBAR.
98 */
99 assert(((ep->spsr >> SPSR_E_SHIFT) & SPSR_E_MASK) ==
100 (EP_GET_EE(ep->h.attr) >> EP_EE_SHIFT));
101
102 sctlr = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0U;
103 sctlr |= (SCTLR_RESET_VAL & ~(SCTLR_TE_BIT | SCTLR_V_BIT));
104 write_ctx_reg(reg_ctx, CTX_NS_SCTLR, sctlr);
105 }
106
107 /*
108 * The target exception level is based on the spsr mode requested. If
109 * execution is requested to hyp mode, HVC is enabled via SCR.HCE.
110 */
111 if (GET_M32(ep->spsr) == MODE32_hyp)
112 scr |= SCR_HCE_BIT;
113
114 /*
115 * Store the initialised values for SCTLR and SCR in the cpu_context.
116 * The Hyp mode registers are not part of the saved context and are
117 * set-up in cm_prepare_el3_exit().
118 */
119 write_ctx_reg(reg_ctx, CTX_SCR, scr);
120 write_ctx_reg(reg_ctx, CTX_LR, ep->pc);
121 write_ctx_reg(reg_ctx, CTX_SPSR, ep->spsr);
122
123 /*
124 * Store the r0-r3 value from the entrypoint into the context
125 * Use memcpy as we are in control of the layout of the structures
126 */
127 memcpy((void *)reg_ctx, (void *)&ep->args, sizeof(aapcs32_params_t));
128 }
129
130 /*******************************************************************************
131 * Enable architecture extensions on first entry to Non-secure world.
132 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise
133 * it is zero.
134 ******************************************************************************/
enable_extensions_nonsecure(bool el2_unused)135 static void enable_extensions_nonsecure(bool el2_unused)
136 {
137 #if IMAGE_BL32
138 #if ENABLE_AMU
139 amu_enable(el2_unused);
140 #endif
141 #endif
142 }
143
144 /*******************************************************************************
145 * The following function initializes the cpu_context for a CPU specified by
146 * its `cpu_idx` for first use, and sets the initial entrypoint state as
147 * specified by the entry_point_info structure.
148 ******************************************************************************/
cm_init_context_by_index(unsigned int cpu_idx,const entry_point_info_t * ep)149 void cm_init_context_by_index(unsigned int cpu_idx,
150 const entry_point_info_t *ep)
151 {
152 cpu_context_t *ctx;
153 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr));
154 cm_setup_context(ctx, ep);
155 }
156
157 /*******************************************************************************
158 * The following function initializes the cpu_context for the current CPU
159 * for first use, and sets the initial entrypoint state as specified by the
160 * entry_point_info structure.
161 ******************************************************************************/
cm_init_my_context(const entry_point_info_t * ep)162 void cm_init_my_context(const entry_point_info_t *ep)
163 {
164 cpu_context_t *ctx;
165 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr));
166 cm_setup_context(ctx, ep);
167 }
168
169 /*******************************************************************************
170 * Prepare the CPU system registers for first entry into secure or normal world
171 *
172 * If execution is requested to hyp mode, HSCTLR is initialized
173 * If execution is requested to non-secure PL1, and the CPU supports
174 * HYP mode then HYP mode is disabled by configuring all necessary HYP mode
175 * registers.
176 ******************************************************************************/
cm_prepare_el3_exit(uint32_t security_state)177 void cm_prepare_el3_exit(uint32_t security_state)
178 {
179 uint32_t hsctlr, scr;
180 cpu_context_t *ctx = cm_get_context(security_state);
181 bool el2_unused = false;
182
183 assert(ctx != NULL);
184
185 if (security_state == NON_SECURE) {
186 scr = read_ctx_reg(get_regs_ctx(ctx), CTX_SCR);
187 if ((scr & SCR_HCE_BIT) != 0U) {
188 /* Use SCTLR value to initialize HSCTLR */
189 hsctlr = read_ctx_reg(get_regs_ctx(ctx),
190 CTX_NS_SCTLR);
191 hsctlr |= HSCTLR_RES1;
192 /* Temporarily set the NS bit to access HSCTLR */
193 write_scr(read_scr() | SCR_NS_BIT);
194 /*
195 * Make sure the write to SCR is complete so that
196 * we can access HSCTLR
197 */
198 isb();
199 write_hsctlr(hsctlr);
200 isb();
201
202 write_scr(read_scr() & ~SCR_NS_BIT);
203 isb();
204 } else if ((read_id_pfr1() &
205 (ID_PFR1_VIRTEXT_MASK << ID_PFR1_VIRTEXT_SHIFT)) != 0U) {
206 el2_unused = true;
207
208 /*
209 * Set the NS bit to access NS copies of certain banked
210 * registers
211 */
212 write_scr(read_scr() | SCR_NS_BIT);
213 isb();
214
215 /*
216 * Hyp / PL2 present but unused, need to disable safely.
217 * HSCTLR can be ignored in this case.
218 *
219 * Set HCR to its architectural reset value so that
220 * Non-secure operations do not trap to Hyp mode.
221 */
222 write_hcr(HCR_RESET_VAL);
223
224 /*
225 * Set HCPTR to its architectural reset value so that
226 * Non-secure access from EL1 or EL0 to trace and to
227 * Advanced SIMD and floating point functionality does
228 * not trap to Hyp mode.
229 */
230 write_hcptr(HCPTR_RESET_VAL);
231
232 /*
233 * Initialise CNTHCTL. All fields are architecturally
234 * UNKNOWN on reset and are set to zero except for
235 * field(s) listed below.
236 *
237 * CNTHCTL.PL1PCEN: Disable traps to Hyp mode of
238 * Non-secure EL0 and EL1 accessed to the physical
239 * timer registers.
240 *
241 * CNTHCTL.PL1PCTEN: Disable traps to Hyp mode of
242 * Non-secure EL0 and EL1 accessed to the physical
243 * counter registers.
244 */
245 write_cnthctl(CNTHCTL_RESET_VAL |
246 PL1PCEN_BIT | PL1PCTEN_BIT);
247
248 /*
249 * Initialise CNTVOFF to zero as it resets to an
250 * IMPLEMENTATION DEFINED value.
251 */
252 write64_cntvoff(0);
253
254 /*
255 * Set VPIDR and VMPIDR to match MIDR_EL1 and MPIDR
256 * respectively.
257 */
258 write_vpidr(read_midr());
259 write_vmpidr(read_mpidr());
260
261 /*
262 * Initialise VTTBR, setting all fields rather than
263 * relying on the hw. Some fields are architecturally
264 * UNKNOWN at reset.
265 *
266 * VTTBR.VMID: Set to zero which is the architecturally
267 * defined reset value. Even though EL1&0 stage 2
268 * address translation is disabled, cache maintenance
269 * operations depend on the VMID.
270 *
271 * VTTBR.BADDR: Set to zero as EL1&0 stage 2 address
272 * translation is disabled.
273 */
274 write64_vttbr(VTTBR_RESET_VAL &
275 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT)
276 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT)));
277
278 /*
279 * Initialise HDCR, setting all the fields rather than
280 * relying on hw.
281 *
282 * HDCR.HPMN: Set to value of PMCR.N which is the
283 * architecturally-defined reset value.
284 *
285 * HDCR.HLP: Set to one so that event counter
286 * overflow, that is recorded in PMOVSCLR[0-30],
287 * occurs on the increment that changes
288 * PMEVCNTR<n>[63] from 1 to 0, when ARMv8.5-PMU is
289 * implemented. This bit is RES0 in versions of the
290 * architecture earlier than ARMv8.5, setting it to 1
291 * doesn't have any effect on them.
292 * This bit is Reserved, UNK/SBZP in ARMv7.
293 *
294 * HDCR.HPME: Set to zero to disable EL2 Event
295 * counters.
296 */
297 #if (ARM_ARCH_MAJOR > 7)
298 write_hdcr((HDCR_RESET_VAL | HDCR_HLP_BIT |
299 ((read_pmcr() & PMCR_N_BITS) >>
300 PMCR_N_SHIFT)) & ~HDCR_HPME_BIT);
301 #else
302 write_hdcr((HDCR_RESET_VAL |
303 ((read_pmcr() & PMCR_N_BITS) >>
304 PMCR_N_SHIFT)) & ~HDCR_HPME_BIT);
305 #endif
306 /*
307 * Set HSTR to its architectural reset value so that
308 * access to system registers in the cproc=1111
309 * encoding space do not trap to Hyp mode.
310 */
311 write_hstr(HSTR_RESET_VAL);
312 /*
313 * Set CNTHP_CTL to its architectural reset value to
314 * disable the EL2 physical timer and prevent timer
315 * interrupts. Some fields are architecturally UNKNOWN
316 * on reset and are set to zero.
317 */
318 write_cnthp_ctl(CNTHP_CTL_RESET_VAL);
319 isb();
320
321 write_scr(read_scr() & ~SCR_NS_BIT);
322 isb();
323 }
324 enable_extensions_nonsecure(el2_unused);
325 }
326 }
327