Lines Matching refs:cru
6 #include <dt-bindings/clock/rk3399-cru.h>
77 clocks = <&cru ARMCLKL>;
85 clocks = <&cru ARMCLKL>;
93 clocks = <&cru ARMCLKL>;
101 clocks = <&cru ARMCLKL>;
110 clocks = <&cru ARMCLKB>;
118 clocks = <&cru ARMCLKB>;
165 clocks = <&cru ACLK_DMAC0_PERILP>;
175 clocks = <&cru ACLK_DMAC1_PERILP>;
190 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
191 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
210 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
211 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
212 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
213 <&cru SRST_A_PCIE>;
230 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
231 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
232 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
233 <&cru PCLK_GMAC>;
239 resets = <&cru SRST_A_GMAC>;
251 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
252 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
256 resets = <&cru SRST_SDIO0>;
267 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
268 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
272 resets = <&cru SRST_SDMMC>;
282 assigned-clocks = <&cru SCLK_EMMC>;
285 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
299 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
313 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
327 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
341 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
356 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
357 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
358 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
362 resets = <&cru SRST_A_USB3_OTG0>;
389 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
390 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
391 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
395 resets = <&cru SRST_A_USB3_OTG1>;
421 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
423 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
424 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
428 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
429 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
489 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
491 resets = <&cru SRST_P_SARADC>;
499 assigned-clocks = <&cru SCLK_I2C1>;
501 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
514 assigned-clocks = <&cru SCLK_I2C2>;
516 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
529 assigned-clocks = <&cru SCLK_I2C3>;
531 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
544 assigned-clocks = <&cru SCLK_I2C5>;
546 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
559 assigned-clocks = <&cru SCLK_I2C6>;
561 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
574 assigned-clocks = <&cru SCLK_I2C7>;
576 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
589 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
602 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
615 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
629 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
642 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
655 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
668 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
681 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
694 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
777 assigned-clocks = <&cru SCLK_TSADC>;
779 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
781 resets = <&cru SRST_TSADC>;
938 clocks = <&cru ACLK_IEP>,
939 <&cru HCLK_IEP>;
944 clocks = <&cru ACLK_RGA>,
945 <&cru HCLK_RGA>;
951 clocks = <&cru ACLK_VCODEC>,
952 <&cru HCLK_VCODEC>;
957 clocks = <&cru ACLK_VDU>,
958 <&cru HCLK_VDU>;
966 clocks = <&cru ACLK_GPU>;
973 clocks = <&cru PCLK_EDP_CTRL>;
977 clocks = <&cru ACLK_EMMC>;
982 clocks = <&cru ACLK_GMAC>,
983 <&cru PCLK_GMAC>;
990 clocks = <&cru ACLK_PERIHP>;
998 clocks = <&cru HCLK_SDMMC>,
999 <&cru SCLK_SDMMC>;
1005 clocks = <&cru HCLK_SDIO>;
1010 clocks = <&cru ACLK_USB3>;
1021 clocks = <&cru ACLK_HDCP>,
1022 <&cru HCLK_HDCP>,
1023 <&cru PCLK_HDCP>;
1028 clocks = <&cru ACLK_ISP0>,
1029 <&cru HCLK_ISP0>;
1035 clocks = <&cru ACLK_ISP1>,
1036 <&cru HCLK_ISP1>;
1042 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1043 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1047 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1048 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1057 clocks = <&cru ACLK_VOP0>,
1058 <&cru HCLK_VOP0>;
1064 clocks = <&cru ACLK_VOP1>,
1065 <&cru HCLK_VOP1>;
1212 clocks = <&cru PCLK_DDR_MON>;
1221 clocks = <&cru SCLK_DDRCLK>;
1238 clocks = <&cru PCLK_EFUSE1024NS>;
1275 cru: clock-controller@ff760000 { label
1276 compatible = "rockchip,rk3399-cru";
1282 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1283 <&cru PLL_NPLL>,
1284 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1285 <&cru PCLK_PERIHP>,
1286 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1287 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
1288 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
1289 <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
1290 <&cru ACLK_GIC_PRE>,
1291 <&cru PCLK_DDR>;
1319 clocks = <&cru SCLK_USB2PHY0_REF>;
1346 clocks = <&cru SCLK_USB2PHY1_REF>;
1381 clocks = <&cru SCLK_PCIEPHY_REF>;
1384 resets = <&cru SRST_PCIEPHY>;
1393 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1394 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1396 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1399 resets = <&cru SRST_UPHY0>,
1400 <&cru SRST_UPHY0_PIPE_L00>,
1401 <&cru SRST_P_UPHY0_TCPHY>;
1418 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1419 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1421 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1424 resets = <&cru SRST_UPHY1>,
1425 <&cru SRST_UPHY1_PIPE_L00>,
1426 <&cru SRST_P_UPHY1_TCPHY>;
1443 clocks = <&cru PCLK_WDT>;
1451 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1462 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1478 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1493 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1508 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1518 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1520 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1524 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1564 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1575 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1577 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1581 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1621 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1633 clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>;
1645 clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>;
1671 clocks = <&cru PCLK_HDMI_CTRL>,
1672 <&cru SCLK_HDMI_SFR>,
1673 <&cru PLL_VPLL>,
1674 <&cru PCLK_VIO_GRF>,
1675 <&cru SCLK_HDMI_CEC>;
1704 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1705 <&cru SCLK_DPHY_TX0_CFG>;
1732 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
1733 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
1736 resets = <&cru SRST_P_MIPI_DSI1>;
1767 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
1772 resets = <&cru SRST_P_EDP_CTRL>;
1805 clocks = <&cru ACLK_GPU>;
1847 clocks = <&cru PCLK_GPIO2>;
1860 clocks = <&cru PCLK_GPIO3>;
1873 clocks = <&cru PCLK_GPIO4>;