1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rk3399-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3399-power.h> 12#include <dt-bindings/thermal/thermal.h> 13#define USB_CLASS_HUB 9 14 15/ { 16 compatible = "rockchip,rk3399"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 i2c2 = &i2c2; 26 i2c3 = &i2c3; 27 i2c4 = &i2c4; 28 i2c5 = &i2c5; 29 i2c6 = &i2c6; 30 i2c7 = &i2c7; 31 i2c8 = &i2c8; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 serial3 = &uart3; 36 serial4 = &uart4; 37 mmc0 = &sdhci; 38 mmc1 = &sdmmc; 39 }; 40 41 cpus { 42 #address-cells = <2>; 43 #size-cells = <0>; 44 45 cpu-map { 46 cluster0 { 47 core0 { 48 cpu = <&cpu_l0>; 49 }; 50 core1 { 51 cpu = <&cpu_l1>; 52 }; 53 core2 { 54 cpu = <&cpu_l2>; 55 }; 56 core3 { 57 cpu = <&cpu_l3>; 58 }; 59 }; 60 61 cluster1 { 62 core0 { 63 cpu = <&cpu_b0>; 64 }; 65 core1 { 66 cpu = <&cpu_b1>; 67 }; 68 }; 69 }; 70 71 cpu_l0: cpu@0 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a53", "arm,armv8"; 74 reg = <0x0 0x0>; 75 enable-method = "psci"; 76 #cooling-cells = <2>; /* min followed by max */ 77 clocks = <&cru ARMCLKL>; 78 }; 79 80 cpu_l1: cpu@1 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a53", "arm,armv8"; 83 reg = <0x0 0x1>; 84 enable-method = "psci"; 85 clocks = <&cru ARMCLKL>; 86 }; 87 88 cpu_l2: cpu@2 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a53", "arm,armv8"; 91 reg = <0x0 0x2>; 92 enable-method = "psci"; 93 clocks = <&cru ARMCLKL>; 94 }; 95 96 cpu_l3: cpu@3 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a53", "arm,armv8"; 99 reg = <0x0 0x3>; 100 enable-method = "psci"; 101 clocks = <&cru ARMCLKL>; 102 }; 103 104 cpu_b0: cpu@100 { 105 device_type = "cpu"; 106 compatible = "arm,cortex-a72", "arm,armv8"; 107 reg = <0x0 0x100>; 108 enable-method = "psci"; 109 #cooling-cells = <2>; /* min followed by max */ 110 clocks = <&cru ARMCLKB>; 111 }; 112 113 cpu_b1: cpu@101 { 114 device_type = "cpu"; 115 compatible = "arm,cortex-a72", "arm,armv8"; 116 reg = <0x0 0x101>; 117 enable-method = "psci"; 118 clocks = <&cru ARMCLKB>; 119 }; 120 }; 121 122 pmu_a53 { 123 compatible = "arm,cortex-a53-pmu"; 124 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 125 }; 126 127 pmu_a72 { 128 compatible = "arm,cortex-a72-pmu"; 129 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 130 }; 131 132 psci { 133 compatible = "arm,psci-1.0"; 134 method = "smc"; 135 }; 136 137 timer { 138 compatible = "arm,armv8-timer"; 139 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 140 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 141 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 142 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 143 arm,no-tick-in-suspend; 144 }; 145 146 xin24m: xin24m { 147 compatible = "fixed-clock"; 148 clock-frequency = <24000000>; 149 clock-output-names = "xin24m"; 150 #clock-cells = <0>; 151 }; 152 153 amba { 154 compatible = "simple-bus"; 155 #address-cells = <2>; 156 #size-cells = <2>; 157 ranges; 158 159 dmac_bus: dma-controller@ff6d0000 { 160 compatible = "arm,pl330", "arm,primecell"; 161 reg = <0x0 0xff6d0000 0x0 0x4000>; 162 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>, 163 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 164 #dma-cells = <1>; 165 clocks = <&cru ACLK_DMAC0_PERILP>; 166 clock-names = "apb_pclk"; 167 }; 168 169 dmac_peri: dma-controller@ff6e0000 { 170 compatible = "arm,pl330", "arm,primecell"; 171 reg = <0x0 0xff6e0000 0x0 0x4000>; 172 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>, 173 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>; 174 #dma-cells = <1>; 175 clocks = <&cru ACLK_DMAC1_PERILP>; 176 clock-names = "apb_pclk"; 177 }; 178 }; 179 180 pcie0: pcie@f8000000 { 181 compatible = "rockchip,rk3399-pcie"; 182 reg = <0x0 0xf8000000 0x0 0x2000000>, 183 <0x0 0xfd000000 0x0 0x1000000>; 184 reg-names = "axi-base", "apb-base"; 185 #address-cells = <3>; 186 #size-cells = <2>; 187 #interrupt-cells = <1>; 188 aspm-no-l0s; 189 bus-range = <0x0 0x1>; 190 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 191 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 192 clock-names = "aclk", "aclk-perf", 193 "hclk", "pm"; 194 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, 195 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, 196 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>; 197 interrupt-names = "sys", "legacy", "client"; 198 interrupt-map-mask = <0 0 0 7>; 199 interrupt-map = <0 0 0 1 &pcie0_intc 0>, 200 <0 0 0 2 &pcie0_intc 1>, 201 <0 0 0 3 &pcie0_intc 2>, 202 <0 0 0 4 &pcie0_intc 3>; 203 linux,pci-domain = <0>; 204 max-link-speed = <1>; 205 msi-map = <0x0 &its 0x0 0x1000>; 206 phys = <&pcie_phy>; 207 phy-names = "pcie-phy"; 208 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000 209 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>; 210 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 211 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, 212 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, 213 <&cru SRST_A_PCIE>; 214 reset-names = "core", "mgmt", "mgmt-sticky", "pipe", 215 "pm", "pclk", "aclk"; 216 status = "disabled"; 217 218 pcie0_intc: interrupt-controller { 219 interrupt-controller; 220 #address-cells = <0>; 221 #interrupt-cells = <1>; 222 }; 223 }; 224 225 gmac: ethernet@fe300000 { 226 compatible = "rockchip,rk3399-gmac"; 227 reg = <0x0 0xfe300000 0x0 0x10000>; 228 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 229 interrupt-names = "macirq"; 230 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 231 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, 232 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, 233 <&cru PCLK_GMAC>; 234 clock-names = "stmmaceth", "mac_clk_rx", 235 "mac_clk_tx", "clk_mac_ref", 236 "clk_mac_refout", "aclk_mac", 237 "pclk_mac"; 238 power-domains = <&power RK3399_PD_GMAC>; 239 resets = <&cru SRST_A_GMAC>; 240 reset-names = "stmmaceth"; 241 rockchip,grf = <&grf>; 242 status = "disabled"; 243 }; 244 245 sdio0: dwmmc@fe310000 { 246 compatible = "rockchip,rk3399-dw-mshc", 247 "rockchip,rk3288-dw-mshc"; 248 reg = <0x0 0xfe310000 0x0 0x4000>; 249 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>; 250 max-frequency = <150000000>; 251 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 252 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 253 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 254 fifo-depth = <0x100>; 255 power-domains = <&power RK3399_PD_SDIOAUDIO>; 256 resets = <&cru SRST_SDIO0>; 257 reset-names = "reset"; 258 status = "disabled"; 259 }; 260 261 sdmmc: dwmmc@fe320000 { 262 compatible = "rockchip,rk3399-dw-mshc", 263 "rockchip,rk3288-dw-mshc"; 264 reg = <0x0 0xfe320000 0x0 0x4000>; 265 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; 266 max-frequency = <150000000>; 267 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 268 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 269 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 270 fifo-depth = <0x100>; 271 power-domains = <&power RK3399_PD_SD>; 272 resets = <&cru SRST_SDMMC>; 273 reset-names = "reset"; 274 status = "disabled"; 275 }; 276 277 sdhci: sdhci@fe330000 { 278 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; 279 reg = <0x0 0xfe330000 0x0 0x10000>; 280 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 281 arasan,soc-ctl-syscon = <&grf>; 282 assigned-clocks = <&cru SCLK_EMMC>; 283 assigned-clock-rates = <200000000>; 284 max-frequency = <200000000>; 285 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; 286 clock-names = "clk_xin", "clk_ahb"; 287 clock-output-names = "emmc_cardclock"; 288 #clock-cells = <0>; 289 phys = <&emmc_phy>; 290 phy-names = "phy_arasan"; 291 power-domains = <&power RK3399_PD_EMMC>; 292 status = "disabled"; 293 }; 294 295 usb_host0_ehci: usb@fe380000 { 296 compatible = "generic-ehci"; 297 reg = <0x0 0xfe380000 0x0 0x20000>; 298 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>; 299 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 300 <&u2phy0>; 301 clock-names = "usbhost", "arbiter", 302 "utmi"; 303 phys = <&u2phy0_host>; 304 phy-names = "usb"; 305 power-domains = <&power RK3399_PD_PERIHP>; 306 status = "disabled"; 307 }; 308 309 usb_host0_ohci: usb@fe3a0000 { 310 compatible = "generic-ohci"; 311 reg = <0x0 0xfe3a0000 0x0 0x20000>; 312 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>; 313 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 314 <&u2phy0>; 315 clock-names = "usbhost", "arbiter", 316 "utmi"; 317 phys = <&u2phy0_host>; 318 phy-names = "usb"; 319 power-domains = <&power RK3399_PD_PERIHP>; 320 status = "disabled"; 321 }; 322 323 usb_host1_ehci: usb@fe3c0000 { 324 compatible = "generic-ehci"; 325 reg = <0x0 0xfe3c0000 0x0 0x20000>; 326 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>; 327 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 328 <&u2phy1>; 329 clock-names = "usbhost", "arbiter", 330 "utmi"; 331 phys = <&u2phy1_host>; 332 phy-names = "usb"; 333 power-domains = <&power RK3399_PD_PERIHP>; 334 status = "disabled"; 335 }; 336 337 usb_host1_ohci: usb@fe3e0000 { 338 compatible = "generic-ohci"; 339 reg = <0x0 0xfe3e0000 0x0 0x20000>; 340 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>; 341 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 342 <&u2phy1>; 343 clock-names = "usbhost", "arbiter", 344 "utmi"; 345 phys = <&u2phy1_host>; 346 phy-names = "usb"; 347 power-domains = <&power RK3399_PD_PERIHP>; 348 status = "disabled"; 349 }; 350 351 usbdrd3_0: dwc3_typec0: usb@fe800000 { 352 compatible = "rockchip,rk3399-dwc3"; 353 #address-cells = <2>; 354 #size-cells = <2>; 355 ranges; 356 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, 357 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 358 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 359 clock-names = "ref_clk", "suspend_clk", 360 "bus_clk", "aclk_usb3_rksoc_axi_perf", 361 "aclk_usb3", "grf_clk"; 362 resets = <&cru SRST_A_USB3_OTG0>; 363 reset-names = "usb3-otg"; 364 status = "disabled"; 365 366 usbdrd_dwc3_0: dwc3 { 367 compatible = "snps,dwc3"; 368 reg = <0x0 0xfe800000 0x0 0x100000>; 369 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 370 dr_mode = "otg"; 371 phys = <&u2phy0_otg>, <&tcphy0_usb3>; 372 phy-names = "usb2-phy", "usb3-phy"; 373 phy_type = "utmi_wide"; 374 snps,dis_enblslpm_quirk; 375 snps,dis-u2-freeclk-exists-quirk; 376 snps,dis_u2_susphy_quirk; 377 snps,dis-del-phy-power-chg-quirk; 378 snps,dis-tx-ipgap-linecheck-quirk; 379 power-domains = <&power RK3399_PD_USB3>; 380 status = "disabled"; 381 }; 382 }; 383 384 dwc3_typec1: usbdrd3_1: usb@fe900000 { 385 compatible = "rockchip,rk3399-dwc3"; 386 #address-cells = <2>; 387 #size-cells = <2>; 388 ranges; 389 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, 390 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 391 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 392 clock-names = "ref_clk", "suspend_clk", 393 "bus_clk", "aclk_usb3_rksoc_axi_perf", 394 "aclk_usb3", "grf_clk"; 395 resets = <&cru SRST_A_USB3_OTG1>; 396 reset-names = "usb3-otg"; 397 status = "disabled"; 398 399 usbdrd_dwc3_1: dwc3 { 400 compatible = "snps,dwc3"; 401 reg = <0x0 0xfe900000 0x0 0x100000>; 402 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 403 dr_mode = "otg"; 404 phys = <&u2phy1_otg>, <&tcphy1_usb3>; 405 phy-names = "usb2-phy", "usb3-phy"; 406 phy_type = "utmi_wide"; 407 snps,dis_enblslpm_quirk; 408 snps,dis-u2-freeclk-exists-quirk; 409 snps,dis_u2_susphy_quirk; 410 snps,dis-del-phy-power-chg-quirk; 411 snps,dis-tx-ipgap-linecheck-quirk; 412 power-domains = <&power RK3399_PD_USB3>; 413 status = "disabled"; 414 }; 415 }; 416 417 cdn_dp: dp@fec00000 { 418 compatible = "rockchip,rk3399-cdn-dp"; 419 reg = <0x0 0xfec00000 0x0 0x100000>; 420 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 421 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>; 422 assigned-clock-rates = <100000000>, <200000000>; 423 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, 424 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; 425 clock-names = "core-clk", "pclk", "spdif", "grf"; 426 phys = <&tcphy0_dp>, <&tcphy1_dp>; 427 power-domains = <&power RK3399_PD_HDCP>; 428 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, 429 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>; 430 reset-names = "spdif", "dptx", "apb", "core"; 431 rockchip,grf = <&grf>; 432 #sound-dai-cells = <1>; 433 status = "disabled"; 434 435 ports { 436 dp_in: port { 437 #address-cells = <1>; 438 #size-cells = <0>; 439 440 dp_in_vopb: endpoint@0 { 441 reg = <0>; 442 remote-endpoint = <&vopb_out_dp>; 443 }; 444 445 dp_in_vopl: endpoint@1 { 446 reg = <1>; 447 remote-endpoint = <&vopl_out_dp>; 448 }; 449 }; 450 }; 451 }; 452 453 gic: interrupt-controller@fee00000 { 454 compatible = "arm,gic-v3"; 455 #interrupt-cells = <4>; 456 #address-cells = <2>; 457 #size-cells = <2>; 458 ranges; 459 interrupt-controller; 460 461 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ 462 <0x0 0xfef00000 0 0xc0000>, /* GICR */ 463 <0x0 0xfff00000 0 0x10000>, /* GICC */ 464 <0x0 0xfff10000 0 0x10000>, /* GICH */ 465 <0x0 0xfff20000 0 0x10000>; /* GICV */ 466 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 467 its: interrupt-controller@fee20000 { 468 compatible = "arm,gic-v3-its"; 469 msi-controller; 470 reg = <0x0 0xfee20000 0x0 0x20000>; 471 }; 472 473 ppi-partitions { 474 ppi_cluster0: interrupt-partition-0 { 475 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 476 }; 477 478 ppi_cluster1: interrupt-partition-1 { 479 affinity = <&cpu_b0 &cpu_b1>; 480 }; 481 }; 482 }; 483 484 saradc: saradc@ff100000 { 485 compatible = "rockchip,rk3399-saradc"; 486 reg = <0x0 0xff100000 0x0 0x100>; 487 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>; 488 #io-channel-cells = <1>; 489 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 490 clock-names = "saradc", "apb_pclk"; 491 resets = <&cru SRST_P_SARADC>; 492 reset-names = "saradc-apb"; 493 status = "disabled"; 494 }; 495 496 i2c1: i2c@ff110000 { 497 compatible = "rockchip,rk3399-i2c"; 498 reg = <0x0 0xff110000 0x0 0x1000>; 499 assigned-clocks = <&cru SCLK_I2C1>; 500 assigned-clock-rates = <200000000>; 501 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 502 clock-names = "i2c", "pclk"; 503 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>; 504 pinctrl-names = "default"; 505 pinctrl-0 = <&i2c1_xfer>; 506 #address-cells = <1>; 507 #size-cells = <0>; 508 status = "disabled"; 509 }; 510 511 i2c2: i2c@ff120000 { 512 compatible = "rockchip,rk3399-i2c"; 513 reg = <0x0 0xff120000 0x0 0x1000>; 514 assigned-clocks = <&cru SCLK_I2C2>; 515 assigned-clock-rates = <200000000>; 516 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 517 clock-names = "i2c", "pclk"; 518 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>; 519 pinctrl-names = "default"; 520 pinctrl-0 = <&i2c2_xfer>; 521 #address-cells = <1>; 522 #size-cells = <0>; 523 status = "disabled"; 524 }; 525 526 i2c3: i2c@ff130000 { 527 compatible = "rockchip,rk3399-i2c"; 528 reg = <0x0 0xff130000 0x0 0x1000>; 529 assigned-clocks = <&cru SCLK_I2C3>; 530 assigned-clock-rates = <200000000>; 531 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 532 clock-names = "i2c", "pclk"; 533 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>; 534 pinctrl-names = "default"; 535 pinctrl-0 = <&i2c3_xfer>; 536 #address-cells = <1>; 537 #size-cells = <0>; 538 status = "disabled"; 539 }; 540 541 i2c5: i2c@ff140000 { 542 compatible = "rockchip,rk3399-i2c"; 543 reg = <0x0 0xff140000 0x0 0x1000>; 544 assigned-clocks = <&cru SCLK_I2C5>; 545 assigned-clock-rates = <200000000>; 546 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; 547 clock-names = "i2c", "pclk"; 548 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>; 549 pinctrl-names = "default"; 550 pinctrl-0 = <&i2c5_xfer>; 551 #address-cells = <1>; 552 #size-cells = <0>; 553 status = "disabled"; 554 }; 555 556 i2c6: i2c@ff150000 { 557 compatible = "rockchip,rk3399-i2c"; 558 reg = <0x0 0xff150000 0x0 0x1000>; 559 assigned-clocks = <&cru SCLK_I2C6>; 560 assigned-clock-rates = <200000000>; 561 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; 562 clock-names = "i2c", "pclk"; 563 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>; 564 pinctrl-names = "default"; 565 pinctrl-0 = <&i2c6_xfer>; 566 #address-cells = <1>; 567 #size-cells = <0>; 568 status = "disabled"; 569 }; 570 571 i2c7: i2c@ff160000 { 572 compatible = "rockchip,rk3399-i2c"; 573 reg = <0x0 0xff160000 0x0 0x1000>; 574 assigned-clocks = <&cru SCLK_I2C7>; 575 assigned-clock-rates = <200000000>; 576 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; 577 clock-names = "i2c", "pclk"; 578 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>; 579 pinctrl-names = "default"; 580 pinctrl-0 = <&i2c7_xfer>; 581 #address-cells = <1>; 582 #size-cells = <0>; 583 status = "disabled"; 584 }; 585 586 uart0: serial@ff180000 { 587 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 588 reg = <0x0 0xff180000 0x0 0x100>; 589 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 590 clock-names = "baudclk", "apb_pclk"; 591 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 592 reg-shift = <2>; 593 reg-io-width = <4>; 594 pinctrl-names = "default"; 595 pinctrl-0 = <&uart0_xfer>; 596 status = "disabled"; 597 }; 598 599 uart1: serial@ff190000 { 600 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 601 reg = <0x0 0xff190000 0x0 0x100>; 602 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 603 clock-names = "baudclk", "apb_pclk"; 604 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>; 605 reg-shift = <2>; 606 reg-io-width = <4>; 607 pinctrl-names = "default"; 608 pinctrl-0 = <&uart1_xfer>; 609 status = "disabled"; 610 }; 611 612 uart2: serial@ff1a0000 { 613 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 614 reg = <0x0 0xff1a0000 0x0 0x100>; 615 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 616 clock-names = "baudclk", "apb_pclk"; 617 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 618 clock-frequency = <24000000>; 619 reg-shift = <2>; 620 reg-io-width = <4>; 621 pinctrl-names = "default"; 622 pinctrl-0 = <&uart2c_xfer>; 623 status = "disabled"; 624 }; 625 626 uart3: serial@ff1b0000 { 627 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 628 reg = <0x0 0xff1b0000 0x0 0x100>; 629 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 630 clock-names = "baudclk", "apb_pclk"; 631 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 632 reg-shift = <2>; 633 reg-io-width = <4>; 634 pinctrl-names = "default"; 635 pinctrl-0 = <&uart3_xfer>; 636 status = "disabled"; 637 }; 638 639 spi0: spi@ff1c0000 { 640 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 641 reg = <0x0 0xff1c0000 0x0 0x1000>; 642 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 643 clock-names = "spiclk", "apb_pclk"; 644 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>; 645 pinctrl-names = "default"; 646 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 647 #address-cells = <1>; 648 #size-cells = <0>; 649 status = "disabled"; 650 }; 651 652 spi1: spi@ff1d0000 { 653 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 654 reg = <0x0 0xff1d0000 0x0 0x1000>; 655 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 656 clock-names = "spiclk", "apb_pclk"; 657 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>; 658 pinctrl-names = "default"; 659 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 660 #address-cells = <1>; 661 #size-cells = <0>; 662 status = "disabled"; 663 }; 664 665 spi2: spi@ff1e0000 { 666 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 667 reg = <0x0 0xff1e0000 0x0 0x1000>; 668 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 669 clock-names = "spiclk", "apb_pclk"; 670 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>; 671 pinctrl-names = "default"; 672 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 673 #address-cells = <1>; 674 #size-cells = <0>; 675 status = "disabled"; 676 }; 677 678 spi4: spi@ff1f0000 { 679 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 680 reg = <0x0 0xff1f0000 0x0 0x1000>; 681 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; 682 clock-names = "spiclk", "apb_pclk"; 683 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>; 684 pinctrl-names = "default"; 685 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; 686 #address-cells = <1>; 687 #size-cells = <0>; 688 status = "disabled"; 689 }; 690 691 spi5: spi@ff200000 { 692 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 693 reg = <0x0 0xff200000 0x0 0x1000>; 694 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; 695 clock-names = "spiclk", "apb_pclk"; 696 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>; 697 pinctrl-names = "default"; 698 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; 699 #address-cells = <1>; 700 #size-cells = <0>; 701 status = "disabled"; 702 }; 703 704 thermal_zones: thermal-zones { 705 cpu_thermal: cpu { 706 polling-delay-passive = <100>; 707 polling-delay = <1000>; 708 709 thermal-sensors = <&tsadc 0>; 710 711 trips { 712 cpu_alert0: cpu_alert0 { 713 temperature = <70000>; 714 hysteresis = <2000>; 715 type = "passive"; 716 }; 717 cpu_alert1: cpu_alert1 { 718 temperature = <75000>; 719 hysteresis = <2000>; 720 type = "passive"; 721 }; 722 cpu_crit: cpu_crit { 723 temperature = <95000>; 724 hysteresis = <2000>; 725 type = "critical"; 726 }; 727 }; 728 729 cooling-maps { 730 map0 { 731 trip = <&cpu_alert0>; 732 cooling-device = 733 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 734 }; 735 map1 { 736 trip = <&cpu_alert1>; 737 cooling-device = 738 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 739 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 740 }; 741 }; 742 }; 743 744 gpu_thermal: gpu { 745 polling-delay-passive = <100>; 746 polling-delay = <1000>; 747 748 thermal-sensors = <&tsadc 1>; 749 750 trips { 751 gpu_alert0: gpu_alert0 { 752 temperature = <75000>; 753 hysteresis = <2000>; 754 type = "passive"; 755 }; 756 gpu_crit: gpu_crit { 757 temperature = <95000>; 758 hysteresis = <2000>; 759 type = "critical"; 760 }; 761 }; 762 763 cooling-maps { 764 map0 { 765 trip = <&gpu_alert0>; 766 cooling-device = 767 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 768 }; 769 }; 770 }; 771 }; 772 773 tsadc: tsadc@ff260000 { 774 compatible = "rockchip,rk3399-tsadc"; 775 reg = <0x0 0xff260000 0x0 0x100>; 776 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 777 assigned-clocks = <&cru SCLK_TSADC>; 778 assigned-clock-rates = <750000>; 779 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 780 clock-names = "tsadc", "apb_pclk"; 781 resets = <&cru SRST_TSADC>; 782 reset-names = "tsadc-apb"; 783 rockchip,grf = <&grf>; 784 rockchip,hw-tshut-temp = <95000>; 785 pinctrl-names = "init", "default", "sleep"; 786 pinctrl-0 = <&otp_gpio>; 787 pinctrl-1 = <&otp_out>; 788 pinctrl-2 = <&otp_gpio>; 789 #thermal-sensor-cells = <1>; 790 status = "disabled"; 791 }; 792 793 qos_emmc: qos@ffa58000 { 794 compatible = "syscon"; 795 reg = <0x0 0xffa58000 0x0 0x20>; 796 }; 797 798 qos_gmac: qos@ffa5c000 { 799 compatible = "syscon"; 800 reg = <0x0 0xffa5c000 0x0 0x20>; 801 }; 802 803 qos_pcie: qos@ffa60080 { 804 compatible = "syscon"; 805 reg = <0x0 0xffa60080 0x0 0x20>; 806 }; 807 808 qos_usb_host0: qos@ffa60100 { 809 compatible = "syscon"; 810 reg = <0x0 0xffa60100 0x0 0x20>; 811 }; 812 813 qos_usb_host1: qos@ffa60180 { 814 compatible = "syscon"; 815 reg = <0x0 0xffa60180 0x0 0x20>; 816 }; 817 818 qos_usb_otg0: qos@ffa70000 { 819 compatible = "syscon"; 820 reg = <0x0 0xffa70000 0x0 0x20>; 821 }; 822 823 qos_usb_otg1: qos@ffa70080 { 824 compatible = "syscon"; 825 reg = <0x0 0xffa70080 0x0 0x20>; 826 }; 827 828 qos_sd: qos@ffa74000 { 829 compatible = "syscon"; 830 reg = <0x0 0xffa74000 0x0 0x20>; 831 }; 832 833 qos_sdioaudio: qos@ffa76000 { 834 compatible = "syscon"; 835 reg = <0x0 0xffa76000 0x0 0x20>; 836 }; 837 838 qos_hdcp: qos@ffa90000 { 839 compatible = "syscon"; 840 reg = <0x0 0xffa90000 0x0 0x20>; 841 }; 842 843 qos_iep: qos@ffa98000 { 844 compatible = "syscon"; 845 reg = <0x0 0xffa98000 0x0 0x20>; 846 }; 847 848 qos_isp0_m0: qos@ffaa0000 { 849 compatible = "syscon"; 850 reg = <0x0 0xffaa0000 0x0 0x20>; 851 }; 852 853 qos_isp0_m1: qos@ffaa0080 { 854 compatible = "syscon"; 855 reg = <0x0 0xffaa0080 0x0 0x20>; 856 }; 857 858 qos_isp1_m0: qos@ffaa8000 { 859 compatible = "syscon"; 860 reg = <0x0 0xffaa8000 0x0 0x20>; 861 }; 862 863 qos_isp1_m1: qos@ffaa8080 { 864 compatible = "syscon"; 865 reg = <0x0 0xffaa8080 0x0 0x20>; 866 }; 867 868 qos_rga_r: qos@ffab0000 { 869 compatible = "syscon"; 870 reg = <0x0 0xffab0000 0x0 0x20>; 871 }; 872 873 qos_rga_w: qos@ffab0080 { 874 compatible = "syscon"; 875 reg = <0x0 0xffab0080 0x0 0x20>; 876 }; 877 878 qos_video_m0: qos@ffab8000 { 879 compatible = "syscon"; 880 reg = <0x0 0xffab8000 0x0 0x20>; 881 }; 882 883 qos_video_m1_r: qos@ffac0000 { 884 compatible = "syscon"; 885 reg = <0x0 0xffac0000 0x0 0x20>; 886 }; 887 888 qos_video_m1_w: qos@ffac0080 { 889 compatible = "syscon"; 890 reg = <0x0 0xffac0080 0x0 0x20>; 891 }; 892 893 qos_vop_big_r: qos@ffac8000 { 894 compatible = "syscon"; 895 reg = <0x0 0xffac8000 0x0 0x20>; 896 }; 897 898 qos_vop_big_w: qos@ffac8080 { 899 compatible = "syscon"; 900 reg = <0x0 0xffac8080 0x0 0x20>; 901 }; 902 903 qos_vop_little: qos@ffad0000 { 904 compatible = "syscon"; 905 reg = <0x0 0xffad0000 0x0 0x20>; 906 }; 907 908 qos_perihp: qos@ffad8080 { 909 compatible = "syscon"; 910 reg = <0x0 0xffad8080 0x0 0x20>; 911 }; 912 913 qos_gpu: qos@ffae0000 { 914 compatible = "syscon"; 915 reg = <0x0 0xffae0000 0x0 0x20>; 916 }; 917 918 pmu: power-management@ff310000 { 919 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; 920 reg = <0x0 0xff310000 0x0 0x1000>; 921 922 /* 923 * Note: RK3399 supports 6 voltage domains including VD_CORE_L, 924 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU. 925 * Some of the power domains are grouped together for every 926 * voltage domain. 927 * The detail contents as below. 928 */ 929 power: power-controller { 930 compatible = "rockchip,rk3399-power-controller"; 931 #power-domain-cells = <1>; 932 #address-cells = <1>; 933 #size-cells = <0>; 934 935 /* These power domains are grouped by VD_CENTER */ 936 pd_iep@RK3399_PD_IEP { 937 reg = <RK3399_PD_IEP>; 938 clocks = <&cru ACLK_IEP>, 939 <&cru HCLK_IEP>; 940 pm_qos = <&qos_iep>; 941 }; 942 pd_rga@RK3399_PD_RGA { 943 reg = <RK3399_PD_RGA>; 944 clocks = <&cru ACLK_RGA>, 945 <&cru HCLK_RGA>; 946 pm_qos = <&qos_rga_r>, 947 <&qos_rga_w>; 948 }; 949 pd_vcodec@RK3399_PD_VCODEC { 950 reg = <RK3399_PD_VCODEC>; 951 clocks = <&cru ACLK_VCODEC>, 952 <&cru HCLK_VCODEC>; 953 pm_qos = <&qos_video_m0>; 954 }; 955 pd_vdu@RK3399_PD_VDU { 956 reg = <RK3399_PD_VDU>; 957 clocks = <&cru ACLK_VDU>, 958 <&cru HCLK_VDU>; 959 pm_qos = <&qos_video_m1_r>, 960 <&qos_video_m1_w>; 961 }; 962 963 /* These power domains are grouped by VD_GPU */ 964 pd_gpu@RK3399_PD_GPU { 965 reg = <RK3399_PD_GPU>; 966 clocks = <&cru ACLK_GPU>; 967 pm_qos = <&qos_gpu>; 968 }; 969 970 /* These power domains are grouped by VD_LOGIC */ 971 pd_edp@RK3399_PD_EDP { 972 reg = <RK3399_PD_EDP>; 973 clocks = <&cru PCLK_EDP_CTRL>; 974 }; 975 pd_emmc@RK3399_PD_EMMC { 976 reg = <RK3399_PD_EMMC>; 977 clocks = <&cru ACLK_EMMC>; 978 pm_qos = <&qos_emmc>; 979 }; 980 pd_gmac@RK3399_PD_GMAC { 981 reg = <RK3399_PD_GMAC>; 982 clocks = <&cru ACLK_GMAC>, 983 <&cru PCLK_GMAC>; 984 pm_qos = <&qos_gmac>; 985 }; 986 pd_perihp@RK3399_PD_PERIHP { 987 reg = <RK3399_PD_PERIHP>; 988 #address-cells = <1>; 989 #size-cells = <0>; 990 clocks = <&cru ACLK_PERIHP>; 991 pm_qos = <&qos_perihp>, 992 <&qos_pcie>, 993 <&qos_usb_host0>, 994 <&qos_usb_host1>; 995 996 pd_sd@RK3399_PD_SD { 997 reg = <RK3399_PD_SD>; 998 clocks = <&cru HCLK_SDMMC>, 999 <&cru SCLK_SDMMC>; 1000 pm_qos = <&qos_sd>; 1001 }; 1002 }; 1003 pd_sdioaudio@RK3399_PD_SDIOAUDIO { 1004 reg = <RK3399_PD_SDIOAUDIO>; 1005 clocks = <&cru HCLK_SDIO>; 1006 pm_qos = <&qos_sdioaudio>; 1007 }; 1008 pd_usb3@RK3399_PD_USB3 { 1009 reg = <RK3399_PD_USB3>; 1010 clocks = <&cru ACLK_USB3>; 1011 pm_qos = <&qos_usb_otg0>, 1012 <&qos_usb_otg1>; 1013 }; 1014 pd_vio@RK3399_PD_VIO { 1015 reg = <RK3399_PD_VIO>; 1016 #address-cells = <1>; 1017 #size-cells = <0>; 1018 1019 pd_hdcp@RK3399_PD_HDCP { 1020 reg = <RK3399_PD_HDCP>; 1021 clocks = <&cru ACLK_HDCP>, 1022 <&cru HCLK_HDCP>, 1023 <&cru PCLK_HDCP>; 1024 pm_qos = <&qos_hdcp>; 1025 }; 1026 pd_isp0@RK3399_PD_ISP0 { 1027 reg = <RK3399_PD_ISP0>; 1028 clocks = <&cru ACLK_ISP0>, 1029 <&cru HCLK_ISP0>; 1030 pm_qos = <&qos_isp0_m0>, 1031 <&qos_isp0_m1>; 1032 }; 1033 pd_isp1@RK3399_PD_ISP1 { 1034 reg = <RK3399_PD_ISP1>; 1035 clocks = <&cru ACLK_ISP1>, 1036 <&cru HCLK_ISP1>; 1037 pm_qos = <&qos_isp1_m0>, 1038 <&qos_isp1_m1>; 1039 }; 1040 pd_tcpc0@RK3399_PD_TCPC0 { 1041 reg = <RK3399_PD_TCPD0>; 1042 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1043 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1044 }; 1045 pd_tcpc1@RK3399_PD_TCPC1 { 1046 reg = <RK3399_PD_TCPD1>; 1047 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1048 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1049 }; 1050 pd_vo@RK3399_PD_VO { 1051 reg = <RK3399_PD_VO>; 1052 #address-cells = <1>; 1053 #size-cells = <0>; 1054 1055 pd_vopb@RK3399_PD_VOPB { 1056 reg = <RK3399_PD_VOPB>; 1057 clocks = <&cru ACLK_VOP0>, 1058 <&cru HCLK_VOP0>; 1059 pm_qos = <&qos_vop_big_r>, 1060 <&qos_vop_big_w>; 1061 }; 1062 pd_vopl@RK3399_PD_VOPL { 1063 reg = <RK3399_PD_VOPL>; 1064 clocks = <&cru ACLK_VOP1>, 1065 <&cru HCLK_VOP1>; 1066 pm_qos = <&qos_vop_little>; 1067 }; 1068 }; 1069 }; 1070 }; 1071 }; 1072 1073 pmugrf: syscon@ff320000 { 1074 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; 1075 reg = <0x0 0xff320000 0x0 0x1000>; 1076 1077 pmu_io_domains: io-domains { 1078 compatible = "rockchip,rk3399-pmu-io-voltage-domain"; 1079 status = "disabled"; 1080 }; 1081 }; 1082 1083 pmusgrf: syscon@ff330000 { 1084 compatible = "rockchip,rk3399-pmusgrf", "syscon"; 1085 reg = <0x0 0xff330000 0x0 0xe3d4>; 1086 }; 1087 1088 spi3: spi@ff350000 { 1089 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 1090 reg = <0x0 0xff350000 0x0 0x1000>; 1091 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; 1092 clock-names = "spiclk", "apb_pclk"; 1093 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>; 1094 pinctrl-names = "default"; 1095 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; 1096 #address-cells = <1>; 1097 #size-cells = <0>; 1098 status = "disabled"; 1099 }; 1100 1101 uart4: serial@ff370000 { 1102 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 1103 reg = <0x0 0xff370000 0x0 0x100>; 1104 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; 1105 clock-names = "baudclk", "apb_pclk"; 1106 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>; 1107 reg-shift = <2>; 1108 reg-io-width = <4>; 1109 pinctrl-names = "default"; 1110 pinctrl-0 = <&uart4_xfer>; 1111 status = "disabled"; 1112 }; 1113 1114 i2c0: i2c@ff3c0000 { 1115 compatible = "rockchip,rk3399-i2c"; 1116 reg = <0x0 0xff3c0000 0x0 0x1000>; 1117 assigned-clocks = <&pmucru SCLK_I2C0_PMU>; 1118 assigned-clock-rates = <200000000>; 1119 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; 1120 clock-names = "i2c", "pclk"; 1121 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; 1122 pinctrl-names = "default"; 1123 pinctrl-0 = <&i2c0_xfer>; 1124 #address-cells = <1>; 1125 #size-cells = <0>; 1126 status = "disabled"; 1127 }; 1128 1129 i2c4: i2c@ff3d0000 { 1130 compatible = "rockchip,rk3399-i2c"; 1131 reg = <0x0 0xff3d0000 0x0 0x1000>; 1132 assigned-clocks = <&pmucru SCLK_I2C4_PMU>; 1133 assigned-clock-rates = <200000000>; 1134 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; 1135 clock-names = "i2c", "pclk"; 1136 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>; 1137 pinctrl-names = "default"; 1138 pinctrl-0 = <&i2c4_xfer>; 1139 #address-cells = <1>; 1140 #size-cells = <0>; 1141 status = "disabled"; 1142 }; 1143 1144 i2c8: i2c@ff3e0000 { 1145 compatible = "rockchip,rk3399-i2c"; 1146 reg = <0x0 0xff3e0000 0x0 0x1000>; 1147 assigned-clocks = <&pmucru SCLK_I2C8_PMU>; 1148 assigned-clock-rates = <200000000>; 1149 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; 1150 clock-names = "i2c", "pclk"; 1151 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 1152 pinctrl-names = "default"; 1153 pinctrl-0 = <&i2c8_xfer>; 1154 #address-cells = <1>; 1155 #size-cells = <0>; 1156 status = "disabled"; 1157 }; 1158 1159 pwm0: pwm@ff420000 { 1160 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1161 reg = <0x0 0xff420000 0x0 0x10>; 1162 #pwm-cells = <3>; 1163 pinctrl-names = "default"; 1164 pinctrl-0 = <&pwm0_pin>; 1165 clocks = <&pmucru PCLK_RKPWM_PMU>; 1166 clock-names = "pwm"; 1167 status = "disabled"; 1168 }; 1169 1170 pwm1: pwm@ff420010 { 1171 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1172 reg = <0x0 0xff420010 0x0 0x10>; 1173 #pwm-cells = <3>; 1174 pinctrl-names = "default"; 1175 pinctrl-0 = <&pwm1_pin>; 1176 clocks = <&pmucru PCLK_RKPWM_PMU>; 1177 clock-names = "pwm"; 1178 status = "disabled"; 1179 }; 1180 1181 pwm2: pwm@ff420020 { 1182 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1183 reg = <0x0 0xff420020 0x0 0x10>; 1184 #pwm-cells = <3>; 1185 pinctrl-names = "default"; 1186 pinctrl-0 = <&pwm2_pin>; 1187 clocks = <&pmucru PCLK_RKPWM_PMU>; 1188 clock-names = "pwm"; 1189 status = "disabled"; 1190 }; 1191 1192 pwm3: pwm@ff420030 { 1193 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1194 reg = <0x0 0xff420030 0x0 0x10>; 1195 #pwm-cells = <3>; 1196 pinctrl-names = "default"; 1197 pinctrl-0 = <&pwm3a_pin>; 1198 clocks = <&pmucru PCLK_RKPWM_PMU>; 1199 clock-names = "pwm"; 1200 status = "disabled"; 1201 }; 1202 1203 cic: syscon@ff620000 { 1204 compatible = "rockchip,rk3399-cic", "syscon"; 1205 reg = <0x0 0xff620000 0x0 0x100>; 1206 }; 1207 1208 dfi: dfi@ff630000 { 1209 reg = <0x00 0xff630000 0x00 0x4000>; 1210 compatible = "rockchip,rk3399-dfi"; 1211 rockchip,pmu = <&pmugrf>; 1212 clocks = <&cru PCLK_DDR_MON>; 1213 clock-names = "pclk_ddr_mon"; 1214 status = "disabled"; 1215 }; 1216 1217 dmc: dmc { 1218 compatible = "rockchip,rk3399-dmc"; 1219 devfreq-events = <&dfi>; 1220 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>; 1221 clocks = <&cru SCLK_DDRCLK>; 1222 clock-names = "dmc_clk"; 1223 reg = <0x0 0xffa80000 0x0 0x0800 1224 0x0 0xffa80800 0x0 0x1800 1225 0x0 0xffa82000 0x0 0x2000 1226 0x0 0xffa84000 0x0 0x1000 1227 0x0 0xffa88000 0x0 0x0800 1228 0x0 0xffa88800 0x0 0x1800 1229 0x0 0xffa8a000 0x0 0x2000 1230 0x0 0xffa8c000 0x0 0x1000>; 1231 }; 1232 1233 efuse0: efuse@ff690000 { 1234 compatible = "rockchip,rk3399-efuse"; 1235 reg = <0x0 0xff690000 0x0 0x80>; 1236 #address-cells = <1>; 1237 #size-cells = <1>; 1238 clocks = <&cru PCLK_EFUSE1024NS>; 1239 clock-names = "pclk_efuse"; 1240 1241 /* Data cells */ 1242 cpu_id: cpu-id@7 { 1243 reg = <0x07 0x10>; 1244 }; 1245 cpub_leakage: cpu-leakage@17 { 1246 reg = <0x17 0x1>; 1247 }; 1248 gpu_leakage: gpu-leakage@18 { 1249 reg = <0x18 0x1>; 1250 }; 1251 center_leakage: center-leakage@19 { 1252 reg = <0x19 0x1>; 1253 }; 1254 cpul_leakage: cpu-leakage@1a { 1255 reg = <0x1a 0x1>; 1256 }; 1257 logic_leakage: logic-leakage@1b { 1258 reg = <0x1b 0x1>; 1259 }; 1260 wafer_info: wafer-info@1c { 1261 reg = <0x1c 0x1>; 1262 }; 1263 }; 1264 1265 pmucru: pmu-clock-controller@ff750000 { 1266 compatible = "rockchip,rk3399-pmucru"; 1267 reg = <0x0 0xff750000 0x0 0x1000>; 1268 rockchip,grf = <&pmugrf>; 1269 #clock-cells = <1>; 1270 #reset-cells = <1>; 1271 assigned-clocks = <&pmucru PLL_PPLL>; 1272 assigned-clock-rates = <676000000>; 1273 }; 1274 1275 cru: clock-controller@ff760000 { 1276 compatible = "rockchip,rk3399-cru"; 1277 reg = <0x0 0xff760000 0x0 0x1000>; 1278 rockchip,grf = <&grf>; 1279 #clock-cells = <1>; 1280 #reset-cells = <1>; 1281 assigned-clocks = 1282 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 1283 <&cru PLL_NPLL>, 1284 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 1285 <&cru PCLK_PERIHP>, 1286 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 1287 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 1288 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, 1289 <&cru ACLK_VIO>, <&cru ACLK_HDCP>, 1290 <&cru ACLK_GIC_PRE>, 1291 <&cru PCLK_DDR>; 1292 assigned-clock-rates = 1293 <594000000>, <800000000>, 1294 <1000000000>, 1295 <150000000>, <75000000>, 1296 <37500000>, 1297 <100000000>, <100000000>, 1298 <50000000>, <600000000>, 1299 <100000000>, <50000000>, 1300 <400000000>, <400000000>, 1301 <200000000>, 1302 <200000000>; 1303 }; 1304 1305 grf: syscon@ff770000 { 1306 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; 1307 reg = <0x0 0xff770000 0x0 0x10000>; 1308 #address-cells = <1>; 1309 #size-cells = <1>; 1310 1311 io_domains: io-domains { 1312 compatible = "rockchip,rk3399-io-voltage-domain"; 1313 status = "disabled"; 1314 }; 1315 1316 u2phy0: usb2-phy@e450 { 1317 compatible = "rockchip,rk3399-usb2phy"; 1318 reg = <0xe450 0x10>; 1319 clocks = <&cru SCLK_USB2PHY0_REF>; 1320 clock-names = "phyclk"; 1321 #clock-cells = <0>; 1322 clock-output-names = "clk_usbphy0_480m"; 1323 status = "disabled"; 1324 1325 u2phy0_host: host-port { 1326 #phy-cells = <0>; 1327 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>; 1328 interrupt-names = "linestate"; 1329 status = "disabled"; 1330 }; 1331 1332 u2phy0_otg: otg-port { 1333 #phy-cells = <0>; 1334 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 1335 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 1336 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 1337 interrupt-names = "otg-bvalid", "otg-id", 1338 "linestate"; 1339 status = "disabled"; 1340 }; 1341 }; 1342 1343 u2phy1: usb2-phy@e460 { 1344 compatible = "rockchip,rk3399-usb2phy"; 1345 reg = <0xe460 0x10>; 1346 clocks = <&cru SCLK_USB2PHY1_REF>; 1347 clock-names = "phyclk"; 1348 #clock-cells = <0>; 1349 clock-output-names = "clk_usbphy1_480m"; 1350 status = "disabled"; 1351 1352 u2phy1_host: host-port { 1353 #phy-cells = <0>; 1354 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>; 1355 interrupt-names = "linestate"; 1356 status = "disabled"; 1357 }; 1358 1359 u2phy1_otg: otg-port { 1360 #phy-cells = <0>; 1361 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 1362 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 1363 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 1364 interrupt-names = "otg-bvalid", "otg-id", 1365 "linestate"; 1366 status = "disabled"; 1367 }; 1368 }; 1369 1370 emmc_phy: phy@f780 { 1371 compatible = "rockchip,rk3399-emmc-phy"; 1372 reg = <0xf780 0x24>; 1373 clocks = <&sdhci>; 1374 clock-names = "emmcclk"; 1375 #phy-cells = <0>; 1376 status = "disabled"; 1377 }; 1378 1379 pcie_phy: pcie-phy { 1380 compatible = "rockchip,rk3399-pcie-phy"; 1381 clocks = <&cru SCLK_PCIEPHY_REF>; 1382 clock-names = "refclk"; 1383 #phy-cells = <0>; 1384 resets = <&cru SRST_PCIEPHY>; 1385 reset-names = "phy"; 1386 status = "disabled"; 1387 }; 1388 }; 1389 1390 tcphy0: phy@ff7c0000 { 1391 compatible = "rockchip,rk3399-typec-phy"; 1392 reg = <0x0 0xff7c0000 0x0 0x40000>; 1393 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1394 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1395 clock-names = "tcpdcore", "tcpdphy-ref"; 1396 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; 1397 assigned-clock-rates = <50000000>; 1398 power-domains = <&power RK3399_PD_TCPD0>; 1399 resets = <&cru SRST_UPHY0>, 1400 <&cru SRST_UPHY0_PIPE_L00>, 1401 <&cru SRST_P_UPHY0_TCPHY>; 1402 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1403 rockchip,grf = <&grf>; 1404 status = "disabled"; 1405 1406 tcphy0_dp: dp-port { 1407 #phy-cells = <0>; 1408 }; 1409 1410 tcphy0_usb3: usb3-port { 1411 #phy-cells = <0>; 1412 }; 1413 }; 1414 1415 tcphy1: phy@ff800000 { 1416 compatible = "rockchip,rk3399-typec-phy"; 1417 reg = <0x0 0xff800000 0x0 0x40000>; 1418 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1419 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1420 clock-names = "tcpdcore", "tcpdphy-ref"; 1421 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; 1422 assigned-clock-rates = <50000000>; 1423 power-domains = <&power RK3399_PD_TCPD1>; 1424 resets = <&cru SRST_UPHY1>, 1425 <&cru SRST_UPHY1_PIPE_L00>, 1426 <&cru SRST_P_UPHY1_TCPHY>; 1427 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1428 rockchip,grf = <&grf>; 1429 status = "disabled"; 1430 1431 tcphy1_dp: dp-port { 1432 #phy-cells = <0>; 1433 }; 1434 1435 tcphy1_usb3: usb3-port { 1436 #phy-cells = <0>; 1437 }; 1438 }; 1439 1440 watchdog@ff848000 { 1441 compatible = "snps,dw-wdt"; 1442 reg = <0x0 0xff848000 0x0 0x100>; 1443 clocks = <&cru PCLK_WDT>; 1444 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 1445 }; 1446 1447 rktimer: rktimer@ff850000 { 1448 compatible = "rockchip,rk3399-timer"; 1449 reg = <0x0 0xff850000 0x0 0x1000>; 1450 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; 1451 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; 1452 clock-names = "pclk", "timer"; 1453 }; 1454 1455 spdif: spdif@ff870000 { 1456 compatible = "rockchip,rk3399-spdif"; 1457 reg = <0x0 0xff870000 0x0 0x1000>; 1458 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>; 1459 dmas = <&dmac_bus 7>; 1460 dma-names = "tx"; 1461 clock-names = "mclk", "hclk"; 1462 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 1463 pinctrl-names = "default"; 1464 pinctrl-0 = <&spdif_bus>; 1465 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1466 #sound-dai-cells = <0>; 1467 status = "disabled"; 1468 }; 1469 1470 i2s0: i2s@ff880000 { 1471 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1472 reg = <0x0 0xff880000 0x0 0x1000>; 1473 rockchip,grf = <&grf>; 1474 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>; 1475 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 1476 dma-names = "tx", "rx"; 1477 clock-names = "i2s_clk", "i2s_hclk"; 1478 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; 1479 pinctrl-names = "default"; 1480 pinctrl-0 = <&i2s0_8ch_bus>; 1481 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1482 #sound-dai-cells = <0>; 1483 status = "disabled"; 1484 }; 1485 1486 i2s1: i2s@ff890000 { 1487 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1488 reg = <0x0 0xff890000 0x0 0x1000>; 1489 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>; 1490 dmas = <&dmac_bus 2>, <&dmac_bus 3>; 1491 dma-names = "tx", "rx"; 1492 clock-names = "i2s_clk", "i2s_hclk"; 1493 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; 1494 pinctrl-names = "default"; 1495 pinctrl-0 = <&i2s1_2ch_bus>; 1496 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1497 #sound-dai-cells = <0>; 1498 status = "disabled"; 1499 }; 1500 1501 i2s2: i2s@ff8a0000 { 1502 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1503 reg = <0x0 0xff8a0000 0x0 0x1000>; 1504 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>; 1505 dmas = <&dmac_bus 4>, <&dmac_bus 5>; 1506 dma-names = "tx", "rx"; 1507 clock-names = "i2s_clk", "i2s_hclk"; 1508 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; 1509 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1510 #sound-dai-cells = <0>; 1511 status = "disabled"; 1512 }; 1513 1514 vopl: vop@ff8f0000 { 1515 compatible = "rockchip,rk3399-vop-lit"; 1516 reg = <0x0 0xff8f0000 0x0 0x3efc>; 1517 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1518 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1519 assigned-clock-rates = <400000000>, <100000000>; 1520 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 1521 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1522 iommus = <&vopl_mmu>; 1523 power-domains = <&power RK3399_PD_VOPL>; 1524 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; 1525 reset-names = "axi", "ahb", "dclk"; 1526 status = "disabled"; 1527 1528 vopl_out: port { 1529 #address-cells = <1>; 1530 #size-cells = <0>; 1531 1532 vopl_out_mipi: endpoint@0 { 1533 reg = <0>; 1534 remote-endpoint = <&mipi_in_vopl>; 1535 }; 1536 1537 vopl_out_edp: endpoint@1 { 1538 reg = <1>; 1539 remote-endpoint = <&edp_in_vopl>; 1540 }; 1541 1542 vopl_out_hdmi: endpoint@2 { 1543 reg = <2>; 1544 remote-endpoint = <&hdmi_in_vopl>; 1545 }; 1546 1547 vopl_out_mipi1: endpoint@3 { 1548 reg = <3>; 1549 remote-endpoint = <&mipi1_in_vopl>; 1550 }; 1551 1552 vopl_out_dp: endpoint@4 { 1553 reg = <4>; 1554 remote-endpoint = <&dp_in_vopl>; 1555 }; 1556 }; 1557 }; 1558 1559 vopl_mmu: iommu@ff8f3f00 { 1560 compatible = "rockchip,iommu"; 1561 reg = <0x0 0xff8f3f00 0x0 0x100>; 1562 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1563 interrupt-names = "vopl_mmu"; 1564 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1565 clock-names = "aclk", "iface"; 1566 power-domains = <&power RK3399_PD_VOPL>; 1567 #iommu-cells = <0>; 1568 status = "disabled"; 1569 }; 1570 1571 vopb: vop@ff900000 { 1572 compatible = "rockchip,rk3399-vop-big"; 1573 reg = <0x0 0xff900000 0x0 0x3efc>; 1574 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1575 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1576 assigned-clock-rates = <400000000>, <100000000>; 1577 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 1578 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1579 iommus = <&vopb_mmu>; 1580 power-domains = <&power RK3399_PD_VOPB>; 1581 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; 1582 reset-names = "axi", "ahb", "dclk"; 1583 status = "disabled"; 1584 1585 vopb_out: port { 1586 #address-cells = <1>; 1587 #size-cells = <0>; 1588 1589 vopb_out_edp: endpoint@0 { 1590 reg = <0>; 1591 remote-endpoint = <&edp_in_vopb>; 1592 }; 1593 1594 vopb_out_mipi: endpoint@1 { 1595 reg = <1>; 1596 remote-endpoint = <&mipi_in_vopb>; 1597 }; 1598 1599 vopb_out_hdmi: endpoint@2 { 1600 reg = <2>; 1601 remote-endpoint = <&hdmi_in_vopb>; 1602 }; 1603 1604 vopb_out_mipi1: endpoint@3 { 1605 reg = <3>; 1606 remote-endpoint = <&mipi1_in_vopb>; 1607 }; 1608 1609 vopb_out_dp: endpoint@4 { 1610 reg = <4>; 1611 remote-endpoint = <&dp_in_vopb>; 1612 }; 1613 }; 1614 }; 1615 1616 vopb_mmu: iommu@ff903f00 { 1617 compatible = "rockchip,iommu"; 1618 reg = <0x0 0xff903f00 0x0 0x100>; 1619 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1620 interrupt-names = "vopb_mmu"; 1621 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1622 clock-names = "aclk", "iface"; 1623 power-domains = <&power RK3399_PD_VOPB>; 1624 #iommu-cells = <0>; 1625 status = "disabled"; 1626 }; 1627 1628 isp0_mmu: iommu@ff914000 { 1629 compatible = "rockchip,iommu"; 1630 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; 1631 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>; 1632 interrupt-names = "isp0_mmu"; 1633 clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>; 1634 clock-names = "aclk", "iface"; 1635 #iommu-cells = <0>; 1636 rockchip,disable-mmu-reset; 1637 status = "disabled"; 1638 }; 1639 1640 isp1_mmu: iommu@ff924000 { 1641 compatible = "rockchip,iommu"; 1642 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; 1643 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>; 1644 interrupt-names = "isp1_mmu"; 1645 clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>; 1646 clock-names = "aclk", "iface"; 1647 #iommu-cells = <0>; 1648 rockchip,disable-mmu-reset; 1649 status = "disabled"; 1650 }; 1651 1652 hdmi_sound: hdmi-sound { 1653 compatible = "simple-audio-card"; 1654 simple-audio-card,format = "i2s"; 1655 simple-audio-card,mclk-fs = <256>; 1656 simple-audio-card,name = "hdmi-sound"; 1657 status = "disabled"; 1658 1659 simple-audio-card,cpu { 1660 sound-dai = <&i2s2>; 1661 }; 1662 simple-audio-card,codec { 1663 sound-dai = <&hdmi>; 1664 }; 1665 }; 1666 1667 hdmi: hdmi@ff940000 { 1668 compatible = "rockchip,rk3399-dw-hdmi"; 1669 reg = <0x0 0xff940000 0x0 0x20000>; 1670 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; 1671 clocks = <&cru PCLK_HDMI_CTRL>, 1672 <&cru SCLK_HDMI_SFR>, 1673 <&cru PLL_VPLL>, 1674 <&cru PCLK_VIO_GRF>, 1675 <&cru SCLK_HDMI_CEC>; 1676 clock-names = "iahb", "isfr", "vpll", "grf", "cec"; 1677 power-domains = <&power RK3399_PD_HDCP>; 1678 reg-io-width = <4>; 1679 rockchip,grf = <&grf>; 1680 #sound-dai-cells = <0>; 1681 status = "disabled"; 1682 1683 ports { 1684 hdmi_in: port { 1685 #address-cells = <1>; 1686 #size-cells = <0>; 1687 1688 hdmi_in_vopb: endpoint@0 { 1689 reg = <0>; 1690 remote-endpoint = <&vopb_out_hdmi>; 1691 }; 1692 hdmi_in_vopl: endpoint@1 { 1693 reg = <1>; 1694 remote-endpoint = <&vopl_out_hdmi>; 1695 }; 1696 }; 1697 }; 1698 }; 1699 1700 mipi_dsi: mipi@ff960000 { 1701 compatible = "rockchip,rk3399_mipi_dsi"; 1702 reg = <0x0 0xff960000 0x0 0x8000>; 1703 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>; 1704 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, 1705 <&cru SCLK_DPHY_TX0_CFG>; 1706 clock-names = "ref", "pclk", "phy_cfg"; 1707 rockchip,grf = <&grf>; 1708 #address-cells = <1>; 1709 #size-cells = <0>; 1710 status = "disabled"; 1711 ports { 1712 reg = <1>; 1713 mipi_in: port { 1714 #address-cells = <1>; 1715 #size-cells = <0>; 1716 mipi_in_vopb: endpoint@0 { 1717 reg = <0>; 1718 remote-endpoint = <&vopb_out_mipi>; 1719 }; 1720 mipi_in_vopl: endpoint@1 { 1721 reg = <1>; 1722 remote-endpoint = <&vopl_out_mipi>; 1723 }; 1724 }; 1725 }; 1726 }; 1727 1728 mipi_dsi1: mipi@ff968000 { 1729 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 1730 reg = <0x0 0xff968000 0x0 0x8000>; 1731 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>; 1732 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>, 1733 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>; 1734 clock-names = "ref", "pclk", "phy_cfg", "grf"; 1735 power-domains = <&power RK3399_PD_VIO>; 1736 resets = <&cru SRST_P_MIPI_DSI1>; 1737 reset-names = "apb"; 1738 rockchip,grf = <&grf>; 1739 status = "disabled"; 1740 1741 ports { 1742 #address-cells = <1>; 1743 #size-cells = <0>; 1744 1745 mipi1_in: port@0 { 1746 reg = <0>; 1747 #address-cells = <1>; 1748 #size-cells = <0>; 1749 1750 mipi1_in_vopb: endpoint@0 { 1751 reg = <0>; 1752 remote-endpoint = <&vopb_out_mipi1>; 1753 }; 1754 1755 mipi1_in_vopl: endpoint@1 { 1756 reg = <1>; 1757 remote-endpoint = <&vopl_out_mipi1>; 1758 }; 1759 }; 1760 }; 1761 }; 1762 1763 edp: edp@ff970000 { 1764 compatible = "rockchip,rk3399-edp"; 1765 reg = <0x0 0xff970000 0x0 0x8000>; 1766 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 1767 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>; 1768 clock-names = "dp", "pclk", "grf"; 1769 pinctrl-names = "default"; 1770 pinctrl-0 = <&edp_hpd>; 1771 power-domains = <&power RK3399_PD_EDP>; 1772 resets = <&cru SRST_P_EDP_CTRL>; 1773 reset-names = "dp"; 1774 rockchip,grf = <&grf>; 1775 status = "disabled"; 1776 1777 ports { 1778 #address-cells = <1>; 1779 #size-cells = <0>; 1780 edp_in: port@0 { 1781 reg = <0>; 1782 #address-cells = <1>; 1783 #size-cells = <0>; 1784 1785 edp_in_vopb: endpoint@0 { 1786 reg = <0>; 1787 remote-endpoint = <&vopb_out_edp>; 1788 }; 1789 1790 edp_in_vopl: endpoint@1 { 1791 reg = <1>; 1792 remote-endpoint = <&vopl_out_edp>; 1793 }; 1794 }; 1795 }; 1796 }; 1797 1798 gpu: gpu@ff9a0000 { 1799 compatible = "rockchip,rk3399-mali", "arm,mali-t860"; 1800 reg = <0x0 0xff9a0000 0x0 0x10000>; 1801 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>, 1802 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>, 1803 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>; 1804 interrupt-names = "gpu", "job", "mmu"; 1805 clocks = <&cru ACLK_GPU>; 1806 power-domains = <&power RK3399_PD_GPU>; 1807 status = "disabled"; 1808 }; 1809 1810 pinctrl: pinctrl { 1811 compatible = "rockchip,rk3399-pinctrl"; 1812 rockchip,grf = <&grf>; 1813 rockchip,pmu = <&pmugrf>; 1814 #address-cells = <2>; 1815 #size-cells = <2>; 1816 ranges; 1817 1818 gpio0: gpio0@ff720000 { 1819 compatible = "rockchip,gpio-bank"; 1820 reg = <0x0 0xff720000 0x0 0x100>; 1821 clocks = <&pmucru PCLK_GPIO0_PMU>; 1822 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 1823 1824 gpio-controller; 1825 #gpio-cells = <0x2>; 1826 1827 interrupt-controller; 1828 #interrupt-cells = <0x2>; 1829 }; 1830 1831 gpio1: gpio1@ff730000 { 1832 compatible = "rockchip,gpio-bank"; 1833 reg = <0x0 0xff730000 0x0 0x100>; 1834 clocks = <&pmucru PCLK_GPIO1_PMU>; 1835 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>; 1836 1837 gpio-controller; 1838 #gpio-cells = <0x2>; 1839 1840 interrupt-controller; 1841 #interrupt-cells = <0x2>; 1842 }; 1843 1844 gpio2: gpio2@ff780000 { 1845 compatible = "rockchip,gpio-bank"; 1846 reg = <0x0 0xff780000 0x0 0x100>; 1847 clocks = <&cru PCLK_GPIO2>; 1848 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>; 1849 1850 gpio-controller; 1851 #gpio-cells = <0x2>; 1852 1853 interrupt-controller; 1854 #interrupt-cells = <0x2>; 1855 }; 1856 1857 gpio3: gpio3@ff788000 { 1858 compatible = "rockchip,gpio-bank"; 1859 reg = <0x0 0xff788000 0x0 0x100>; 1860 clocks = <&cru PCLK_GPIO3>; 1861 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>; 1862 1863 gpio-controller; 1864 #gpio-cells = <0x2>; 1865 1866 interrupt-controller; 1867 #interrupt-cells = <0x2>; 1868 }; 1869 1870 gpio4: gpio4@ff790000 { 1871 compatible = "rockchip,gpio-bank"; 1872 reg = <0x0 0xff790000 0x0 0x100>; 1873 clocks = <&cru PCLK_GPIO4>; 1874 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 1875 1876 gpio-controller; 1877 #gpio-cells = <0x2>; 1878 1879 interrupt-controller; 1880 #interrupt-cells = <0x2>; 1881 }; 1882 1883 pcfg_pull_up: pcfg-pull-up { 1884 bias-pull-up; 1885 }; 1886 1887 pcfg_pull_down: pcfg-pull-down { 1888 bias-pull-down; 1889 }; 1890 1891 pcfg_pull_none: pcfg-pull-none { 1892 bias-disable; 1893 }; 1894 1895 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1896 bias-disable; 1897 drive-strength = <12>; 1898 }; 1899 1900 pcfg_pull_none_13ma: pcfg-pull-none-13ma { 1901 bias-disable; 1902 drive-strength = <13>; 1903 }; 1904 1905 pcfg_pull_none_18ma: pcfg-pull-none-18ma { 1906 bias-disable; 1907 drive-strength = <18>; 1908 }; 1909 1910 pcfg_pull_none_20ma: pcfg-pull-none-20ma { 1911 bias-disable; 1912 drive-strength = <20>; 1913 }; 1914 1915 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1916 bias-pull-up; 1917 drive-strength = <2>; 1918 }; 1919 1920 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1921 bias-pull-up; 1922 drive-strength = <8>; 1923 }; 1924 1925 pcfg_pull_up_18ma: pcfg-pull-up-18ma { 1926 bias-pull-up; 1927 drive-strength = <18>; 1928 }; 1929 1930 pcfg_pull_up_20ma: pcfg-pull-up-20ma { 1931 bias-pull-up; 1932 drive-strength = <20>; 1933 }; 1934 1935 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1936 bias-pull-down; 1937 drive-strength = <4>; 1938 }; 1939 1940 pcfg_pull_down_8ma: pcfg-pull-down-8ma { 1941 bias-pull-down; 1942 drive-strength = <8>; 1943 }; 1944 1945 pcfg_pull_down_12ma: pcfg-pull-down-12ma { 1946 bias-pull-down; 1947 drive-strength = <12>; 1948 }; 1949 1950 pcfg_pull_down_18ma: pcfg-pull-down-18ma { 1951 bias-pull-down; 1952 drive-strength = <18>; 1953 }; 1954 1955 pcfg_pull_down_20ma: pcfg-pull-down-20ma { 1956 bias-pull-down; 1957 drive-strength = <20>; 1958 }; 1959 1960 pcfg_output_high: pcfg-output-high { 1961 output-high; 1962 }; 1963 1964 pcfg_output_low: pcfg-output-low { 1965 output-low; 1966 }; 1967 1968 clock { 1969 clk_32k: clk-32k { 1970 rockchip,pins = <0 RK_PA0 RK_FUNC_2 &pcfg_pull_none>; 1971 }; 1972 }; 1973 1974 edp { 1975 edp_hpd: edp-hpd { 1976 rockchip,pins = 1977 <4 RK_PC7 RK_FUNC_2 &pcfg_pull_none>; 1978 }; 1979 }; 1980 1981 gmac { 1982 rgmii_pins: rgmii-pins { 1983 rockchip,pins = 1984 /* mac_txclk */ 1985 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_none_13ma>, 1986 /* mac_rxclk */ 1987 <3 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 1988 /* mac_mdio */ 1989 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, 1990 /* mac_txen */ 1991 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none_13ma>, 1992 /* mac_clk */ 1993 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, 1994 /* mac_rxdv */ 1995 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, 1996 /* mac_mdc */ 1997 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, 1998 /* mac_rxd1 */ 1999 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, 2000 /* mac_rxd0 */ 2001 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, 2002 /* mac_txd1 */ 2003 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none_13ma>, 2004 /* mac_txd0 */ 2005 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none_13ma>, 2006 /* mac_rxd3 */ 2007 <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>, 2008 /* mac_rxd2 */ 2009 <3 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, 2010 /* mac_txd3 */ 2011 <3 RK_PA1 RK_FUNC_1 &pcfg_pull_none_13ma>, 2012 /* mac_txd2 */ 2013 <3 RK_PA0 RK_FUNC_1 &pcfg_pull_none_13ma>; 2014 }; 2015 2016 rmii_pins: rmii-pins { 2017 rockchip,pins = 2018 /* mac_mdio */ 2019 <3 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, 2020 /* mac_txen */ 2021 <3 RK_PB4 RK_FUNC_1 &pcfg_pull_none_13ma>, 2022 /* mac_clk */ 2023 <3 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, 2024 /* mac_rxer */ 2025 <3 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, 2026 /* mac_rxdv */ 2027 <3 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, 2028 /* mac_mdc */ 2029 <3 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, 2030 /* mac_rxd1 */ 2031 <3 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, 2032 /* mac_rxd0 */ 2033 <3 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, 2034 /* mac_txd1 */ 2035 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none_13ma>, 2036 /* mac_txd0 */ 2037 <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none_13ma>; 2038 }; 2039 }; 2040 2041 i2c0 { 2042 i2c0_xfer: i2c0-xfer { 2043 rockchip,pins = 2044 <1 RK_PB7 RK_FUNC_2 &pcfg_pull_none>, 2045 <1 RK_PC0 RK_FUNC_2 &pcfg_pull_none>; 2046 }; 2047 }; 2048 2049 i2c1 { 2050 i2c1_xfer: i2c1-xfer { 2051 rockchip,pins = 2052 <4 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, 2053 <4 RK_PA1 RK_FUNC_1 &pcfg_pull_none>; 2054 }; 2055 }; 2056 2057 i2c2 { 2058 i2c2_xfer: i2c2-xfer { 2059 rockchip,pins = 2060 <2 RK_PA1 RK_FUNC_2 &pcfg_pull_none_12ma>, 2061 <2 RK_PA0 RK_FUNC_2 &pcfg_pull_none_12ma>; 2062 }; 2063 }; 2064 2065 i2c3 { 2066 i2c3_xfer: i2c3-xfer { 2067 rockchip,pins = 2068 <4 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, 2069 <4 RK_PC0 RK_FUNC_1 &pcfg_pull_none>; 2070 }; 2071 }; 2072 2073 i2c4 { 2074 i2c4_xfer: i2c4-xfer { 2075 rockchip,pins = 2076 <1 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, 2077 <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>; 2078 }; 2079 }; 2080 2081 i2c5 { 2082 i2c5_xfer: i2c5-xfer { 2083 rockchip,pins = 2084 <3 RK_PB3 RK_FUNC_2 &pcfg_pull_none>, 2085 <3 RK_PB2 RK_FUNC_2 &pcfg_pull_none>; 2086 }; 2087 }; 2088 2089 i2c6 { 2090 i2c6_xfer: i2c6-xfer { 2091 rockchip,pins = 2092 <2 RK_PB2 RK_FUNC_2 &pcfg_pull_none>, 2093 <2 RK_PB1 RK_FUNC_2 &pcfg_pull_none>; 2094 }; 2095 }; 2096 2097 i2c7 { 2098 i2c7_xfer: i2c7-xfer { 2099 rockchip,pins = 2100 <2 RK_PB0 RK_FUNC_2 &pcfg_pull_none>, 2101 <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>; 2102 }; 2103 }; 2104 2105 i2c8 { 2106 i2c8_xfer: i2c8-xfer { 2107 rockchip,pins = 2108 <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>, 2109 <1 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; 2110 }; 2111 }; 2112 2113 i2s0 { 2114 i2s0_8ch_bus: i2s0-8ch-bus { 2115 rockchip,pins = 2116 <3 RK_PD0 RK_FUNC_1 &pcfg_pull_none>, 2117 <3 RK_PD1 RK_FUNC_1 &pcfg_pull_none>, 2118 <3 RK_PD2 RK_FUNC_1 &pcfg_pull_none>, 2119 <3 RK_PD3 RK_FUNC_1 &pcfg_pull_none>, 2120 <3 RK_PD4 RK_FUNC_1 &pcfg_pull_none>, 2121 <3 RK_PD5 RK_FUNC_1 &pcfg_pull_none>, 2122 <3 RK_PD6 RK_FUNC_1 &pcfg_pull_none>, 2123 <3 RK_PD7 RK_FUNC_1 &pcfg_pull_none>, 2124 <4 RK_PA0 RK_FUNC_1 &pcfg_pull_none>; 2125 }; 2126 }; 2127 2128 i2s1 { 2129 i2s1_2ch_bus: i2s1-2ch-bus { 2130 rockchip,pins = 2131 <4 RK_PA3 RK_FUNC_1 &pcfg_pull_none>, 2132 <4 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, 2133 <4 RK_PA5 RK_FUNC_1 &pcfg_pull_none>, 2134 <4 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, 2135 <4 RK_PA7 RK_FUNC_1 &pcfg_pull_none>; 2136 }; 2137 }; 2138 2139 sdio0 { 2140 sdio0_bus1: sdio0-bus1 { 2141 rockchip,pins = 2142 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>; 2143 }; 2144 2145 sdio0_bus4: sdio0-bus4 { 2146 rockchip,pins = 2147 <2 RK_PC4 RK_FUNC_1 &pcfg_pull_up>, 2148 <2 RK_PC5 RK_FUNC_1 &pcfg_pull_up>, 2149 <2 RK_PC6 RK_FUNC_1 &pcfg_pull_up>, 2150 <2 RK_PC7 RK_FUNC_1 &pcfg_pull_up>; 2151 }; 2152 2153 sdio0_cmd: sdio0-cmd { 2154 rockchip,pins = 2155 <2 RK_PD0 RK_FUNC_1 &pcfg_pull_up>; 2156 }; 2157 2158 sdio0_clk: sdio0-clk { 2159 rockchip,pins = 2160 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; 2161 }; 2162 2163 sdio0_cd: sdio0-cd { 2164 rockchip,pins = 2165 <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>; 2166 }; 2167 2168 sdio0_pwr: sdio0-pwr { 2169 rockchip,pins = 2170 <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>; 2171 }; 2172 2173 sdio0_bkpwr: sdio0-bkpwr { 2174 rockchip,pins = 2175 <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>; 2176 }; 2177 2178 sdio0_wp: sdio0-wp { 2179 rockchip,pins = 2180 <0 RK_PA3 RK_FUNC_1 &pcfg_pull_up>; 2181 }; 2182 2183 sdio0_int: sdio0-int { 2184 rockchip,pins = 2185 <0 RK_PA4 RK_FUNC_1 &pcfg_pull_up>; 2186 }; 2187 }; 2188 2189 sdmmc { 2190 sdmmc_bus1: sdmmc-bus1 { 2191 rockchip,pins = 2192 <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>; 2193 }; 2194 2195 sdmmc_bus4: sdmmc-bus4 { 2196 rockchip,pins = 2197 <4 RK_PB0 RK_FUNC_1 &pcfg_pull_up>, 2198 <4 RK_PB1 RK_FUNC_1 &pcfg_pull_up>, 2199 <4 RK_PB2 RK_FUNC_1 &pcfg_pull_up>, 2200 <4 RK_PB3 RK_FUNC_1 &pcfg_pull_up>; 2201 }; 2202 2203 sdmmc_clk: sdmmc-clk { 2204 rockchip,pins = 2205 <4 RK_PB4 RK_FUNC_1 &pcfg_pull_none>; 2206 }; 2207 2208 sdmmc_cmd: sdmmc-cmd { 2209 rockchip,pins = 2210 <4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>; 2211 }; 2212 2213 sdmmc_cd: sdmmc-cd { 2214 rockchip,pins = 2215 <0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>; 2216 }; 2217 2218 sdmmc_wp: sdmmc-wp { 2219 rockchip,pins = 2220 <0 RK_PB0 RK_FUNC_1 &pcfg_pull_up>; 2221 }; 2222 }; 2223 2224 sleep { 2225 ap_pwroff: ap-pwroff { 2226 rockchip,pins = <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>; 2227 }; 2228 2229 ddrio_pwroff: ddrio-pwroff { 2230 rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_none>; 2231 }; 2232 }; 2233 2234 spdif { 2235 spdif_bus: spdif-bus { 2236 rockchip,pins = 2237 <4 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 2238 }; 2239 2240 spdif_bus_1: spdif-bus-1 { 2241 rockchip,pins = 2242 <3 RK_PC0 RK_FUNC_3 &pcfg_pull_none>; 2243 }; 2244 }; 2245 2246 spi0 { 2247 spi0_clk: spi0-clk { 2248 rockchip,pins = 2249 <3 RK_PA6 RK_FUNC_2 &pcfg_pull_up>; 2250 }; 2251 spi0_cs0: spi0-cs0 { 2252 rockchip,pins = 2253 <3 RK_PA7 RK_FUNC_2 &pcfg_pull_up>; 2254 }; 2255 spi0_cs1: spi0-cs1 { 2256 rockchip,pins = 2257 <3 RK_PB0 RK_FUNC_2 &pcfg_pull_up>; 2258 }; 2259 spi0_tx: spi0-tx { 2260 rockchip,pins = 2261 <3 RK_PA5 RK_FUNC_2 &pcfg_pull_up>; 2262 }; 2263 spi0_rx: spi0-rx { 2264 rockchip,pins = 2265 <3 RK_PA4 RK_FUNC_2 &pcfg_pull_up>; 2266 }; 2267 }; 2268 2269 spi1 { 2270 spi1_clk: spi1-clk { 2271 rockchip,pins = 2272 <1 RK_PB1 RK_FUNC_2 &pcfg_pull_up>; 2273 }; 2274 spi1_cs0: spi1-cs0 { 2275 rockchip,pins = 2276 <1 RK_PB2 RK_FUNC_2 &pcfg_pull_up>; 2277 }; 2278 spi1_rx: spi1-rx { 2279 rockchip,pins = 2280 <1 RK_PA7 RK_FUNC_2 &pcfg_pull_up>; 2281 }; 2282 spi1_tx: spi1-tx { 2283 rockchip,pins = 2284 <1 RK_PB0 RK_FUNC_2 &pcfg_pull_up>; 2285 }; 2286 }; 2287 2288 spi2 { 2289 spi2_clk: spi2-clk { 2290 rockchip,pins = 2291 <2 RK_PB3 RK_FUNC_1 &pcfg_pull_up>; 2292 }; 2293 spi2_cs0: spi2-cs0 { 2294 rockchip,pins = 2295 <2 RK_PB4 RK_FUNC_1 &pcfg_pull_up>; 2296 }; 2297 spi2_rx: spi2-rx { 2298 rockchip,pins = 2299 <2 RK_PB1 RK_FUNC_1 &pcfg_pull_up>; 2300 }; 2301 spi2_tx: spi2-tx { 2302 rockchip,pins = 2303 <2 RK_PB2 RK_FUNC_1 &pcfg_pull_up>; 2304 }; 2305 }; 2306 2307 spi3 { 2308 spi3_clk: spi3-clk { 2309 rockchip,pins = 2310 <1 RK_PC1 RK_FUNC_1 &pcfg_pull_up>; 2311 }; 2312 spi3_cs0: spi3-cs0 { 2313 rockchip,pins = 2314 <1 RK_PC2 RK_FUNC_1 &pcfg_pull_up>; 2315 }; 2316 spi3_rx: spi3-rx { 2317 rockchip,pins = 2318 <1 RK_PB7 RK_FUNC_1 &pcfg_pull_up>; 2319 }; 2320 spi3_tx: spi3-tx { 2321 rockchip,pins = 2322 <1 RK_PC0 RK_FUNC_1 &pcfg_pull_up>; 2323 }; 2324 }; 2325 2326 spi4 { 2327 spi4_clk: spi4-clk { 2328 rockchip,pins = 2329 <3 RK_PA2 RK_FUNC_2 &pcfg_pull_up>; 2330 }; 2331 spi4_cs0: spi4-cs0 { 2332 rockchip,pins = 2333 <3 RK_PA3 RK_FUNC_2 &pcfg_pull_up>; 2334 }; 2335 spi4_rx: spi4-rx { 2336 rockchip,pins = 2337 <3 RK_PA0 RK_FUNC_2 &pcfg_pull_up>; 2338 }; 2339 spi4_tx: spi4-tx { 2340 rockchip,pins = 2341 <3 RK_PA1 RK_FUNC_2 &pcfg_pull_up>; 2342 }; 2343 }; 2344 2345 spi5 { 2346 spi5_clk: spi5-clk { 2347 rockchip,pins = 2348 <2 RK_PC6 RK_FUNC_2 &pcfg_pull_up>; 2349 }; 2350 spi5_cs0: spi5-cs0 { 2351 rockchip,pins = 2352 <2 RK_PC7 RK_FUNC_2 &pcfg_pull_up>; 2353 }; 2354 spi5_rx: spi5-rx { 2355 rockchip,pins = 2356 <2 RK_PC4 RK_FUNC_2 &pcfg_pull_up>; 2357 }; 2358 spi5_tx: spi5-tx { 2359 rockchip,pins = 2360 <2 RK_PC5 RK_FUNC_2 &pcfg_pull_up>; 2361 }; 2362 }; 2363 2364 tsadc { 2365 otp_gpio: otp-gpio { 2366 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 2367 }; 2368 2369 otp_out: otp-out { 2370 rockchip,pins = <1 RK_PA6 RK_FUNC_1 &pcfg_pull_none>; 2371 }; 2372 }; 2373 2374 uart0 { 2375 uart0_xfer: uart0-xfer { 2376 rockchip,pins = 2377 <2 RK_PC0 RK_FUNC_1 &pcfg_pull_up>, 2378 <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>; 2379 }; 2380 2381 uart0_cts: uart0-cts { 2382 rockchip,pins = 2383 <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none>; 2384 }; 2385 2386 uart0_rts: uart0-rts { 2387 rockchip,pins = 2388 <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; 2389 }; 2390 }; 2391 2392 uart1 { 2393 uart1_xfer: uart1-xfer { 2394 rockchip,pins = 2395 <3 RK_PB4 RK_FUNC_2 &pcfg_pull_up>, 2396 <3 RK_PB5 RK_FUNC_2 &pcfg_pull_none>; 2397 }; 2398 }; 2399 2400 uart2a { 2401 uart2a_xfer: uart2a-xfer { 2402 rockchip,pins = 2403 <4 RK_PB0 RK_FUNC_2 &pcfg_pull_up>, 2404 <4 RK_PB1 RK_FUNC_2 &pcfg_pull_none>; 2405 }; 2406 }; 2407 2408 uart2b { 2409 uart2b_xfer: uart2b-xfer { 2410 rockchip,pins = 2411 <4 RK_PC0 RK_FUNC_2 &pcfg_pull_up>, 2412 <4 RK_PC1 RK_FUNC_2 &pcfg_pull_none>; 2413 }; 2414 }; 2415 2416 uart2c { 2417 uart2c_xfer: uart2c-xfer { 2418 rockchip,pins = 2419 <4 RK_PC3 RK_FUNC_1 &pcfg_pull_up>, 2420 <4 RK_PC4 RK_FUNC_1 &pcfg_pull_none>; 2421 }; 2422 }; 2423 2424 uart3 { 2425 uart3_xfer: uart3-xfer { 2426 rockchip,pins = 2427 <3 RK_PB6 RK_FUNC_2 &pcfg_pull_up>, 2428 <3 RK_PB7 RK_FUNC_2 &pcfg_pull_none>; 2429 }; 2430 2431 uart3_cts: uart3-cts { 2432 rockchip,pins = 2433 <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; 2434 }; 2435 2436 uart3_rts: uart3-rts { 2437 rockchip,pins = 2438 <3 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; 2439 }; 2440 }; 2441 2442 uart4 { 2443 uart4_xfer: uart4-xfer { 2444 rockchip,pins = 2445 <1 RK_PA7 RK_FUNC_1 &pcfg_pull_up>, 2446 <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>; 2447 }; 2448 }; 2449 2450 uarthdcp { 2451 uarthdcp_xfer: uarthdcp-xfer { 2452 rockchip,pins = 2453 <4 RK_PC5 RK_FUNC_2 &pcfg_pull_up>, 2454 <4 RK_PC6 RK_FUNC_2 &pcfg_pull_none>; 2455 }; 2456 }; 2457 2458 pwm0 { 2459 pwm0_pin: pwm0-pin { 2460 rockchip,pins = 2461 <4 RK_PC2 RK_FUNC_1 &pcfg_pull_none>; 2462 }; 2463 2464 vop0_pwm_pin: vop0-pwm-pin { 2465 rockchip,pins = 2466 <4 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; 2467 }; 2468 }; 2469 2470 pwm1 { 2471 pwm1_pin: pwm1-pin { 2472 rockchip,pins = 2473 <4 RK_PC6 RK_FUNC_1 &pcfg_pull_none>; 2474 }; 2475 2476 vop1_pwm_pin: vop1-pwm-pin { 2477 rockchip,pins = 2478 <4 RK_PC2 RK_FUNC_3 &pcfg_pull_none>; 2479 }; 2480 }; 2481 2482 pwm2 { 2483 pwm2_pin: pwm2-pin { 2484 rockchip,pins = 2485 <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>; 2486 }; 2487 2488 pwm2_pin_pull_down: pwm2-pin-pull-down { 2489 rockchip,pins = 2490 <1 RK_PC3 RK_FUNC_1 &pcfg_pull_down>; 2491 }; 2492 }; 2493 2494 pwm3a { 2495 pwm3a_pin: pwm3a-pin { 2496 rockchip,pins = 2497 <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>; 2498 }; 2499 }; 2500 2501 pwm3b { 2502 pwm3b_pin: pwm3b-pin { 2503 rockchip,pins = 2504 <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>; 2505 }; 2506 }; 2507 2508 hdmi { 2509 hdmi_i2c_xfer: hdmi-i2c-xfer { 2510 rockchip,pins = 2511 <4 RK_PC1 RK_FUNC_3 &pcfg_pull_none>, 2512 <4 RK_PC0 RK_FUNC_3 &pcfg_pull_none>; 2513 }; 2514 2515 hdmi_cec: hdmi-cec { 2516 rockchip,pins = 2517 <4 RK_PC7 RK_FUNC_1 &pcfg_pull_none>; 2518 }; 2519 }; 2520 2521 pcie { 2522 pcie_clkreqn: pci-clkreqn { 2523 rockchip,pins = 2524 <2 RK_PD2 RK_FUNC_2 &pcfg_pull_none>; 2525 }; 2526 2527 pcie_clkreqnb: pci-clkreqnb { 2528 rockchip,pins = 2529 <4 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; 2530 }; 2531 2532 pcie_clkreqn_cpm: pci-clkreqn-cpm { 2533 rockchip,pins = 2534 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 2535 }; 2536 2537 pcie_clkreqnb_cpm: pci-clkreqnb-cpm { 2538 rockchip,pins = 2539 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 2540 }; 2541 }; 2542 2543 }; 2544}; 2545