| /external/llvm/lib/CodeGen/ |
| D | LiveRegMatrix.cpp | 97 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { in assign()
114 void LiveRegMatrix::unassign(LiveInterval &VirtReg) { in unassign()
139 bool LiveRegMatrix::checkRegMaskInterference(LiveInterval &VirtReg, in checkRegMaskInterference()
157 bool LiveRegMatrix::checkRegUnitInterference(LiveInterval &VirtReg, in checkRegUnitInterference()
171 LiveIntervalUnion::Query &LiveRegMatrix::query(LiveInterval &VirtReg, in query()
179 LiveRegMatrix::checkInterference(LiveInterval &VirtReg, unsigned PhysReg) { in checkInterference()
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| D | RegAllocFast.cpp | 71 unsigned VirtReg; // Virtual register number. member
184 LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) { in findLiveVirtReg()
205 int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) { in getStackSpaceFor()
260 void RAFast::killVirtReg(unsigned VirtReg) { in killVirtReg()
270 void RAFast::spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg) { in spillVirtReg()
419 switch (unsigned VirtReg = PhysRegState[PhysReg]) { in definePhysReg() local
435 switch (unsigned VirtReg = PhysRegState[Alias]) { in definePhysReg() local
462 switch (unsigned VirtReg = PhysRegState[PhysReg]) { in calcSpillCost() local
483 switch (unsigned VirtReg = PhysRegState[Alias]) { in calcSpillCost() local
516 RAFast::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) { in assignVirtToPhysReg()
[all …]
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| D | RegAllocGreedy.cpp | 216 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { in setStage()
494 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) { in LRE_CanEraseVirtReg()
506 void RAGreedy::LRE_WillShrinkVirtReg(unsigned VirtReg) { in LRE_WillShrinkVirtReg()
618 unsigned RAGreedy::tryAssign(LiveInterval &VirtReg, in tryAssign()
662 unsigned RAGreedy::canReassign(LiveInterval &VirtReg, unsigned PrevReg) { in canReassign()
725 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg, in canEvictInterference()
807 void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg, in evictInterference()
858 unsigned RAGreedy::tryEvict(LiveInterval &VirtReg, in tryEvict()
1353 unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order, in tryRegionSplit()
1383 unsigned RAGreedy::calculateRegionSplitCost(LiveInterval &VirtReg, in calculateRegionSplitCost()
[all …]
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| D | LiveIntervalUnion.cpp | 29 void LiveIntervalUnion::unify(LiveInterval &VirtReg, const LiveRange &Range) { in unify()
56 void LiveIntervalUnion::extract(LiveInterval &VirtReg, const LiveRange &Range) { in extract()
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| D | VirtRegMap.cpp | 82 bool VirtRegMap::hasPreferredPhys(unsigned VirtReg) { in hasPreferredPhys()
91 bool VirtRegMap::hasKnownPreference(unsigned VirtReg) { in hasKnownPreference()
291 unsigned VirtReg = TargetRegisterInfo::index2VirtReg(Idx); in addMBBLiveIns() local
398 unsigned VirtReg = MO.getReg(); in rewrite() local
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| D | AllocationOrder.cpp | 30 AllocationOrder::AllocationOrder(unsigned VirtReg, in AllocationOrder()
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| D | RegAllocBasic.cpp | 166 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, in spillInterferences()
220 unsigned RABasic::selectOrSplit(LiveInterval &VirtReg, in selectOrSplit()
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| D | RegAllocBase.cpp | 85 while (LiveInterval *VirtReg = dequeue()) { in allocatePhysRegs() local
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| D | RegisterCoalescer.h | 66 CoalescerPair(unsigned VirtReg, unsigned PhysReg, in CoalescerPair()
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| D | LiveDebugVariables.cpp | 479 void LDVImpl::mapVirtReg(unsigned VirtReg, UserValue *EC) { in mapVirtReg()
485 UserValue *LDVImpl::lookupVirtReg(unsigned VirtReg) { in lookupVirtReg()
923 unsigned VirtReg = Loc.getReg(); in rewriteLocations() local
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | LiveRegMatrix.cpp | 104 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { in assign()
121 void LiveRegMatrix::unassign(LiveInterval &VirtReg) { in unassign()
146 bool LiveRegMatrix::checkRegMaskInterference(LiveInterval &VirtReg, in checkRegMaskInterference()
164 bool LiveRegMatrix::checkRegUnitInterference(LiveInterval &VirtReg, in checkRegUnitInterference()
186 LiveRegMatrix::checkInterference(LiveInterval &VirtReg, unsigned PhysReg) { in checkInterference()
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| D | RegAllocFast.cpp | 86 unsigned VirtReg; ///< Virtual register number. member
201 LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) { in findLiveVirtReg()
231 int RegAllocFast::getStackSpaceFor(unsigned VirtReg, in getStackSpaceFor()
295 void RegAllocFast::killVirtReg(unsigned VirtReg) { in killVirtReg()
306 unsigned VirtReg) { in spillVirtReg()
443 switch (unsigned VirtReg = PhysRegState[PhysReg]) { in definePhysReg() local
459 switch (unsigned VirtReg = PhysRegState[Alias]) { in definePhysReg() local
485 switch (unsigned VirtReg = PhysRegState[PhysReg]) { in calcSpillCost() local
506 switch (unsigned VirtReg = PhysRegState[Alias]) { in calcSpillCost() local
537 RegAllocFast::assignVirtToPhysReg(unsigned VirtReg, MCPhysReg PhysReg) { in assignVirtToPhysReg()
[all …]
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| D | RegAllocGreedy.cpp | 260 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { in setStage()
633 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) { in LRE_CanEraseVirtReg()
648 void RAGreedy::LRE_WillShrinkVirtReg(unsigned VirtReg) { in LRE_WillShrinkVirtReg()
759 unsigned RAGreedy::tryAssign(LiveInterval &VirtReg, in tryAssign()
805 unsigned RAGreedy::canReassign(LiveInterval &VirtReg, unsigned PrevReg) { in canReassign()
868 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg, in canEvictInterference()
957 bool RAGreedy::canEvictInterferenceInRange(LiveInterval &VirtReg, in canEvictInterferenceInRange()
1011 LiveInterval &VirtReg, in getCheapestEvicteeWeight()
1036 void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg, in evictInterference()
1094 unsigned RAGreedy::tryEvict(LiveInterval &VirtReg, in tryEvict()
[all …]
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| D | RegAllocBasic.cpp | 160 void RABasic::LRE_WillShrinkVirtReg(unsigned VirtReg) { in LRE_WillShrinkVirtReg()
205 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, in spillInterferences()
257 unsigned RABasic::selectOrSplit(LiveInterval &VirtReg, in selectOrSplit()
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| D | LiveIntervalUnion.cpp | 30 void LiveIntervalUnion::unify(LiveInterval &VirtReg, const LiveRange &Range) { in unify()
57 void LiveIntervalUnion::extract(LiveInterval &VirtReg, const LiveRange &Range) { in extract()
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| D | AllocationOrder.cpp | 30 AllocationOrder::AllocationOrder(unsigned VirtReg, in AllocationOrder()
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| D | VirtRegMap.cpp | 103 bool VirtRegMap::hasPreferredPhys(unsigned VirtReg) { in hasPreferredPhys()
112 bool VirtRegMap::hasKnownPreference(unsigned VirtReg) { in hasKnownPreference()
316 unsigned VirtReg = TargetRegisterInfo::index2VirtReg(Idx); in addMBBLiveIns() local
519 unsigned VirtReg = MO.getReg(); in rewrite() local
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| D | RegAllocBase.cpp | 89 while (LiveInterval *VirtReg = dequeue()) { in allocatePhysRegs() local
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| D | RegisterCoalescer.h | 63 CoalescerPair(unsigned VirtReg, unsigned PhysReg, in CoalescerPair()
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| D | LiveDebugVariables.cpp | 502 void LDVImpl::mapVirtReg(unsigned VirtReg, UserValue *EC) { in mapVirtReg()
508 UserValue *LDVImpl::lookupVirtReg(unsigned VirtReg) { in lookupVirtReg()
1060 unsigned VirtReg = Loc.getReg(); in rewriteLocations() local
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| /external/llvm/include/llvm/CodeGen/ |
| D | LiveIntervalUnion.h | 88 void unify(LiveInterval &VirtReg) { in unify()
94 void extract(LiveInterval &VirtReg) { in extract()
113 LiveInterval *VirtReg; variable
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| D | VirtRegMap.h | 151 unsigned getOriginal(unsigned VirtReg) const { in getOriginal()
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| D | ScheduleDAGInstrs.h | 36 unsigned VirtReg; member
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | VirtRegMap.h | 147 unsigned getOriginal(unsigned VirtReg) const { in getOriginal()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| D | SystemZRegisterInfo.cpp | 58 SystemZRegisterInfo::getRegAllocationHints(unsigned VirtReg, in getRegAllocationHints()
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