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Searched refs:dividend (Results 1 – 3 of 3) sorted by relevance

/art/runtime/interpreter/
Dinterpreter_common.h814 int32_t dividend, int32_t divisor) in DoIntDivide() argument
821 if (UNLIKELY(dividend == kMinInt && divisor == -1)) { in DoIntDivide()
824 shadow_frame.SetVReg(result_reg, dividend / divisor); in DoIntDivide()
832 int32_t dividend, int32_t divisor) in DoIntRemainder() argument
839 if (UNLIKELY(dividend == kMinInt && divisor == -1)) { in DoIntRemainder()
842 shadow_frame.SetVReg(result_reg, dividend % divisor); in DoIntRemainder()
851 int64_t dividend, in DoLongDivide() argument
859 if (UNLIKELY(dividend == kMinLong && divisor == -1)) { in DoLongDivide()
862 shadow_frame.SetVRegLong(result_reg, dividend / divisor); in DoLongDivide()
871 int64_t dividend, in DoLongRemainder() argument
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/art/compiler/optimizing/
Dcode_generator_arm64.cc3014 Register dividend = InputRegisterAt(instruction, 0); in FOR_EACH_CONDITION_INSTRUCTION() local
3018 __ Add(out, dividend, Operand(dividend, LSR, bits - 1)); in FOR_EACH_CONDITION_INSTRUCTION()
3022 __ Add(temp, dividend, abs_imm - 1); in FOR_EACH_CONDITION_INSTRUCTION()
3023 __ Cmp(dividend, 0); in FOR_EACH_CONDITION_INSTRUCTION()
3024 __ Csel(out, temp, dividend, lt); in FOR_EACH_CONDITION_INSTRUCTION()
3043 Register dividend = InputRegisterAt(instruction, 0); in GenerateDivRemWithAnyConstant() local
3060 __ Smulh(temp, dividend, temp); in GenerateDivRemWithAnyConstant()
3062 __ Smull(temp.X(), dividend, temp); in GenerateDivRemWithAnyConstant()
3067 __ Add(temp, temp, dividend); in GenerateDivRemWithAnyConstant()
3069 __ Sub(temp, temp, dividend); in GenerateDivRemWithAnyConstant()
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Dcode_generator_arm_vixl.cc4130 vixl32::Register dividend = InputRegisterAt(instruction, 0); in DivRemOneOrMinusOne() local
4138 __ Mov(out, dividend); in DivRemOneOrMinusOne()
4140 __ Rsb(out, dividend, 0); in DivRemOneOrMinusOne()
4154 vixl32::Register dividend = InputRegisterAt(instruction, 0); in DivRemByPowerOfTwo() local
4161 __ Lsr(temp, dividend, 32 - ctz_imm); in DivRemByPowerOfTwo()
4163 __ Asr(temp, dividend, 31); in DivRemByPowerOfTwo()
4166 __ Add(out, temp, dividend); in DivRemByPowerOfTwo()
4188 vixl32::Register dividend = InputRegisterAt(instruction, 0); in GenerateDivRemWithAnyConstant() local
4199 __ Smull(temp2, temp1, dividend, temp1); in GenerateDivRemWithAnyConstant()
4202 __ Add(temp1, temp1, dividend); in GenerateDivRemWithAnyConstant()
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