Home
last modified time | relevance | path

Searched refs:MmioWrite32 (Results 1 – 25 of 152) sorted by relevance

1234567

/device/linaro/bootloader/OpenPlatformPkg/Platforms/Hisilicon/D03/EarlyConfigPeim/
DEarlyConfigPeimD03.c73 MmioWrite32 (PERI_SUBCTRL_BASE + SC_TM_CLKEN0_REG, SC_TM_CLKEN0_REG_VALUE); in PlatformTimerStart()
115 MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_EN_REG, SC_BROADCAST_EN_REG_VALUE); in EarlyConfigEntry()
116MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1); in EarlyConfigEntry()
117MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0); in EarlyConfigEntry()
118MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2); in EarlyConfigEntry()
119MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3); in EarlyConfigEntry()
120MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1); in EarlyConfigEntry()
121MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3); in EarlyConfigEntry()
123 MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_EN_REG, SC_BROADCAST_EN_REG_VALUE); in EarlyConfigEntry()
124MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2); in EarlyConfigEntry()
[all …]
/device/linaro/bootloader/edk2/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/
DHdLcd.c38 MmioWrite32(HDLCD_REG_COMMAND, HDLCD_DISABLE); in LcdInitialize()
41 MmioWrite32(HDLCD_REG_INT_MASK, 0); in LcdInitialize()
44 MmioWrite32(HDLCD_REG_FB_BASE, (UINT32) VramBaseAddress); in LcdInitialize()
47 MmioWrite32(HDLCD_REG_BUS_OPTIONS, (4 << 8) | HDLCD_BURST_8); in LcdInitialize()
48MmioWrite32(HDLCD_REG_POLARITIES, HDLCD_PXCLK_LOW | HDLCD_DATA_HIGH | HDLCD_DATEN_HIGH | HDLCD_H… in LcdInitialize()
49 MmioWrite32(HDLCD_REG_PIXEL_FORMAT, HDLCD_LITTLE_ENDIAN | HDLCD_4BYTES_PER_PIXEL); in LcdInitialize()
50 MmioWrite32(HDLCD_REG_RED_SELECT, (0 << 16 | 8 << 8 | 0)); in LcdInitialize()
51 MmioWrite32(HDLCD_REG_GREEN_SELECT, (0 << 16 | 8 << 8 | 8)); in LcdInitialize()
52 MmioWrite32(HDLCD_REG_BLUE_SELECT, (0 << 16 | 8 << 8 | 16)); in LcdInitialize()
93 MmioWrite32(HDLCD_REG_COMMAND, HDLCD_DISABLE); in LcdSetMode()
[all …]
DPL111Lcd.c57 MmioWrite32(PL111_REG_LCD_UP_BASE, (UINT32) VramBaseAddress); in LcdInitialize()
58 MmioWrite32(PL111_REG_LCD_LP_BASE, 0); // We are not using a double buffer in LcdInitialize()
61 MmioWrite32(PL111_REG_LCD_IMSC, 0); in LcdInitialize()
100 MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl & ~1); in LcdSetMode()
103 MmioWrite32 (PL111_REG_LCD_TIMING_0, HOR_AXIS_PANEL(HBackPorch, HFrontPorch, HSync, HRes)); in LcdSetMode()
104 MmioWrite32 (PL111_REG_LCD_TIMING_1, VER_AXIS_PANEL(VBackPorch, VFrontPorch, VSync, VRes)); in LcdSetMode()
105 MmioWrite32 (PL111_REG_LCD_TIMING_2, CLK_SIG_POLARITY(HRes)); in LcdSetMode()
106 MmioWrite32 (PL111_REG_LCD_TIMING_3, 0); in LcdSetMode()
110 MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl); in LcdSetMode()
114 MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl); in LcdSetMode()
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformInitPei/
DPlatformEarlyInit.c347 MmioWrite32 (IO_BASE_ADDRESS + 0x03E0, 0x2003ED01); //EMMC 4.41
348 MmioWrite32 (IO_BASE_ADDRESS + 0x0390, 0x2003EC81);
349 MmioWrite32 (IO_BASE_ADDRESS + 0x03D0, 0x2003EC81);
350 MmioWrite32 (IO_BASE_ADDRESS + 0x0400, 0x2003EC81);
351 MmioWrite32 (IO_BASE_ADDRESS + 0x03B0, 0x2003EC81);
352 MmioWrite32 (IO_BASE_ADDRESS + 0x0360, 0x2003EC81);
353 MmioWrite32 (IO_BASE_ADDRESS + 0x0380, 0x2003EC81);
354 MmioWrite32 (IO_BASE_ADDRESS + 0x03C0, 0x2003EC81);
355 MmioWrite32 (IO_BASE_ADDRESS + 0x0370, 0x2003EC81);
356 MmioWrite32 (IO_BASE_ADDRESS + 0x03F0, 0x2003EC81);
[all …]
/device/linaro/bootloader/edk2/Omap35xxPkg/Library/OmapDmaLib/
DOmapDmaLib.c70 MmioWrite32 (DMA4_CSDP (Channel), RegVal); in EnableDmaChannel()
73 MmioWrite32 (DMA4_CEN (Channel), DMA4->NumberOfElementPerFrame); in EnableDmaChannel()
76 MmioWrite32 (DMA4_CFN (Channel), DMA4->NumberOfFramePerTransferBlock); in EnableDmaChannel()
79 MmioWrite32 (DMA4_CSSA (Channel), DMA4->SourceStartAddress); in EnableDmaChannel()
80 MmioWrite32 (DMA4_CDSA (Channel), DMA4->DestinationStartAddress); in EnableDmaChannel()
100 MmioWrite32 (DMA4_CCR (Channel), RegVal); in EnableDmaChannel()
103 MmioWrite32 (DMA4_CSEI (Channel), DMA4->SourceElementIndex); in EnableDmaChannel()
106 MmioWrite32 (DMA4_CSFI (Channel), DMA4->SourceFrameIndex); in EnableDmaChannel()
110 MmioWrite32 (DMA4_CDEI (Channel), DMA4->DestinationElementIndex); in EnableDmaChannel()
113 MmioWrite32 (DMA4_CDFI (Channel), DMA4->DestinationFrameIndex); in EnableDmaChannel()
[all …]
/device/linaro/bootloader/edk2/ArmPlatformPkg/Drivers/PL180MciDxe/
DPL180Mci.c92 MmioWrite32 (MCI_DATA_TIMER_REG, 0xFFFFFFF); in MciPrepareDataPath()
93 MmioWrite32 (MCI_DATA_LENGTH_REG, MMCI0_BLOCKLEN); in MciPrepareDataPath()
98MmioWrite32 (MCI_DATA_CTL_REG, MCI_DATACTL_ENABLE | MCI_DATACTL_DMA_ENABLE | TransferDirection | (… in MciPrepareDataPath()
100MmioWrite32 (MCI_DATA_CTL_REG, MCI_DATACTL_ENABLE | MCI_DATACTL_DMA_ENABLE | TransferDirection | M… in MciPrepareDataPath()
124 MmioWrite32 (MCI_DATA_TIMER_REG, 0xFFFFFFF); in MciSendCommand()
125 MmioWrite32 (MCI_DATA_LENGTH_REG, 64); in MciSendCommand()
127MmioWrite32 (MCI_DATA_CTL_REG, MCI_DATACTL_ENABLE | MCI_DATACTL_CARD_TO_CONT | GetPow2BlockLen (64… in MciSendCommand()
129MmioWrite32 (MCI_DATA_CTL_REG, MCI_DATACTL_ENABLE | MCI_DATACTL_CARD_TO_CONT | MCI_DATACTL_STREAM_… in MciSendCommand()
132 MmioWrite32 (MCI_DATA_TIMER_REG, 0xFFFFFFF); in MciSendCommand()
134 MmioWrite32 (MCI_DATA_LENGTH_REG, 8); in MciSendCommand()
[all …]
/device/linaro/bootloader/OpenPlatformPkg/Platforms/Hisilicon/HiKey960/HiKey960UsbDxe/
DHiKey960UsbDxe.c80 MmioWrite32 ( in HiKey960UsbPhyCrSetAddr()
88 MmioWrite32 (USB3OTG_PHY_CR_CTRL, 0); in HiKey960UsbPhyCrSetAddr()
100 MmioWrite32 (USB3OTG_PHY_CR_CTRL, USB3OTG_PHY_CR_READ); in HiKey960UsbPhyCrRead()
120 MmioWrite32 (USB3OTG_PHY_CR_CTRL, 0); in HiKey960UsbPhyCrRead()
134 MmioWrite32 (USB3OTG_PHY_CR_CTRL, Data); in HiKey960UsbPhyCrWrite()
138 MmioWrite32 (USB3OTG_PHY_CR_CTRL, Data); in HiKey960UsbPhyCrWrite()
141 MmioWrite32 (USB3OTG_PHY_CR_CTRL, 0); in HiKey960UsbPhyCrWrite()
142 MmioWrite32 (USB3OTG_PHY_CR_CTRL, USB3OTG_PHY_CR_WRITE); in HiKey960UsbPhyCrWrite()
154 MmioWrite32 (USB3OTG_CTRL4, USB_EYE_PARAM); in HiKey960UsbSetEyeDiagramParam()
169 MmioWrite32 (USB3OTG_CTRL6, Data); in HiKey960UsbSetEyeDiagramParam()
[all …]
/device/linaro/bootloader/edk2/Omap35xxPkg/Library/DebugAgentTimerLib/
DDebugAgentTimerLib.c43 MmioWrite32 (INTCPS_ILR (gVector), 1); in EnableInterruptSource()
48 MmioWrite32 (INTCPS_MIR_CLEAR(Bank), Bit); in EnableInterruptSource()
62 MmioWrite32 (INTCPS_MIR_SET(Bank), Bit); in DisableInterruptSource()
121 MmioWrite32 (gTCLR, TCLR_ST_OFF); in DebugAgentTimerSetPeriod()
130 MmioWrite32 (gTLDR, LoadValue); in DebugAgentTimerSetPeriod()
131 MmioWrite32 (gTCRR, LoadValue); in DebugAgentTimerSetPeriod()
134 MmioWrite32 (gTIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_ENABLE | TIER_MAT_IT_DISABLE); in DebugAgentTimerSetPeriod()
137 MmioWrite32 (gTCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON); in DebugAgentTimerSetPeriod()
156 MmioWrite32 (gTISR, TISR_CLEAR_ALL); in DebugAgentTimerEndOfInterrupt()
161 MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWFIQAGR); in DebugAgentTimerEndOfInterrupt()
/device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Pv660/Drivers/SasInitDxe/
DSasV1Init.c48 MmioWrite32(SAS0_BASE + SAS0_RESET, SAS_RESET_VALUE); in SasInit_0()
49 MmioWrite32(SAS0_BASE + SAS0_DISABLE_CLK, SAS_RESET_VALUE); in SasInit_0()
53 MmioWrite32(SAS0_BASE + SAS0_DERESET, SAS_RESET_VALUE); in SasInit_0()
54 MmioWrite32(SAS0_BASE + SAS0_ENABLE_CLK, SAS_RESET_VALUE); in SasInit_0()
71 MmioWrite32(SAS1_BASE + SAS1_RESET, SAS_RESET_VALUE); in SasInit_1()
72 MmioWrite32(SAS1_BASE + SAS1_DISABLE_CLK, SAS_RESET_VALUE); in SasInit_1()
76 MmioWrite32(SAS1_BASE + SAS1_DERESET, SAS_RESET_VALUE); in SasInit_1()
77 MmioWrite32(SAS1_BASE + SAS1_ENABLE_CLK, SAS_RESET_VALUE); in SasInit_1()
/device/linaro/bootloader/OpenPlatformPkg/Platforms/Hisilicon/D03/Library/OemMiscLib2P/
DOemMiscLib2PHi1610.c82 MmioWrite32(0xd0002180, 0x3); in OemPostEndIndicator()
83 MmioWrite32(0xd0002194, 0xa4); in OemPostEndIndicator()
84 MmioWrite32(0xd0000a54, 0x1); in OemPostEndIndicator()
88 MmioWrite32(0xd0002108, 0x1); in OemPostEndIndicator()
89 MmioWrite32(0xd0002114, 0x1); in OemPostEndIndicator()
90 MmioWrite32(0xd0002120, 0x1); in OemPostEndIndicator()
91 MmioWrite32(0xd0003108, 0x1); in OemPostEndIndicator()
/device/linaro/bootloader/edk2/ArmPkg/Drivers/ArmGic/GicV2/
DArmGicV2SecLib.c42 MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0); in ArmGicV2SetupNonSecure()
60 MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff); in ArmGicV2SetupNonSecure()
64 MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff); in ArmGicV2SetupNonSecure()
68 MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask); in ArmGicV2SetupNonSecure()
78 MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF); in ArmGicV2EnableInterruptInterface()
83 MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, in ArmGicV2EnableInterruptInterface()
99MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, ControlValue & ~(ARM_GIC_ICCICR_ENABLE_SE… in ArmGicV2DisableInterruptInterface()
DArmGicV2NonSecLib.c30 MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x1); in ArmGicV2EnableInterruptInterface()
40 MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x0); in ArmGicV2DisableInterruptInterface()
41 MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x0); in ArmGicV2DisableInterruptInterface()
/device/linaro/bootloader/OpenPlatformPkg/Platforms/Hisilicon/HiKey960/HiKey960Dxe/
DHiKey960Dxe.c119 MmioWrite32 (CRG_PERRSTEN2, PERRSTEN2_HKADCSSI); in InitAdc()
122 MmioWrite32 (CRG_PERRSTDIS2, PERRSTEN2_HKADCSSI); in InitAdc()
125 MmioWrite32 (CRG_PERDIS2, PEREN2_HKADCSSI); in InitAdc()
127 MmioWrite32 (CRG_PEREN2, PEREN2_HKADCSSI); in InitAdc()
146 MmioWrite32 (HKADC_WR01_DATA, HKADC_WR01_VALUE | Channel); in AdcGetAdc()
147 MmioWrite32 (HKADC_WR23_DATA, HKADC_WR23_VALUE); in AdcGetAdc()
148 MmioWrite32 (HKADC_WR45_DATA, HKADC_WR45_VALUE); in AdcGetAdc()
150 MmioWrite32 (HKADC_WR_NUM, HKADC_WR_NUM_VALUE); in AdcGetAdc()
152 MmioWrite32 (HKADC_DELAY01, HKADC_CHANNEL0_DELAY01_VALUE); in AdcGetAdc()
153 MmioWrite32 (HKADC_DELAY23, HKADC_DELAY23_VALUE); in AdcGetAdc()
[all …]
/device/linaro/bootloader/edk2/Omap35xxPkg/InterruptDxe/
DHardwareInterrupt.c56 MmioWrite32 (INTCPS_MIR(0), 0xFFFFFFFF); in ExitBootServicesEvent()
57 MmioWrite32 (INTCPS_MIR(1), 0xFFFFFFFF); in ExitBootServicesEvent()
58 MmioWrite32 (INTCPS_MIR(2), 0xFFFFFFFF); in ExitBootServicesEvent()
59 MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR); in ExitBootServicesEvent()
137 MmioWrite32 (INTCPS_MIR_CLEAR(Bank), Bit); in EnableInterruptSource()
171 MmioWrite32 (INTCPS_MIR_SET(Bank), Bit); in DisableInterruptSource()
239 MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR); in EndOfInterrupt()
269 MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR); in IrqInterruptHandler()
279 MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR); in IrqInterruptHandler()
323 MmioWrite32 (INTCPS_MIR(0), 0xFFFFFFFF); in InterruptDxeInitialize()
[all …]
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/I2CLibDxe/
DI2CLib.c224MmioWrite32 ((UINTN) (PciMmBase + R_PCH_LPSS_I2C_BAR), (UINT32) (mLpssPciDeviceList[I2cControllerI… in ProgramPciLpssI2C()
230MmioWrite32 ((UINTN) (PciMmBase + R_PCH_LPSS_I2C_BAR1), (UINT32) (mLpssPciDeviceList[I2cController… in ProgramPciLpssI2C()
242MmioWrite32 (mLpssPciDeviceList[I2cControllerIndex+1].Bar0 + R_PCH_LPIO_I2C_MEM_RESETS,(B_PCH_LPIO… in ProgramPciLpssI2C()
247MmioWrite32 (mLpssPciDeviceList[I2cControllerIndex+1].Bar0 + R_PCH_LPSS_I2C_MEM_PCP,0x80020003);//… in ProgramPciLpssI2C()
296 MmioWrite32 ( mI2CBaseAddress + R_IC_ENABLE, 0 ); in I2cDisable()
325 MmioWrite32 (mI2CBaseAddress + R_IC_ENABLE, 1); in I2cEnable()
355 MmioWrite32 ( mI2CBaseAddress + R_IC_SS_SCL_HCNT, (UINT16)0x214 ); in I2cBusFrequencySet()
356 MmioWrite32 ( mI2CBaseAddress + R_IC_SS_SCL_LCNT, (UINT16)0x272 ); in I2cBusFrequencySet()
361 MmioWrite32 ( mI2CBaseAddress + R_IC_FS_SCL_HCNT, (UINT16)0x50 ); in I2cBusFrequencySet()
362 MmioWrite32 ( mI2CBaseAddress + R_IC_FS_SCL_LCNT, (UINT16)0xAD ); in I2cBusFrequencySet()
[all …]
/device/linaro/bootloader/OpenPlatformPkg/Drivers/Mmc/DwEmmcDxe/
DDwEmmcDxe.c123 MmioWrite32 (DWEMMC_CMD, Data); in DwEmmcUpdateClock()
164 MmioWrite32 (DWEMMC_CLKENA, 0); in DwEmmcSetClock()
168 MmioWrite32 (DWEMMC_CLKDIV, Divider); in DwEmmcSetClock()
173 MmioWrite32 (DWEMMC_CLKENA, 1); in DwEmmcSetClock()
174 MmioWrite32 (DWEMMC_CLKSRC, 0); in DwEmmcSetClock()
193 MmioWrite32 (DWEMMC_PWREN, 1); in DwEmmcNotifyState()
197 MmioWrite32 (DWEMMC_CTRL, Data); in DwEmmcNotifyState()
209 MmioWrite32 (DWEMMC_RINTSTS, ~0); in DwEmmcNotifyState()
210 MmioWrite32 (DWEMMC_INTMASK, 0); in DwEmmcNotifyState()
211 MmioWrite32 (DWEMMC_TMOUT, ~0); in DwEmmcNotifyState()
[all …]
/device/linaro/bootloader/OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKeyDxe/
DHiKeyDxe.c68 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART1); in UartInit()
69 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART1); in UartInit()
71 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART2); in UartInit()
72 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART2); in UartInit()
74 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART3); in UartInit()
75 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART3); in UartInit()
77 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART4); in UartInit()
78 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART4); in UartInit()
81 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS0, PERIPH_RST0_MMC2); in UartInit()
85 MmioWrite32 (PMUSSI_REG(0x1c), Val); in UartInit()
[all …]
/device/linaro/bootloader/edk2/Omap35xxPkg/Library/Omap35xxTimerLib/
DTimerLib.c40 MmioWrite32 (TimerBaseAddress + GPTIMER_TCRR, 0x00000000); in TimerConstructor()
41 MmioWrite32 (TimerBaseAddress + GPTIMER_TLDR, 0x00000000); in TimerConstructor()
44MmioWrite32 (TimerBaseAddress + GPTIMER_TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_DISABLE | TIER_MA… in TimerConstructor()
47 MmioWrite32 (TimerBaseAddress + GPTIMER_TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON); in TimerConstructor()
50 MmioWrite32 (WDTIMER2_BASE + WSPR, 0xAAAA); in TimerConstructor()
52 MmioWrite32 (WDTIMER2_BASE + WSPR, 0x5555); in TimerConstructor()
/device/linaro/bootloader/edk2/ArmPlatformPkg/Drivers/ArmTrustZone/
DArmTrustZone.c44 MmioWrite32 ((UINTN)TzpcBase + TZPC_DECPROT0_SET_REG + (TzpcId * 0x0C), Bits); in TZPCSetDecProtBits()
63 MmioWrite32 ((UINTN)TzpcBase + TZPC_DECPROT0_CLEAR_REG + (TzpcId * 0x0C), Bits); in TZPCClearDecProtBits()
101 MmioWrite32((UINTN)(Region), LowAddress&0xFFFF8000); in TZASCSetRegion()
102 MmioWrite32((UINTN)(Region+1), HighAddress); in TZASCSetRegion()
103 MmioWrite32((UINTN)(Region+2), ((Security & 0xF) <<28) | ((Size & 0x3F) << 1) | (Enabled & 0x1)); in TZASCSetRegion()
/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/
DPchAccess.h433MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MS…
434MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode <…
440MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MS…
441MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode <…
443MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MS…
444MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR ), (UINT32) (Dbuff & AndDa…
445MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((WriteOpCode …
450MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MS…
451MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode <…
453MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MS…
[all …]
/device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Pv660/Drivers/IoInitDxe/
DSmmu.c234 MmioWrite32 (Base, Value); in writel_relaxed()
281 MmioWrite32 (Base + SMMU_RINT_GFSR, Value); in SmmuInit()
284 MmioWrite32 (Base + SMMU_CFG_GFIM, 0xFFFFFFFF); in SmmuInit()
288 MmioWrite32 (Base + SMMU_CFG_CBF, Value); in SmmuInit()
292 MmioWrite32 (Base + SMMU_RINT_CB_FSR(Index), FSR_FAULT); in SmmuInit()
312 MmioWrite32 ((UINTN)Table + SMMU_CB_S1CTBAR(Index), 0); in SmmuCreateS2Cbt()
313 MmioWrite32 ((UINTN)Table + SMMU_CB_S2CR(Index), S2CR_TYPE_BYPASS); in SmmuCreateS2Cbt()
353MmioWrite32 (Smmu->S2Cbt + SMMU_CB_S1CTBAR(SMMU_OS_VMID), (UINT32) RShiftU64 ((UINT64)S1, SMMU_S1C… in SmmuConfigSwitch()
356 MmioWrite32 ((UINTN)S1 + SMMU_CB(0) + SMMU_S1_SCTLR, SCTLR_CACHE_WBRAWA); in SmmuConfigSwitch()
358 MmioWrite32 ((UINTN)S1 + SMMU_CB(1) + SMMU_S1_SCTLR, SCTLR_CACHE_NGNRE); in SmmuConfigSwitch()
[all …]
/device/linaro/bootloader/OpenPlatformPkg/Platforms/Hisilicon/D02/EarlyConfigPeim/
DEarlyConfigPeim.c44 MmioWrite32 (TIMER_SUBCTRL_BASE + SC_TM_CLKEN0_REG, 0x3); in PlatformTimerStart()
78 MmioWrite32(ALG_BASE + SC_ITS_M3_INT_MUX_SEL_REG, SC_ITS_M3_INT_MUX_SEL_VALUE); in EarlyConfigEntry()
84 MmioWrite32(PERI_SUB_CTRL_BASE + SYS_APB_IF_BASE + TSENSOR_REG, TSENSOR_CONFIG_VALUE); in EarlyConfigEntry()
85 MmioWrite32(ALG_BASE + SC_HLLC_RESET_DREQ_REG, SC_HLLC_RESET_DREQ_VALUE); in EarlyConfigEntry()
/device/linaro/bootloader/edk2/Omap35xxPkg/LcdGraphicsOutputDxe/
DLcdGraphicsOutputDxe.c145 MmioWrite32 (CM_ICLKEN_DSS, EN_DSS); in DssSetMode()
151 MmioWrite32 (CM_CLKSEL_DSS, 0x1000 | (LcdModes[ModeNumber].DssDivisor)); in DssSetMode()
160 MmioWrite32(DSS_SYSCONFIG, DSS_SOFTRESET); in DssSetMode()
164 MmioWrite32 (DISPC_SIZE_LCD, in DssSetMode()
168 MmioWrite32 (DISPC_TIMING_H, in DssSetMode()
173 MmioWrite32 (DISPC_TIMING_V, in DssSetMode()
184 MmioWrite32(DISPC_DIVISOR, ((1 << 16) | LcdModes[ModeNumber].DispcDivisor) ); in DssSetMode()
187 MmioWrite32 (DISPC_GFX_PRELD, 0x2D8); in DssSetMode()
188 MmioWrite32 (DISPC_GFX_BA0, VramBaseAddress); in DssSetMode()
189 MmioWrite32 (DISPC_GFX_SIZE, in DssSetMode()
[all …]
/device/linaro/bootloader/OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKeyUsbDxe/
DHiKeyUsbDxe.c52 MmioWrite32 (0xf8001864, 1); in HiKeyDetectUsbModeInit()
53 MmioWrite32 (0xf8001868, 1); in HiKeyDetectUsbModeInit()
109 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CLKEN0, BIT4); in HiKeyUsbPhyInit()
117 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS0, Data); in HiKeyUsbPhyInit()
127 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CTRL4, Value); in HiKeyUsbPhyInit()
141 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CTRL5, Value); in HiKeyUsbPhyInit()
155 MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CTRL5, Data); in HiKeyUsbPhyInit()
157 MmioWrite32 (PERI_CTRL_BASE + 0x018, 0x70533483); //EYE_PATTERN in HiKeyUsbPhyInit()
/device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Drivers/PciHostBridgeDxe/
DPciRootBridgeIo.c644 MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index); in SetAtuConfig0RW()
645 MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Private->Ecam)); in SetAtuConfig0RW()
646MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(Private->Ecam) >> … in SetAtuConfig0RW()
647 MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit); in SetAtuConfig0RW()
648 MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0); in SetAtuConfig0RW()
649 MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0); in SetAtuConfig0RW()
650 MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_CONFIG0); in SetAtuConfig0RW()
651 MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_SHIIF_MODE); in SetAtuConfig0RW()
670 MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index); in SetAtuConfig1RW()
671 MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_CONFIG1); in SetAtuConfig1RW()
[all …]

1234567